Remove dead and redundant code (#124)

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

rtl/cve2_controller.sv

@@ -58,7 +58,6 @@ module cve2_controller #(
   input  logic [31:0]           lsu_addr_last_i,         // for mtval
   input  logic                  load_err_i,
   input  logic                  store_err_i,
-  output logic                  id_exception_o,          // Instruction in ID taking an exception
 
   // jump/branch signals
   input  logic                  branch_set_i,            // branch set signal (branch definitely
@@ -215,8 +214,6 @@ module cve2_controller #(
   // LSU exception requests
   assign exc_req_lsu = store_err_i | load_err_i;
 
-  assign id_exception_o = exc_req_d;
-
   // special requests: special instructions, pipeline flushes, exceptions...
   // All terms in these expressions are qualified by instr_valid_i except exc_req_lsu which can come
   // from the Writeback stage with no instr_valid_i from the ID stage

rtl/cve2_core.sv

@@ -960,7 +960,7 @@ module cve2_core import cve2_pkg::*; #(
   // Factor in exceptions taken in ID so RVFI tracking picks up flushed instructions that took
   // a trap
   assign rvfi_id_done = instr_id_done | (id_stage_i.controller_i.rvfi_flush_next &
-                                         id_stage_i.controller_i.id_exception_o);
+                                         id_stage_i.controller_i.exc_req_d);
 
   // Without writeback stage first RVFI stage is output stage so simply valid the cycle after
   // instruction leaves ID/EX (and so has retired)

rtl/cve2_id_stage.sv

@@ -494,7 +494,6 @@ module cve2_id_stage #(
     .lsu_addr_last_i(lsu_addr_last_i),
     .load_err_i     (lsu_load_err_i),
     .store_err_i    (lsu_store_err_i),
-    .id_exception_o (),
     // jump/branch control
     .branch_set_i     (branch_set),
     .branch_not_set_i (branch_not_set),