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[rtl] Change misa for RV32E

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Following RISC-V privileged architecture version 1.11,
the "E" bit of misa should return the complement of the "I" bit.

Set the "I" bit only if RV32E is not used.

Closes lowRISC/ibex#612.
This commit is contained in:
Tobias Wölfel 2020-02-20 12:39:23 +01:00 • committed by Philipp Wagner
parent f90faa6ca3
commit 7c9c7599d2
1 changed files with 12 additions and 12 deletions
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24
rtl/ibex_cs_registers.sv
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@ -105,18 +105,18 @@ module ibex_cs_registers #(
// misa
localparam logic [1:0] MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32
localparam logic [31:0] MISA_VALUE =
(0 << 0) // A - Atomic Instructions extension
| (1 << 2) // C - Compressed extension
| (0 << 3) // D - Double precision floating-point extension
| (32'(RV32E) << 4) // E - RV32E base ISA
| (0 << 5) // F - Single precision floating-point extension
| (1 << 8) // I - RV32I/64I/128I base ISA
| (32'(RV32M) << 12) // M - Integer Multiply/Divide extension
| (0 << 13) // N - User level interrupts supported
| (0 << 18) // S - Supervisor mode implemented
| (1 << 20) // U - User mode implemented
| (0 << 23) // X - Non-standard extensions present
| (32'(MXL) << 30); // M-XLEN
(0 << 0) // A - Atomic Instructions extension
| (1 << 2) // C - Compressed extension
| (0 << 3) // D - Double precision floating-point extension
| (32'(RV32E) << 4) // E - RV32E base ISA
| (0 << 5) // F - Single precision floating-point extension
| (32'(!RV32E) << 8) // I - RV32I/64I/128I base ISA
| (32'(RV32M) << 12) // M - Integer Multiply/Divide extension
| (0 << 13) // N - User level interrupts supported
| (0 << 18) // S - Supervisor mode implemented
| (1 << 20) // U - User mode implemented
| (0 << 23) // X - Non-standard extensions present
| (32'(MXL) << 30); // M-XLEN
typedef struct packed {
logic mie;