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Possibility to enter debug when never started yet

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This commit is contained in:
Andreas Traber 2016-05-06 16:54:20 +02:00
parent 3f53888355
commit 7de2b84e44
3 changed files with 8 additions and 5 deletions
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5
controller.sv
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@ -192,6 +192,11 @@ module riscv_controller
if (fetch_enable_i == 1'b1)
ctrl_fsm_ns = BOOT_SET;
else if (dbg_req_i) begin
// just go to debug even when we did not yet get a fetch enable
// this means that the NPC will not be set yet
ctrl_fsm_ns = DBG_SIGNAL;
end
end
// copy boot address to instr fetch address

4
cs_registers.sv
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@ -153,8 +153,8 @@ module riscv_cs_registers
// mcause: exception cause
12'h342: csr_rdata_int = {exc_cause[5], 26'b0, exc_cause[4:0]};
// mcpuid: RV32I
12'hF00: csr_rdata_int = 32'h00_00_01_00;
// mcpuid: RV32IM and X
12'hF00: csr_rdata_int = 32'h00_80_11_00;
// mimpid: PULP, anonymous source (no allocated ID yet)
12'hF01: csr_rdata_int = 32'h00_00_80_00;
// mhartid: unique hardware thread id

4
debug_unit.sv
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@ -236,9 +236,7 @@ module riscv_debug_unit
6'b10_0000: begin // Debug Registers, only accessible when in debug
debug_gnt_o = 1'b1; // grant it even when invalid access to not block
if (debug_halted_o) begin
rdata_sel_n = RD_DBGS;
end
rdata_sel_n = RD_DBGS;
end
6'b00_0100: begin // General-Purpose Registers