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Update google_riscv-dv to be14080 (#57)

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Update code from upstream repository https://github.com/google/riscv-
dv to revision be14080425cc3b9a5b33c6c29962893c890c62ee

* Merge pull request #23 from google/dev (taoliug)
* Add privileged CSR implementation configuration (Tao Liu)
This commit is contained in:
taoliug 2019-06-03 15:05:35 -07:00 • committed by GitHub
parent 2782ae9677
commit 7ec87d8044
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GPG key ID: 4AEE18F83AFDEB23
4 changed files with 82 additions and 29 deletions
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2
vendor/google_riscv-dv.lock.hjson vendored
View file

@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/google/riscv-dv
rev: 215e0646ae9909aa0e78d6e91f4f33ed77f95e43
rev: be14080425cc3b9a5b33c6c29962893c890c62ee
}
}

47
vendor/google_riscv-dv/src/riscv_core_setting.sv vendored
View file

@ -75,3 +75,50 @@ int kernel_stack_len = 5000;
// Number of instructions for each kernel program
int kernel_program_instr_cnt = 400;
// ----------------------------------------------------------------------------
// Previleged CSR implementation
// ----------------------------------------------------------------------------
// Implemented previlieged CSR list
privileged_reg_t implemented_csr[$] = {
// User mode CSR
USTATUS, // User status
UIE, // User interrupt-enable register
UTVEC, // User trap-handler base address
USCRATCH, // Scratch register for user trap handlers
UEPC, // User exception program counter
UCAUSE, // User trap cause
UTVAL, // User bad address or instruction
UIP, // User interrupt pending
// Supervisor mode CSR
SSTATUS, // Supervisor status
SEDELEG, // Supervisor exception delegation register
SIDELEG, // Supervisor interrupt delegation register
SIE, // Supervisor interrupt-enable register
STVEC, // Supervisor trap-handler base address
SCOUNTEREN, // Supervisor counter enable
SSCRATCH, // Scratch register for supervisor trap handlers
SEPC, // Supervisor exception program counter
SCAUSE, // Supervisor trap cause
STVAL, // Supervisor bad address or instruction
SIP, // Supervisor interrupt pending
SATP, // Supervisor address translation and protection
// Machine mode mode CSR
MVENDORID, // Vendor ID
MARCHID, // Architecture ID
MIMPID, // Implementation ID
MHARTID, // Hardware thread ID
MSTATUS, // Machine status
MISA, // ISA and extensions
MEDELEG, // Machine exception delegation register
MIDELEG, // Machine interrupt delegation register
MIE, // Machine interrupt-enable register
MTVEC, // Machine trap-handler base address
MCOUNTEREN, // Machine counter enable
MSCRATCH, // Scratch register for machine trap handlers
MEPC, // Machine exception program counter
MCAUSE, // Machine trap cause
MTVAL, // Machine bad address or instruction
MIP // Machine interrupt pending
};

14
vendor/google_riscv-dv/src/riscv_instr_pkg.sv vendored
View file

@ -238,16 +238,9 @@ package riscv_instr_pkg;
INVALID_INSTR
} riscv_instr_name_t;
`include "riscv_core_setting.sv"
// Maximum virtual address bits used by the program
parameter MAX_USED_VADDR_BITS = 30;
// xSTATUS bit mask
parameter bit [XLEN - 1 : 0] MPRV_BIT_MASK = 'h1 << 17;
parameter bit [XLEN - 1 : 0] SUM_BIT_MASK = 'h1 << 18;
parameter bit [XLEN - 1 : 0] MPP_BIT_MASK = 'h3 << 11;
typedef enum bit [4:0] {
ZERO = 5'b00000,
RA,
@ -620,8 +613,15 @@ package riscv_instr_pkg;
STORE_AMO_PAGE_FAULT = 4'hF
} exception_cause_t;
`include "riscv_core_setting.sv"
typedef bit [15:0] program_id_t;
// xSTATUS bit mask
parameter bit [XLEN - 1 : 0] MPRV_BIT_MASK = 'h1 << 17;
parameter bit [XLEN - 1 : 0] SUM_BIT_MASK = 'h1 << 18;
parameter bit [XLEN - 1 : 0] MPP_BIT_MASK = 'h3 << 11;
parameter IMM25_WIDTH = 25;
parameter IMM12_WIDTH = 12;
parameter INSTR_WIDTH = 32;

48
vendor/google_riscv-dv/src/riscv_privileged_common_seq.sv vendored
View file

@ -54,9 +54,7 @@ class riscv_privileged_common_seq extends uvm_sequence;
virtual function void setup_mmode_reg(privileged_mode_t mode, ref riscv_privil_reg regs[$]);
mstatus = riscv_privil_reg::type_id::create("mstatus");
mie = riscv_privil_reg::type_id::create("mie");
mstatus.init_reg(MSTATUS);
mie.init_reg(MIE);
`DV_CHECK_RANDOMIZE_FATAL(mstatus, "cannot randomize mstatus");
if(XLEN==64) begin
mstatus.set_field("UXL", 2'b10);
@ -85,20 +83,22 @@ class riscv_privileged_common_seq extends uvm_sequence;
mstatus.set_field("UIE", riscv_instr_pkg::support_umode_trap);
regs.push_back(mstatus);
// Enable external and timer interrupt
mie.set_field("UEIE", cfg.enable_interrupt);
mie.set_field("SEIE", cfg.enable_interrupt);
mie.set_field("MEIE", cfg.enable_interrupt);
mie.set_field("USIE", cfg.enable_interrupt);
mie.set_field("SSIE", cfg.enable_interrupt);
mie.set_field("MSIE", cfg.enable_interrupt);
regs.push_back(mie);
if (MIE inside {implemented_csr}) begin
mie = riscv_privil_reg::type_id::create("mie");
mie.init_reg(MIE);
mie.set_field("UEIE", cfg.enable_interrupt);
mie.set_field("SEIE", cfg.enable_interrupt);
mie.set_field("MEIE", cfg.enable_interrupt);
mie.set_field("USIE", cfg.enable_interrupt);
mie.set_field("SSIE", cfg.enable_interrupt);
mie.set_field("MSIE", cfg.enable_interrupt);
regs.push_back(mie);
end
endfunction
virtual function void setup_smode_reg(privileged_mode_t mode, ref riscv_privil_reg regs[$]);
sstatus = riscv_privil_reg::type_id::create("sstatus");
sie = riscv_privil_reg::type_id::create("sie");
sstatus.init_reg(SSTATUS);
sie.init_reg(SIE);
`DV_CHECK_RANDOMIZE_FATAL(sstatus, "cannot randomize sstatus")
sstatus.set_field("SPIE", cfg.enable_interrupt);
sstatus.set_field("SIE", cfg.enable_interrupt);
@ -117,25 +117,31 @@ class riscv_privileged_common_seq extends uvm_sequence;
sstatus.set_field("SPP", 1);
regs.push_back(sstatus);
// Enable external and timer interrupt
sie.set_field("UEIE", cfg.enable_interrupt);
sie.set_field("SEIE", cfg.enable_interrupt);
sie.set_field("USIE", cfg.enable_interrupt);
sie.set_field("SSIE", cfg.enable_interrupt);
regs.push_back(sie);
if (SIE inside {implemented_csr}) begin
sie = riscv_privil_reg::type_id::create("sie");
sie.init_reg(SIE);
sie.set_field("UEIE", cfg.enable_interrupt);
sie.set_field("SEIE", cfg.enable_interrupt);
sie.set_field("USIE", cfg.enable_interrupt);
sie.set_field("SSIE", cfg.enable_interrupt);
regs.push_back(sie);
end
endfunction
virtual function void setup_umode_reg(privileged_mode_t mode, ref riscv_privil_reg regs[$]);
ustatus = riscv_privil_reg::type_id::create("ustatus");
uie = riscv_privil_reg::type_id::create("uie");
ustatus.init_reg(USTATUS);
uie.init_reg(UIE);
`DV_CHECK_RANDOMIZE_FATAL(ustatus, "cannot randomize ustatus")
ustatus.set_field("UIE", cfg.enable_interrupt);
ustatus.set_field("UPIE", cfg.enable_interrupt);
regs.push_back(ustatus);
uie.set_field("UEIE", cfg.enable_interrupt);
uie.set_field("USIE", cfg.enable_interrupt);
regs.push_back(uie);
if (UIE inside {implemented_csr}) begin
uie = riscv_privil_reg::type_id::create("uie");
uie.init_reg(UIE);
uie.set_field("UEIE", cfg.enable_interrupt);
uie.set_field("USIE", cfg.enable_interrupt);
regs.push_back(uie);
end
endfunction
virtual function void gen_csr_instr(riscv_privil_reg regs[$], ref string instrs[$]);