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Update google_riscv-dv to 63fa0ca (#241)

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Update code from upstream repository https://github.com/google/riscv-
dv to revision 63fa0ca922ecf10f3cd733d15a0a79a7937a591e

* Merge pull request #74 from google/dev (taoliug)
* Add gcc compile options, fix unaligned load/store (Tao Liu)
* Merge pull request #72 from google/dev (taoliug)
* Properly disable branch instruction in push/pop stack operations
  (Tao Liu)
This commit is contained in:
taoliug 2019-08-14 17:16:44 -07:00 • committed by GitHub
parent e087e32490
commit 7eecbd1b05
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GPG key ID: 4AEE18F83AFDEB23
6 changed files with 69 additions and 27 deletions
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2
vendor/google_riscv-dv.lock.hjson vendored
View file

@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/google/riscv-dv
rev: 07599f689a385794cb73932922008bdbe8131d82
rev: 63fa0ca922ecf10f3cd733d15a0a79a7937a591e
}
}

27
vendor/google_riscv-dv/run.py vendored
View file

@ -127,15 +127,18 @@ def gen(test_list, csr_file, end_signature_addr, isa, simulator,
compile_cmd = []
sim_cmd = ""
compile_cmd, sim_cmd = get_generator_cmd(simulator, simulator_yaml);
if len(test_list) == 0:
return
# Compile the instruction generator
if not sim_only:
logging.info("Building RISC-V instruction generator")
for cmd in compile_cmd:
cmd = re.sub("<out>", os.path.abspath(output_dir), cmd)
cmd = re.sub("<cwd>", cwd, cmd)
cmd = re.sub("<cmp_opts>", cmp_opts, cmd)
logging.debug("Compile command: %s" % cmd)
logging.debug(run_cmd(cmd))
if (not((len(test_list) == 1) and (test_list[0]['test'] == 'riscv_csr_test'))):
logging.info("Building RISC-V instruction generator")
for cmd in compile_cmd:
cmd = re.sub("<out>", os.path.abspath(output_dir), cmd)
cmd = re.sub("<cwd>", cwd, cmd)
cmd = re.sub("<cmp_opts>", cmp_opts, cmd)
logging.debug("Compile command: %s" % cmd)
logging.debug(run_cmd(cmd))
# Run the instruction generator
if not compile_only:
cmd_list = []
@ -176,7 +179,7 @@ def gen(test_list, csr_file, end_signature_addr, isa, simulator,
run_parallel_cmd(cmd_list, timeout_s)
def gcc_compile(test_list, output_dir, isa, mabi):
def gcc_compile(test_list, output_dir, isa, mabi, opts):
"""Use riscv gcc toolchain to compile the assembly program
Args:
@ -194,9 +197,9 @@ def gcc_compile(test_list, output_dir, isa, mabi):
# gcc comilation
cmd = ("%s -march=%s -mabi=%s -static -mcmodel=medany \
-fvisibility=hidden -nostdlib \
-nostartfiles \
-nostartfiles %s \
-Tscripts/link.ld %s -o %s" % \
(get_env_var("RISCV_GCC") ,isa, mabi, asm, elf))
(get_env_var("RISCV_GCC") ,isa, mabi, asm, opts, elf))
logging.info("Compiling %s" % asm)
logging.debug(cmd)
output = subprocess.check_output(cmd.split())
@ -323,6 +326,8 @@ def setup_parser():
help="Compile options for the generator")
parser.add_argument("--sim_opts", type=str, default="",
help="Simulation options for the generator")
parser.add_argument("--gcc_opts", type=str, default="",
help="GCC compile options")
parser.add_argument("--steps", type=str, default="all",
help="Run steps: gen,gcc_compile,iss_sim,iss_cmp")
parser.add_argument("--lsf_cmd", type=str, default="",
@ -397,7 +402,7 @@ def main():
if not args.co:
# Compile the assembly program to ELF, convert to plain binary
if args.steps == "all" or re.match("gcc_compile", args.steps):
gcc_compile(matched_list, output_dir, args.isa, args.mabi)
gcc_compile(matched_list, output_dir, args.isa, args.mabi, args.gcc_opts)
# Run ISS simulation
if args.steps == "all" or re.match("iss_sim", args.steps):

7
vendor/google_riscv-dv/scripts/gen_csr_test.py vendored
View file

@ -31,7 +31,12 @@ import sys
import yaml
import argparse
import random
from bitstring import BitArray as bitarray
try:
from bitstring import BitArray as bitarray
except ImportError as e:
logging.error("Please install bitstring package: sudo apt-get install python3-bitstring")
sys.exit(1)
"""
Defines the test's success/failure values, one of which will be written to

1
vendor/google_riscv-dv/src/riscv_instr_sequence.sv vendored
View file

@ -91,6 +91,7 @@ class riscv_instr_sequence extends uvm_sequence;
// pointer(SP) is reduced by the amount the stack space allocated to this program.
function void gen_stack_enter_instr();
bit allow_branch = ((illegal_instr_pct > 0) || (hint_instr_pct > 0)) ? 1'b0 : 1'b1;
allow_branch &= !cfg.no_branch_jump;
`DV_CHECK_STD_RANDOMIZE_WITH_FATAL(program_stack_len,
program_stack_len inside {[cfg.min_stack_len_per_program : cfg.max_stack_len_per_program]};
// Keep stack len word aligned to avoid unaligned load/store

51
vendor/google_riscv-dv/src/riscv_load_store_instr_lib.sv vendored
View file

@ -86,8 +86,12 @@ class riscv_load_store_base_instr_stream extends riscv_directed_instr_stream;
// Generate each load/store instruction
virtual function void gen_load_store_instr();
bit enable_compressed_load_store;
riscv_rand_instr rand_instr;
riscv_instr_name_t allowed_instr[];
if (rs1_reg inside {[S0 : A5]}) begin
enable_compressed_load_store = 1;
end
if(avail_regs.size() > 0) begin
`DV_CHECK_STD_RANDOMIZE_WITH_FATAL(avail_regs,
unique{avail_regs};
@ -106,30 +110,49 @@ class riscv_load_store_base_instr_stream extends riscv_directed_instr_stream;
if (addr[i][0] == 1'b0) begin
allowed_instr = {LH, LHU, SH, allowed_instr};
end
if (addr[i][1:0] == 2'b00) begin
allowed_instr = {LW, SW, LWU, allowed_instr};
if((offset[i] inside {[0:127]}) && (offset[i] % 4 == 0)) begin
if (!cfg.enable_unaligned_load_store) begin
if (addr[i][1:0] == 2'b00) begin
allowed_instr = {LW, SW, allowed_instr};
if((offset[i] inside {[0:127]}) && (offset[i] % 4 == 0) &&
(RV32C inside {riscv_instr_pkg::supported_isa}) &&
enable_compressed_load_store) begin
allowed_instr = {C_LW, C_SW, allowed_instr};
end
end
if ((XLEN >= 64) && (addr[i][2:0] == 3'b000)) begin
allowed_instr = {LWU, LD, SD, allowed_instr};
if((offset[i] inside {[0:255]}) && (offset[i] % 8 == 0) &&
(RV64C inside {riscv_instr_pkg::supported_isa} &&
enable_compressed_load_store)) begin
allowed_instr = {C_LD, C_SD, allowed_instr};
end
end
end else begin
allowed_instr = {LW, SW, allowed_instr};
if ((offset[i] inside {[0:127]}) && (offset[i] % 4 == 0) &&
(RV32C inside {riscv_instr_pkg::supported_isa}) &&
enable_compressed_load_store) begin
allowed_instr = {C_LW, C_SW, allowed_instr};
end
end
if(addr[i][2:0] == 3'b000) begin
allowed_instr = {LD, SD, allowed_instr};
if((offset[i] inside {[0:255]}) && (offset[i] % 8 == 0)) begin
allowed_instr = {C_LD, C_SD, allowed_instr};
if (XLEN >= 64) begin
allowed_instr = {LWU, LD, SD, allowed_instr};
if ((offset[i] inside {[0:255]}) && (offset[i] % 8 == 0) &&
(RV64C inside {riscv_instr_pkg::supported_isa}) &&
enable_compressed_load_store) begin
allowed_instr = {C_LD, C_SD, allowed_instr};
end
end
end
`DV_CHECK_RANDOMIZE_WITH_FATAL(rand_instr,
solve rs1 before rd;
rs1 == rs1_reg;
if (!cfg.enable_unaligned_load_store) {
instr_name inside {allowed_instr};
} else {
category inside {LOAD, STORE};
}
instr_name inside {allowed_instr};
if(avail_regs.size() > 0) {
rd inside {avail_regs};
}
rd != rs1;
if (num_load_store > 1) {
rd != rs1;
}
)
rand_instr.process_load_store = 0;
rand_instr.imm_str = $sformatf("%0d", offset[i]);

8
vendor/google_riscv-dv/src/riscv_rand_instr.sv vendored
View file

@ -110,6 +110,14 @@ class riscv_rand_instr extends riscv_instr_base;
}
}
// No label is needed if there's no branch/jump instruction
function void post_randomize();
super.post_randomize();
if (cfg.no_branch_jump) begin
has_label = 1'b0;
end
endfunction
`uvm_object_new
endclass