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Align prim_assert.sv with OpenTitan
OpenTitan commit ce974659db7b2b99a75ac407eadefbf2912b8539 slightly modified prim_assert.sv, copy over these changes to align the two implementations.
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73c0b810a9
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1 changed files with 4 additions and 4 deletions
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@ -81,7 +81,7 @@
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// It can be called as a module (or interface) body item.
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`define ASSERT(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
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`ifdef INC_ASSERT \
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__name: assert property (@(posedge __clk) disable iff (__rst !== '0) (__prop)) \
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__name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)) \
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else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop)) \
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`endif
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// Note: Above we use (__rst !== '0) in the disable iff statements instead of
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@ -92,7 +92,7 @@
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// Assert a concurrent property NEVER happens
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`define ASSERT_NEVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
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`ifdef INC_ASSERT \
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__name: assert property (@(posedge __clk) disable iff (__rst !== '0) not (__prop)) \
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__name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) not (__prop)) \
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else `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop)) \
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`endif
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@ -106,7 +106,7 @@
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// Cover a concurrent property
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`define COVER(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
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`ifdef INC_ASSERT \
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__name: cover property (@(posedge __clk) disable iff (__rst !== '0) (__prop)); \
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__name: cover property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)); \
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`endif
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//////////////////////////////
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@ -141,7 +141,7 @@
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// Assume a concurrent property
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`define ASSUME(__name, __prop, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
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`ifdef INC_ASSERT \
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__name: assume property (@(posedge __clk) disable iff (__rst !== '0) (__prop)) \
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__name: assume property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)) \
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else begin `ASSERT_RPT(`PRIM_STRINGIFY(__name), `PRIM_STRINGIFY(__prop)) end \
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`endif
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