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Relocate RegFile from TOP level to CORE level (#95)
Remove dead and related code Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
This commit is contained in:
christian-herber-nxp
GitHub
parent
ec096aafd3
commit
823f596047
9 changed files with 22 additions and 425 deletions
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@ -5,13 +5,6 @@ Getting Started with Ibex
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This page discusses initial steps and requirements to start using Ibex in your design.
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Register File
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-------------
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Ibex comes with three different register file implementations that can be selected using the enumerated parameter ``RegFile`` defined in :file:`rtl/cve2_pkg.sv`.
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Depending on the target technology, either the flip-flop-based ("cve2_pkg::RegFileFF", default), the latch-based ("cve2_pkg::RegFileLatch") or an FPGA-targeted ("cve2_pkg::RegFileFPGA") implementation should be selected.
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For more information about the three register file implementations and their trade-offs, check out :ref:`register-file`.
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Identification CSRs
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-------------------
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@ -18,7 +18,6 @@ Instantiation Template
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.MHPMCounterWidth ( 40 ),
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.RV32E ( 0 ),
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.RV32M ( cve2_pkg::RV32MFast ),
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.RegFile ( cve2_pkg::RegFileFF ),
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.BranchPrediction ( 0 ),
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.RndCnstLfsrSeed ( cve2_pkg::RndCnstLfsrSeedDefault ),
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.RndCnstLfsrPerm ( cve2_pkg::RndCnstLfsrPermDefault ),
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@ -95,11 +94,6 @@ Parameters
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| | | | "cve2_pkg::RV32MFast": 3-4 cycle multiplier, iterative divider |
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| | | | "cve2_pkg::RV32MSingleCycle": 1-2 cycle multiplier, iterative divider |
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+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
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| ``RegFile`` | cve2_pkg::regfile_e | RegFileFF | Register file implementation select: |
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| | | | "cve2_pkg::RegFileFF": Generic flip-flop-based register file |
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| | | | "cve2_pkg::RegFileFPGA": Register file for FPGA targets |
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| | | | "cve2_pkg::RegFileLatch": Latch-based register file for ASIC targets |
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+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
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| ``WritebackStage`` | bit | 0 | *EXPERIMENTAL* - Enables third pipeline stage (writeback) |
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| | | | improving performance of loads and stores |
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+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
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@ -2,79 +2,17 @@
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Register File
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=============
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Source Files: :file:`rtl/cve2_register_file_ff.sv` :file:`rtl/cve2_register_file_fpga.sv` :file:`rtl/cve2_register_file_latch.sv`
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Source File: :file:`rtl/cve2_register_file_ff.sv`
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Ibex has either 31 or 15 32-bit registers if the RV32E extension is disabled or enabled, respectively.
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CVE2 has either 31 or 15 32-bit registers if the RV32E extension is disabled or enabled, respectively.
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Register ``x0`` is statically bound to 0 and can only be read, it does not contain any sequential logic.
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The register file has two read ports and one write port, register file data is available the same cycle a read is requested.
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There is no write to read forwarding path so if one register is being both read and written the read will return the current value rather than the value being written.
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There are three flavors of register file available, each having their own benefits and trade-offs.
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The register file flavor is selected via the enumerated parameter ``RegFile`` defined in :file:`rtl/cve2_pkg.sv`.
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Flip-Flop-Based Register File
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-----------------------------
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The flip-flop-based register file uses regular, positive-edge-triggered flip-flops to implement the registers.
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This makes it the **first choice when simulating the design using Verilator**.
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This implementation can be selected by setting the ``RegFile`` parameter to "cve2_pkg::RegFileFF".
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It is the default selection.
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FPGA Register File
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------------------
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The FPGA register file leverages synchronous-write / asynchronous-read RAM design elements, where available on FPGA targets.
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For Xilinx FPGAs, synthesis results in an implementation using RAM32M primitives. Using this design with a Xilinx Artya7-100 FPGA conserves around 600 Logic LUTs and 1000 flip-flops at the expense of 48 LUTRAMs for the 31-entry register file as compared to the flip-flop-based register file.
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This makes it the **first choice for FPGA synthesis**.
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To select the FPGA register file, set the ``RegFile`` parameter to "cve2_pkg::RegFileFPGA".
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Latch-Based Register File
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-------------------------
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The latch-based register file uses level-sensitive latches to implement the registers.
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This allows for significant area savings compared to an implementation using regular flip-flops and thus makes the latch-based register file the **first choice for ASIC implementations**.
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Simulation of the latch-based register file is possible using commercial tools.
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.. note:: The latch-based register file cannot be simulated using Verilator.
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The latch-based register file can also be used for FPGA synthesis, but this is not recommended as FPGAs usually do not well support latches.
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To select the latch-based register file, set the ``RegFile`` parameter to "cve2_pkg::RegFileLatch".
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In addition, a technology-specific clock gating cell must be provided to keep the clock inactive when the latches are not written.
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This cell must be wrapped in a module called ``prim_clock_gating``.
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For more information regarding the clock gating cell, checkout :ref:`getting-started`.
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.. note:: The latch-based register file requires the gated clock to be enabled in the cycle after the write enable ``we_a_i`` signal was set high.
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This can be achieved by latching ``we_a_i`` in the clock gating cell during the low phase of ``clk_i``.
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The resulting behavior of the latch-based register file is visualized in :numref:`timing`.
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The input data ``wdata_a_i`` is sampled into a flip-flop-based register ``wdata_a_q`` using ``clk_int``.
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The actual latch-based registers ``mem[1]`` and ``mem[2]`` are transparent during high phases of ``mem_clk[1]`` and ``mem_clk[2]``, respectively.
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Their content is sampled from ``wdata_a_q`` on falling edges of these clocks.
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.. wavedrom::
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:name: timing
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:caption: Latch-based register file operation
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{"signal":
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[
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{"name": "clk_i", "wave": "hlhlhlhl"},
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{"name": "we_a_i", "wave": "0.1...0."},
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{"name": "waddr_a_i", "wave": "xx=.=.xx", "data": ["1","2"]},
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{"name": "wdata_a_i", "wave": "xx=.=.xx", "data": ["Data1","Data2"]},
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{"name": "clk_int", "wave": "0...HlHl"},
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{"name": "wdata_a_q", "wave": "xxxx=.=.", "data": ["Data1", "Data2"]},
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{"name": "mem_clk[1]", "wave": "0...hL.."},
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{"name": "mem[1]", "wave": "xxxx=...", "data": ["Data1"]},
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{"name": "mem_clk[2]", "wave": "0.....hL"},
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{"name": "mem[2]", "wave": "xxxxxx=.", "data": ["Data2"]}
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],
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"config": { "hscale": 2 }
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}
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@ -54,15 +54,6 @@ module cve2_core import cve2_pkg::*; #(
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input logic [31:0] data_rdata_i,
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input logic data_err_i,
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// Register file interface
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output logic [4:0] rf_raddr_a_o,
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output logic [4:0] rf_raddr_b_o,
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output logic [4:0] rf_waddr_wb_o,
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output logic rf_we_wb_o,
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output logic [31:0] rf_wdata_wb_ecc_o,
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input logic [31:0] rf_rdata_a_ecc_i,
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input logic [31:0] rf_rdata_b_ecc_i,
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// Interrupt inputs
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input logic irq_software_i,
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input logic irq_timer_i,
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@ -180,7 +171,6 @@ module cve2_core import cve2_pkg::*; #(
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logic [31:0] rf_wdata_lsu;
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logic rf_we_wb;
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logic rf_we_lsu;
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logic rf_ecc_err_comb;
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logic [4:0] rf_waddr_id;
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logic [31:0] rf_wdata_id;
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@ -678,20 +668,6 @@ module cve2_core import cve2_pkg::*; #(
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assign rf_we_wb_o = rf_we_wb;
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assign rf_raddr_b_o = rf_raddr_b;
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begin : gen_no_regfile_ecc
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logic unused_rf_ren_a, unused_rf_ren_b;
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logic unused_rf_rd_a_wb_match, unused_rf_rd_b_wb_match;
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assign unused_rf_ren_a = rf_ren_a;
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assign unused_rf_ren_b = rf_ren_b;
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assign unused_rf_rd_a_wb_match = rf_rd_a_wb_match;
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assign unused_rf_rd_b_wb_match = rf_rd_b_wb_match;
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assign rf_wdata_wb_ecc_o = rf_wdata_wb;
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assign rf_rdata_a = rf_rdata_a_ecc_i;
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assign rf_rdata_b = rf_rdata_b_ecc_i;
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assign rf_ecc_err_comb = 1'b0;
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end
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///////////////////////
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// Crash dump output //
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///////////////////////
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@ -708,9 +684,6 @@ module cve2_core import cve2_pkg::*; #(
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// Minor alert - core is in a recoverable state
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assign alert_minor_o = 1'b0;
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// Major alert - core is unrecoverable
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assign alert_major_o = rf_ecc_err_comb;
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// Explict INC_ASSERT block to avoid unused signal lint warnings were asserts are not included
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`ifdef INC_ASSERT
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// Signals used for assertions only
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@ -753,8 +726,26 @@ module cve2_core import cve2_pkg::*; #(
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////////////////////////
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// RF (Register File) //
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////////////////////////
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`ifdef RVFI
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`endif
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begin : gen_regfile_ff
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cve2_register_file_ff #(
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.RV32E (RV32E),
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.DataWidth (32),
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.WordZeroVal (32'(prim_secded_pkg::SecdedInv3932ZeroWord))
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) register_file_i (
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.clk_i (clk_i),
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.rst_ni(rst_ni),
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.test_en_i (test_en_i),
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.raddr_a_i(rf_raddr_a),
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.rdata_a_o(rf_rdata_a),
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.raddr_b_i(rf_raddr_b),
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.rdata_b_o(rf_rdata_b),
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.waddr_a_i(rf_waddr_wb),
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.wdata_a_i(rf_wdata_wb),
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.we_a_i (rf_we_wb)
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);
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end
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/////////////////////////////////////////
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@ -31,12 +31,6 @@ package cve2_pkg;
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// Parameter Enums //
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/////////////////////
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typedef enum integer {
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RegFileFF = 0,
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RegFileFPGA = 1,
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RegFileLatch = 2
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} regfile_e;
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typedef enum integer {
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RV32MNone = 0,
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RV32MSlow = 1,
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@ -1,82 +0,0 @@
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// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* RISC-V register file
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*
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* Register file with 31 or 15x 32 bit wide registers. Register 0 is fixed to 0.
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*
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* This register file is designed to make FPGA synthesis tools infer RAM primitives. For Xilinx
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* FPGA architectures, it will produce RAM32M primitives. Other vendors have not yet been tested.
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*/
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module cve2_register_file_fpga #(
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parameter bit RV32E = 0,
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parameter int unsigned DataWidth = 32,
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parameter logic [DataWidth-1:0] WordZeroVal = '0
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) (
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// Clock and Reset
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input logic clk_i,
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input logic rst_ni,
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input logic test_en_i,
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input logic dummy_instr_id_i,
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//Read port R1
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input logic [ 4:0] raddr_a_i,
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output logic [DataWidth-1:0] rdata_a_o,
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//Read port R2
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input logic [ 4:0] raddr_b_i,
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output logic [DataWidth-1:0] rdata_b_o,
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// Write port W1
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input logic [ 4:0] waddr_a_i,
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input logic [DataWidth-1:0] wdata_a_i,
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input logic we_a_i
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);
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localparam int ADDR_WIDTH = RV32E ? 4 : 5;
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localparam int NUM_WORDS = 2 ** ADDR_WIDTH;
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logic [DataWidth-1:0] mem[NUM_WORDS];
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logic we; // write enable if writing to any register other than R0
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// async_read a
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assign rdata_a_o = (raddr_a_i == '0) ? '0 : mem[raddr_a_i];
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// async_read b
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assign rdata_b_o = (raddr_b_i == '0) ? '0 : mem[raddr_b_i];
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// we select
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assign we = (waddr_a_i == '0) ? 1'b0 : we_a_i;
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// Note that the SystemVerilog LRM requires variables on the LHS of assignments within
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// "always_ff" to not be written to by any other process. However, to enable the initialization
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// of the inferred RAM32M primitives with non-zero values, below "initial" procedure is needed.
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// Therefore, we use "always" instead of the generally preferred "always_ff" for the synchronous
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// write procedure.
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always @(posedge clk_i) begin : sync_write
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if (we == 1'b1) begin
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mem[waddr_a_i] <= wdata_a_i;
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end
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end : sync_write
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// Make sure we initialize the BRAM with the correct register reset value.
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initial begin
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for (int k = 0; k < NUM_WORDS; k++) begin
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mem[k] = WordZeroVal;
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end
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end
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// Reset not used in this register file version
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logic unused_rst_ni;
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assign unused_rst_ni = rst_ni;
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// Dummy instruction changes not relevant for FPGA implementation
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logic unused_dummy_instr;
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assign unused_dummy_instr = dummy_instr_id_i;
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// Test enable signal not used in FPGA implementation
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logic unused_test_en;
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assign unused_test_en = test_en_i;
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endmodule
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@ -1,135 +0,0 @@
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// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* RISC-V register file
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*
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* Register file with 31 or 15x 32 bit wide registers. Register 0 is fixed to 0.
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* This register file is based on latches and is thus smaller than the flip-flop
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* based RF. It requires a target technology-specific clock gating cell. Use this
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* register file when targeting ASIC synthesis or event-based simulators.
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*/
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module cve2_register_file_latch #(
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parameter bit RV32E = 0,
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parameter int unsigned DataWidth = 32,
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parameter logic [DataWidth-1:0] WordZeroVal = '0
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) (
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// Clock and Reset
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input logic clk_i,
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input logic rst_ni,
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input logic test_en_i,
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input logic dummy_instr_id_i,
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//Read port R1
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input logic [4:0] raddr_a_i,
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output logic [DataWidth-1:0] rdata_a_o,
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//Read port R2
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input logic [4:0] raddr_b_i,
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output logic [DataWidth-1:0] rdata_b_o,
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// Write port W1
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input logic [4:0] waddr_a_i,
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input logic [DataWidth-1:0] wdata_a_i,
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input logic we_a_i
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);
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localparam int unsigned ADDR_WIDTH = RV32E ? 4 : 5;
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localparam int unsigned NUM_WORDS = 2**ADDR_WIDTH;
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logic [DataWidth-1:0] mem[NUM_WORDS];
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logic [NUM_WORDS-1:1] waddr_onehot_a;
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logic [NUM_WORDS-1:1] mem_clocks;
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logic [DataWidth-1:0] wdata_a_q;
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// internal addresses
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logic [ADDR_WIDTH-1:0] raddr_a_int, raddr_b_int, waddr_a_int;
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assign raddr_a_int = raddr_a_i[ADDR_WIDTH-1:0];
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assign raddr_b_int = raddr_b_i[ADDR_WIDTH-1:0];
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assign waddr_a_int = waddr_a_i[ADDR_WIDTH-1:0];
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logic clk_int;
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//////////
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// READ //
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//////////
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assign rdata_a_o = mem[raddr_a_int];
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assign rdata_b_o = mem[raddr_b_int];
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///////////
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// WRITE //
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///////////
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// Global clock gating
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prim_clock_gating cg_we_global (
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.clk_i ( clk_i ),
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.en_i ( we_a_i ),
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.test_en_i ( test_en_i ),
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.clk_o ( clk_int )
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);
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// Sample input data
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// Use clk_int here, since otherwise we don't want to write anything anyway.
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always_ff @(posedge clk_int or negedge rst_ni) begin : sample_wdata
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if (!rst_ni) begin
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wdata_a_q <= WordZeroVal;
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end else begin
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if (we_a_i) begin
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wdata_a_q <= wdata_a_i;
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end
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end
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end
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// Write address decoding
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always_comb begin : wad
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for (int i = 1; i < NUM_WORDS; i++) begin : wad_word_iter
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if (we_a_i && (waddr_a_int == 5'(i))) begin
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waddr_onehot_a[i] = 1'b1;
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end else begin
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waddr_onehot_a[i] = 1'b0;
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end
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end
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end
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// Individual clock gating (if integrated clock-gating cells are available)
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for (genvar x = 1; x < NUM_WORDS; x++) begin : gen_cg_word_iter
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prim_clock_gating cg_i (
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.clk_i ( clk_int ),
|
||||
.en_i ( waddr_onehot_a[x] ),
|
||||
.test_en_i ( test_en_i ),
|
||||
.clk_o ( mem_clocks[x] )
|
||||
);
|
||||
end
|
||||
|
||||
// Actual write operation:
|
||||
// Generate the sequential process for the NUM_WORDS words of the memory.
|
||||
// The process is synchronized with the clocks mem_clocks[i], i = 1, ..., NUM_WORDS-1.
|
||||
for (genvar i = 1; i < NUM_WORDS; i++) begin : g_rf_latches
|
||||
always_latch begin
|
||||
if (mem_clocks[i]) begin
|
||||
mem[i] = wdata_a_q;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
begin : g_normal_r0
|
||||
logic unused_dummy_instr_id;
|
||||
assign unused_dummy_instr_id = dummy_instr_id_i;
|
||||
|
||||
assign mem[0] = WordZeroVal;
|
||||
end
|
||||
|
||||
`ifdef VERILATOR
|
||||
initial begin
|
||||
$display("Latch-based register file not supported for Verilator simulation");
|
||||
$fatal;
|
||||
end
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
|
@ -17,7 +17,6 @@ module cve2_top import cve2_pkg::*; #(
|
|||
parameter int unsigned MHPMCounterWidth = 40,
|
||||
parameter bit RV32E = 1'b0,
|
||||
parameter rv32m_e RV32M = RV32MFast,
|
||||
parameter regfile_e RegFile = RegFileFF,
|
||||
parameter bit WritebackStage = 1'b0,
|
||||
parameter bit BranchPredictor = 1'b0,
|
||||
parameter int unsigned DmHaltAddr = 32'h1A110800,
|
||||
|
|
@ -130,14 +129,6 @@ module cve2_top import cve2_pkg::*; #(
|
|||
logic core_busy_d, core_busy_q;
|
||||
logic clock_en;
|
||||
logic irq_pending;
|
||||
// Core <-> Register file signals
|
||||
logic [4:0] rf_raddr_a;
|
||||
logic [4:0] rf_raddr_b;
|
||||
logic [4:0] rf_waddr_wb;
|
||||
logic rf_we_wb;
|
||||
logic [31:0] rf_wdata_wb_ecc;
|
||||
logic [31:0] rf_rdata_a_ecc, rf_rdata_a_ecc_buf;
|
||||
logic [31:0] rf_rdata_b_ecc, rf_rdata_b_ecc_buf;
|
||||
// Alert signals
|
||||
logic core_alert_major, core_alert_minor;
|
||||
|
||||
|
|
@ -167,16 +158,6 @@ module cve2_top import cve2_pkg::*; #(
|
|||
// Core instantiation //
|
||||
////////////////////////
|
||||
|
||||
prim_buf #(.Width(32)) u_rf_rdata_a_ecc_buf (
|
||||
.in_i (rf_rdata_a_ecc),
|
||||
.out_o(rf_rdata_a_ecc_buf)
|
||||
);
|
||||
|
||||
prim_buf #(.Width(32)) u_rf_rdata_b_ecc_buf (
|
||||
.in_i (rf_rdata_b_ecc),
|
||||
.out_o(rf_rdata_b_ecc_buf)
|
||||
);
|
||||
|
||||
cve2_core #(
|
||||
.PMPEnable (PMPEnable),
|
||||
.PMPGranularity (PMPGranularity),
|
||||
|
|
@ -216,14 +197,6 @@ module cve2_top import cve2_pkg::*; #(
|
|||
.data_rdata_i,
|
||||
.data_err_i,
|
||||
|
||||
.rf_raddr_a_o (rf_raddr_a),
|
||||
.rf_raddr_b_o (rf_raddr_b),
|
||||
.rf_waddr_wb_o (rf_waddr_wb),
|
||||
.rf_we_wb_o (rf_we_wb),
|
||||
.rf_wdata_wb_ecc_o(rf_wdata_wb_ecc),
|
||||
.rf_rdata_a_ecc_i (rf_rdata_a_ecc), //_buf),
|
||||
.rf_rdata_b_ecc_i (rf_rdata_b_ecc), //_buf),
|
||||
|
||||
.irq_software_i,
|
||||
.irq_timer_i,
|
||||
.irq_external_i,
|
||||
|
|
@ -269,69 +242,6 @@ module cve2_top import cve2_pkg::*; #(
|
|||
.core_busy_o (core_busy_d)
|
||||
);
|
||||
|
||||
/////////////////////////////////
|
||||
// Register file Instantiation //
|
||||
/////////////////////////////////
|
||||
|
||||
if (RegFile == RegFileFF) begin : gen_regfile_ff
|
||||
cve2_register_file_ff #(
|
||||
.RV32E (RV32E),
|
||||
.DataWidth (32),
|
||||
.WordZeroVal (32'(prim_secded_pkg::SecdedInv3932ZeroWord))
|
||||
) register_file_i (
|
||||
.clk_i (clk),
|
||||
.rst_ni(rst_ni),
|
||||
|
||||
.test_en_i (test_en_i),
|
||||
|
||||
.raddr_a_i(rf_raddr_a),
|
||||
.rdata_a_o(rf_rdata_a_ecc),
|
||||
.raddr_b_i(rf_raddr_b),
|
||||
.rdata_b_o(rf_rdata_b_ecc),
|
||||
.waddr_a_i(rf_waddr_wb),
|
||||
.wdata_a_i(rf_wdata_wb_ecc),
|
||||
.we_a_i (rf_we_wb)
|
||||
);
|
||||
end else if (RegFile == RegFileFPGA) begin : gen_regfile_fpga
|
||||
cve2_register_file_fpga #(
|
||||
.RV32E (RV32E),
|
||||
.DataWidth (32),
|
||||
.WordZeroVal (32'(prim_secded_pkg::SecdedInv3932ZeroWord))
|
||||
) register_file_i (
|
||||
.clk_i (clk),
|
||||
.rst_ni(rst_ni),
|
||||
|
||||
.test_en_i (test_en_i),
|
||||
|
||||
.raddr_a_i(rf_raddr_a),
|
||||
.rdata_a_o(rf_rdata_a_ecc),
|
||||
.raddr_b_i(rf_raddr_b),
|
||||
.rdata_b_o(rf_rdata_b_ecc),
|
||||
.waddr_a_i(rf_waddr_wb),
|
||||
.wdata_a_i(rf_wdata_wb_ecc),
|
||||
.we_a_i (rf_we_wb)
|
||||
);
|
||||
end else if (RegFile == RegFileLatch) begin : gen_regfile_latch
|
||||
cve2_register_file_latch #(
|
||||
.RV32E (RV32E),
|
||||
.DataWidth (32),
|
||||
.WordZeroVal (32'(prim_secded_pkg::SecdedInv3932ZeroWord))
|
||||
) register_file_i (
|
||||
.clk_i (clk),
|
||||
.rst_ni(rst_ni),
|
||||
|
||||
.test_en_i (test_en_i),
|
||||
|
||||
.raddr_a_i(rf_raddr_a),
|
||||
.rdata_a_o(rf_rdata_a_ecc),
|
||||
.raddr_b_i(rf_raddr_b),
|
||||
.rdata_b_o(rf_rdata_b_ecc),
|
||||
.waddr_a_i(rf_waddr_wb),
|
||||
.wdata_a_i(rf_wdata_wb_ecc),
|
||||
.we_a_i (rf_we_wb)
|
||||
);
|
||||
end
|
||||
|
||||
////////////////////////
|
||||
// Rams Instantiation //
|
||||
////////////////////////
|
||||
|
|
@ -346,10 +256,6 @@ module cve2_top import cve2_pkg::*; #(
|
|||
|
||||
end
|
||||
|
||||
assign alert_major_internal_o = core_alert_major;
|
||||
assign alert_major_bus_o = 1'b0;
|
||||
assign alert_minor_o = core_alert_minor;
|
||||
|
||||
// X checks for top-level outputs
|
||||
`ASSERT_KNOWN(IbexInstrReqX, instr_req_o)
|
||||
`ASSERT_KNOWN_IF(IbexInstrReqPayloadX, instr_addr_o, instr_req_o)
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@ module cve2_top_tracing import cve2_pkg::*; #(
|
|||
parameter bit RV32E = 1'b0,
|
||||
parameter rv32m_e RV32M = RV32MFast,
|
||||
parameter rv32b_e RV32B = RV32BNone,
|
||||
parameter regfile_e RegFile = RegFileFF,
|
||||
parameter bit WritebackStage = 1'b0,
|
||||
parameter bit BranchPredictor = 1'b0,
|
||||
parameter bit DbgTriggerEn = 1'b0,
|
||||
|
|
@ -124,7 +123,6 @@ module cve2_top_tracing import cve2_pkg::*; #(
|
|||
.RV32E ( RV32E ),
|
||||
.RV32M ( RV32M ),
|
||||
.RV32B ( RV32B ),
|
||||
.RegFile ( RegFile ),
|
||||
.BranchPredictor ( BranchPredictor ),
|
||||
.DbgTriggerEn ( DbgTriggerEn ),
|
||||
.DbgHwBreakNum ( DbgHwBreakNum ),
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue