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[syn] Update path to prim_assert

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- Also remove unsigned keyword stripping which is no longer required

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit is contained in:
Tom Roberts 2020-06-05 17:42:52 +01:00 • committed by Tom Roberts
parent bfa531c039
commit 85ce3874eb
2 changed files with 2 additions and 8 deletions
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2
formal/Makefile
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@ -14,7 +14,7 @@ OUTDIR := build
# Source directory relative to this Makefile
SRC_DIR := ../rtl
# Include directory relative to this Makefile
INC_DIR := ../shared/rtl
INC_DIR := ../vendor/lowrisc_ip/prim/rtl
# SystemVerilog sources of Ibex
SRCS_SV ?= $(SRC_DIR)/ibex_alu.sv \

8
syn/syn_yosys.sh
View file

@ -31,15 +31,9 @@ for file in ../rtl/*.sv; do
sv2v \
--define=SYNTHESIS \
../rtl/*_pkg.sv \
-I../shared/rtl \
-I../vendor/lowrisc_ip/prim/rtl \
$file \
> $LR_SYNTH_OUT_DIR/generated/${module}.v
# TODO: eventually remove below hack. It removes "unsigned" from params
# because Yosys doesn't support unsigned parameters
sed -i 's/parameter unsigned/parameter/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/localparam unsigned/localparam/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
sed -i 's/reg unsigned/reg/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
done
# remove generated *pkg.v files (they are empty files and not needed)