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Move hwloop regs into ID stage, WIP

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This commit is contained in:
Sven Stucki 2015-09-03 13:39:11 +02:00
parent 77ef44a82f
commit 87e2eec128
3 changed files with 40 additions and 76 deletions
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23
ex_stage.sv
View file

@ -64,10 +64,6 @@ module ex_stage
input logic [31:0] regfile_rb_data_i,
input logic hwloop_wb_mux_sel_i,
input logic [31:0] hwloop_pc_plus4_i,
input logic [31:0] hwloop_cnt_i,
// CSR access
input logic csr_access_i,
input logic [31:0] csr_rdata_i,
@ -77,10 +73,6 @@ module ex_stage
output logic regfile_we_wb_o,
output logic [31:0] regfile_rb_data_wb_o,
output logic [31:0] hwloop_start_data_o,
output logic [31:0] hwloop_end_data_o,
output logic [31:0] hwloop_cnt_data_o,
// Forwarding ports : to ID stage
output logic [4:0] regfile_alu_waddr_fw_o,
output logic regfile_alu_we_fw_o,
@ -113,21 +105,6 @@ module ex_stage
regfile_alu_wdata_fw_o = csr_rdata_i;
end
// hwloop mux. selects the right data to be sent to the hwloop registers (start/end-address and counter)
always_comb
begin : hwloop_start_mux
case (hwloop_wb_mux_sel_i)
1'b0: hwloop_start_data_o = hwloop_pc_plus4_i;
1'b1: hwloop_start_data_o = alu_result;
endcase
end
// assign alu result to hwloop end data
assign hwloop_end_data_o = alu_result;
// assign hwloop mux. selects the right data to be sent to the hwloop registers (start/end-address and counter)
assign hwloop_cnt_data_o = hwloop_cnt_i;
// Branch is taken when result[0] == 1'b1
assign branch_decision_o = alu_flag;
assign jump_target_o = alu_operand_c_i;

55
id_stage.sv
View file

@ -701,25 +701,50 @@ module id_stage
//////////////////////////////////////////////////////////////////////////
hwloop_controller hwloop_controller_i
(
// from ID stage
.enable_i ( hwloop_enable ),
.current_pc_i ( current_pc_if_i ),
(
// from ID stage
.enable_i ( hwloop_enable ),
// to ID controller
.hwloop_jump_o ( hwloop_jump ),
.current_pc_i ( current_pc_if_i ),
// to if stage
.hwloop_targ_addr_o ( hwloop_targ_addr_o ),
// to ID controller
.hwloop_jump_o ( hwloop_jump ),
// from hwloop_regs
.hwloop_start_addr_i ( hwloop_start_addr_i ),
.hwloop_end_addr_i ( hwloop_end_addr_i ),
.hwloop_counter_i ( hwloop_counter_i ),
// to if stage
.hwloop_targ_addr_o ( hwloop_targ_addr_o ),
// to hwloop_regs
.hwloop_dec_cnt_o ( hwloop_dec_cnt_o )
);
// from hwloop_regs
.hwloop_start_addr_i ( hwloop_start_addr_i ),
.hwloop_end_addr_i ( hwloop_end_addr_i ),
.hwloop_counter_i ( hwloop_counter_i ),
// to hwloop_regs
.hwloop_dec_cnt_o ( hwloop_dec_cnt_o )
);
hwloop_regs hwloop_regs_i
(
.clk ( clk ),
.rst_n ( rst_n ),
// from ex stage
.hwloop_start_data_i ( hwlp_start_data_ex ),
.hwloop_end_data_i ( hwlp_end_data_ex ),
.hwloop_cnt_data_i ( hwlp_cnt_data_ex ),
.hwloop_we_i ( hwlp_we_ex ),
.hwloop_regid_i ( hwlp_regid_ex ),
// from controller
.stall_id_i ( stall_id ),
// to hwloop controller
.hwloop_start_addr_o ( hwlp_start_addr ),
.hwloop_end_addr_o ( hwlp_end_addr ),
.hwloop_counter_o ( hwlp_counter ),
// from hwloop controller
.hwloop_dec_cnt_i ( hwlp_dec_cnt )
);
/////////////////////////////////////////////////////////////////////////////////

38
riscv_core.sv
View file

@ -461,11 +461,6 @@ module riscv_core
.regfile_alu_we_i ( regfile_alu_we_ex ),
.regfile_alu_waddr_i ( regfile_alu_waddr_ex ),
// From ID stage: hwloop wb reg signals
.hwloop_wb_mux_sel_i ( hwlp_wb_mux_sel_ex ),
.hwloop_pc_plus4_i ( current_pc_id ),
.hwloop_cnt_i ( hwlp_cnt_ex ),
//From ID stage.Controller
.regfile_rb_data_i ( regfile_rb_data_ex ),
@ -474,11 +469,6 @@ module riscv_core
.regfile_we_wb_o ( regfile_we_wb ),
.regfile_rb_data_wb_o ( regfile_rb_data_wb ),
// To hwloop regs
.hwloop_start_data_o ( hwlp_start_data_ex ),
.hwloop_end_data_o ( hwlp_end_data_ex ),
.hwloop_cnt_data_o ( hwlp_cnt_data_ex ),
// To IF: Jump and branch target and decision
.jump_target_o ( jump_target_ex ),
.branch_decision_o ( branch_decision ),
@ -596,34 +586,6 @@ module riscv_core
assign dbg_rdata = (dbg_sp_mux == 1'b0) ? dbg_reg_rdata : csr_rdata;
//////////////////////////////////////////////
// Hardware Loop Registers //
//////////////////////////////////////////////
hwloop_regs hwloop_regs_i
(
.clk ( clk ),
.rst_n ( rst_n ),
// from ex stage
.hwloop_start_data_i ( hwlp_start_data_ex ),
.hwloop_end_data_i ( hwlp_end_data_ex ),
.hwloop_cnt_data_i ( hwlp_cnt_data_ex ),
.hwloop_we_i ( hwlp_we_ex ),
.hwloop_regid_i ( hwlp_regid_ex ),
// from controller
.stall_id_i ( stall_id ),
// to hwloop controller
.hwloop_start_addr_o ( hwlp_start_addr ),
.hwloop_end_addr_o ( hwlp_end_addr ),
.hwloop_counter_o ( hwlp_counter ),
// from hwloop controller
.hwloop_dec_cnt_i ( hwlp_dec_cnt )
);
/////////////////////////////////////////////////////////////
// ____ _____ ____ _ _ ____ _ _ _ _ ___ _____ //
// | _ \| ____| __ )| | | |/ ___| | | | | \ | |_ _|_ _| //