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commenting fcov macros

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This commit is contained in:
Davide Schiavone 2022-08-11 08:42:54 +02:00
parent afe6c56771
commit 89ef78a803
4 changed files with 20 additions and 20 deletions
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16
rtl/ibex_controller.sv
View file

@ -8,7 +8,7 @@
*/
`include "prim_assert.sv"
`include "dv_fcov_macros.svh"
//`include "dv_fcov_macros.svh"
module ibex_controller #(
parameter bit WritebackStage = 0,
@ -828,13 +828,13 @@ module ibex_controller #(
// FCOV //
//////////
`DV_FCOV_SIGNAL(logic, interrupt_taken, (ctrl_fsm_cs != IRQ_TAKEN) & (ctrl_fsm_ns == IRQ_TAKEN))
`DV_FCOV_SIGNAL(logic, debug_entry_if,
(ctrl_fsm_cs != DBG_TAKEN_IF) & (ctrl_fsm_ns == DBG_TAKEN_IF))
`DV_FCOV_SIGNAL(logic, debug_entry_id,
(ctrl_fsm_cs != DBG_TAKEN_ID) & (ctrl_fsm_ns == DBG_TAKEN_ID))
`DV_FCOV_SIGNAL(logic, pipe_flush, (ctrl_fsm_cs != FLUSH) & (ctrl_fsm_ns == FLUSH))
`DV_FCOV_SIGNAL(logic, debug_req, debug_req_i & ~debug_mode_q)
//`DV_FCOV_SIGNAL(logic, interrupt_taken, (ctrl_fsm_cs != IRQ_TAKEN) & (ctrl_fsm_ns == IRQ_TAKEN))
//`DV_FCOV_SIGNAL(logic, debug_entry_if,
// (ctrl_fsm_cs != DBG_TAKEN_IF) & (ctrl_fsm_ns == DBG_TAKEN_IF))
//`DV_FCOV_SIGNAL(logic, debug_entry_id,
// (ctrl_fsm_cs != DBG_TAKEN_ID) & (ctrl_fsm_ns == DBG_TAKEN_ID))
//`DV_FCOV_SIGNAL(logic, pipe_flush, (ctrl_fsm_cs != FLUSH) & (ctrl_fsm_ns == FLUSH))
//`DV_FCOV_SIGNAL(logic, debug_req, debug_req_i & ~debug_mode_q)
////////////////
// Assertions //

14
rtl/ibex_id_stage.sv
View file

@ -15,7 +15,7 @@
*/
`include "prim_assert.sv"
`include "dv_fcov_macros.svh"
//`include "dv_fcov_macros.svh"
module ibex_id_stage #(
parameter bit RV32E = 0,
@ -1068,12 +1068,12 @@ module ibex_id_stage #(
// FCOV //
//////////
`DV_FCOV_SIGNAL_GEN_IF(logic, rf_rd_wb_hz,
(gen_stall_mem.rf_rd_a_hz | gen_stall_mem.rf_rd_b_hz) & instr_valid_i, WritebackStage)
`DV_FCOV_SIGNAL(logic, branch_taken,
instr_executing & (id_fsm_q == FIRST_CYCLE) & branch_decision_i)
`DV_FCOV_SIGNAL(logic, branch_not_taken,
instr_executing & (id_fsm_q == FIRST_CYCLE) & ~branch_decision_i)
//`DV_FCOV_SIGNAL_GEN_IF(logic, rf_rd_wb_hz,
// (gen_stall_mem.rf_rd_a_hz | gen_stall_mem.rf_rd_b_hz) & instr_valid_i, WritebackStage)
//`DV_FCOV_SIGNAL(logic, branch_taken,
// instr_executing & (id_fsm_q == FIRST_CYCLE) & branch_decision_i)
//`DV_FCOV_SIGNAL(logic, branch_not_taken,
// instr_executing & (id_fsm_q == FIRST_CYCLE) & ~branch_decision_i)
////////////////
// Assertions //

6
rtl/ibex_load_store_unit.sv
View file

@ -12,7 +12,7 @@
*/
`include "prim_assert.sv"
`include "dv_fcov_macros.svh"
//`include "dv_fcov_macros.svh"
module ibex_load_store_unit
(
@ -503,8 +503,8 @@ module ibex_load_store_unit
// FCOV //
//////////
`DV_FCOV_SIGNAL(logic, ls_error_exception, (load_err_o | store_err_o) & ~pmp_err_q)
`DV_FCOV_SIGNAL(logic, ls_pmp_exception, (load_err_o | store_err_o) & pmp_err_q)
//`DV_FCOV_SIGNAL(logic, ls_error_exception, (load_err_o | store_err_o) & ~pmp_err_q)
//`DV_FCOV_SIGNAL(logic, ls_pmp_exception, (load_err_o | store_err_o) & pmp_err_q)
////////////////
// Assertions //

4
rtl/ibex_wb_stage.sv
View file

@ -12,7 +12,7 @@
*/
`include "prim_assert.sv"
`include "dv_fcov_macros.svh"
//`include "dv_fcov_macros.svh"
module ibex_wb_stage #(
parameter bit ResetAll = 1'b0,
@ -208,7 +208,7 @@ module ibex_wb_stage #(
({32{rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);
assign rf_we_wb_o = |rf_wdata_wb_mux_we;
`DV_FCOV_SIGNAL_GEN_IF(logic, wb_valid, g_writeback_stage.wb_valid_q, WritebackStage)
//`DV_FCOV_SIGNAL_GEN_IF(logic, wb_valid, g_writeback_stage.wb_valid_q, WritebackStage)
`ASSERT(RFWriteFromOneSourceOnly, $onehot0(rf_wdata_wb_mux_we))
endmodule