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Enable ECC in ICache tests
Eventually we probably want to make this configurable but, for now, enable it unconditionally.
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parent
2569a63eb7
commit
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4 changed files with 32 additions and 5 deletions
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@ -18,8 +18,17 @@ filesets:
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targets:
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sim:
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parameters:
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- ICacheECC
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filesets:
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- files_rtl
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- files_dv
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toplevel: tb
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default_tool: vcs
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parameters:
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ICacheECC:
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datatype: int
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default: 0
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paramtype: vlogparam
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description: "Enable ECC protection in instruction cache"
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@ -20,10 +20,15 @@
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// Testplan hjson file.
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testplan: "{proj_root}/dv/uvm/icache/data/ibex_icache_testplan.hjson"
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// Import additional common sim cfg files.
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import_cfgs: [// Project wide common sim cfg file
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"{proj_root}/dv/uvm/data/common_sim_cfg.hjson"]
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import_cfgs: [
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// Project wide common sim cfg file
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"{proj_root}/dv/uvm/data/common_sim_cfg.hjson",
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// Configuration options that should apply after the settings in
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// common_sim_cfg.
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"{proj_root}/dv/uvm/icache/dv/late_cfg.hjson"
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]
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// Default iterations for all tests - each test entry can override this.
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reseed: 50
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9
dv/uvm/icache/dv/late_cfg.hjson
Normal file
9
dv/uvm/icache/dv/late_cfg.hjson
Normal file
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@ -0,0 +1,9 @@
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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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{
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// Set any fusesoc parameters by appending to sv_flist_gen_opts
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//
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// We want to enable ICache ECC (needed for the ECC test below)
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sv_flist_gen_opts: ["--ICacheECC=1"]
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}
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@ -2,7 +2,9 @@
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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module tb;
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module tb #(
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parameter bit ICacheECC = 1'b0
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);
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// dep packages
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import uvm_pkg::*;
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import dv_utils_pkg::*;
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@ -22,7 +24,9 @@ module tb;
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ibex_icache_mem_if mem_if (.clk(clk), .rst_n(rst_n));
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// dut
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ibex_icache dut (
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ibex_icache #(
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.ICacheECC (ICacheECC)
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) dut (
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.clk_i (clk),
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.rst_ni (rst_n),
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