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Rename all modules to cve2 (#25)

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* rename files and modules to cve2

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* updated tb files

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remaining references to ibex: gitignore, examples, etc.

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
This commit is contained in:
christian-herber-nxp 2023-01-05 10:27:24 +01:00 • committed by GitHub
parent bbe47ea66b
commit 932db14619
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GPG key ID: 4AEE18F83AFDEB23
118 changed files with 722 additions and 722 deletions
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10
.gitignore vendored
View file

@ -19,18 +19,18 @@ ibex_simple_system_pcount.csv
__pycache__
# This is generated by VCS when running DV simulations with WAVE=1.
/dv/uvm/core_ibex/ucli.key
/dv/uvm/core_cve2/ucli.key
# This is generated by UVM when running simulations and doesn't seem
# to be something you can disable.
/dv/uvm/core_ibex/tr_db.log
/dv/uvm/core_cve2/tr_db.log
# This is the default output directory in dv/uvm/core_ibex and
# This is the default output directory in dv/uvm/core_cve2 and
# contains auto-generated files from building and running tests.
/dv/uvm/core_ibex/out
/dv/uvm/core_cve2/out
# This is generated by Questa tool when running DV simulations
modelsim.ini
# This is generated by Xcelium when running DV simulations, even with WAVE=0
/dv/uvm/core_ibex/waves.shm
/dv/uvm/core_cve2/waves.shm

34
Makefile
View file

@ -1,6 +1,6 @@
IBEX_CONFIG ?= small
CVE2_CONFIG ?= small
FUSESOC_CONFIG_OPTS = $(shell ./util/ibex_config.py $(IBEX_CONFIG) fusesoc_opts)
FUSESOC_CONFIG_OPTS = $(shell ./util/cve2_config.py $(CVE2_CONFIG) fusesoc_opts)
all: help
@ -19,7 +19,7 @@ build-all: build-riscv-compliance build-simple-system build-arty-100 \
.PHONY: build-riscv-compliance
build-riscv-compliance:
fusesoc --cores-root=. run --target=sim --setup --build \
lowrisc:ibex:ibex_riscv_compliance \
lowrisc:cve2:cve2_riscv_compliance \
$(FUSESOC_CONFIG_OPTS)
@ -30,7 +30,7 @@ build-riscv-compliance:
.PHONY: build-simple-system
build-simple-system:
fusesoc --cores-root=. run --target=sim --setup --build \
lowrisc:ibex:ibex_simple_system \
lowrisc:cve2:cve2_simple_system \
$(FUSESOC_CONFIG_OPTS)
simple-system-program = examples/sw/simple_system/hello_test/hello_test.vmem
@ -40,15 +40,15 @@ sw-simple-hello: $(simple-system-program)
$(simple-system-program):
cd examples/sw/simple_system/hello_test && $(MAKE)
Vibex_simple_system = \
build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system
$(Vibex_simple_system):
Vcve2_simple_system = \
build/lowrisc_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system
$(Vcve2_simple_system):
@echo "$@ not found"
@echo "Run \"make build-simple-system\" to create the dependency"
@false
run-simple-system: sw-simple-hello | $(Vibex_simple_system)
build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system \
run-simple-system: sw-simple-hello | $(Vcve2_simple_system)
build/lowrisc_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system \
--raminit=$(simple-system-program)
@ -67,23 +67,23 @@ $(arty-sw-program):
.PHONY: build-arty-35
build-arty-35: sw-led
fusesoc --cores-root=. run --target=synth --setup --build \
lowrisc:ibex:top_artya7 --part xc7a35ticsg324-1L
lowrisc:cve2:top_artya7 --part xc7a35ticsg324-1L
.PHONY: build-arty-100
build-arty-100: sw-led
fusesoc --cores-root=. run --target=synth --setup --build \
lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1
lowrisc:cve2:top_artya7 --part xc7a100tcsg324-1
.PHONY: program-arty
program-arty:
fusesoc --cores-root=. run --target=synth --run \
lowrisc:ibex:top_artya7
lowrisc:cve2:top_artya7
# Lint check
.PHONY: lint-core-tracing
lint-core-tracing:
fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core_tracing \
fusesoc --cores-root . run --target=lint lowrisc:cve2:cve2_core_tracing \
$(FUSESOC_CONFIG_OPTS)
@ -94,9 +94,9 @@ lint-core-tracing:
.PHONY: build-csr-test
build-csr-test:
fusesoc --cores-root=. run --target=sim --setup --build \
--tool=verilator lowrisc:ibex:tb_cs_registers
--tool=verilator lowrisc:cve2:tb_cs_registers
Vtb_cs_registers = \
build/lowrisc_ibex_tb_cs_registers_0/sim-verilator/Vtb_cs_registers
build/lowrisc_cve2_tb_cs_registers_0/sim-verilator/Vtb_cs_registers
$(Vtb_cs_registers):
@echo "$@ not found"
@echo "Run \"make build-csr-test\" to create the dependency"
@ -105,9 +105,9 @@ $(Vtb_cs_registers):
.PHONY: run-csr-test
run-csr-test: | $(Vtb_cs_registers)
fusesoc --cores-root=. run --target=sim --run \
--tool=verilator lowrisc:ibex:tb_cs_registers
--tool=verilator lowrisc:cve2:tb_cs_registers
# Echo the parameters passed to fusesoc for the chosen IBEX_CONFIG
# Echo the parameters passed to fusesoc for the chosen CVE2_CONFIG
.PHONY: test-cfg
test-cfg:
@echo $(FUSESOC_CONFIG_OPTS)

16
azure-pipelines.yml
View file

@ -49,10 +49,10 @@ jobs:
# Verible format is experimental so only run on default config for now,
# will eventually become part of the per-config CI
- bash: |
fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_top_tracing
fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:cve2:cve2_top_tracing
if [ $? != 0 ]; then
echo -n "##vso[task.logissue type=error]"
echo "Verilog format with Verible failed. Run 'fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_top_tracing' to check and fix all errors."
echo "Verilog format with Verible failed. Run 'fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:cve2:cve2_top_tracing' to check and fix all errors."
echo "This flow is currently experimental and failures can be ignored."
fi
# Show diff of what verilog_format would have changed, and then revert.
@ -78,7 +78,7 @@ jobs:
- bash: |
# Build and run CSR testbench, chosen Ibex configuration does not effect
# this so doesn't need to be part of per-config CI
fusesoc --cores-root=. run --target=sim --tool=verilator lowrisc:ibex:tb_cs_registers
fusesoc --cores-root=. run --target=sim --tool=verilator lowrisc:cve2:tb_cs_registers
displayName: Build and run CSR testbench with Verilator
- bash: |
@ -96,7 +96,7 @@ jobs:
# Run Ibex RTL CI per supported configuration
- template : ci/ibex-rtl-ci-steps.yml
parameters:
ibex_configs:
cve2_configs:
# Note: Try to keep the list of configurations in sync with the one used
# in Private CI.
- small
@ -107,19 +107,19 @@ jobs:
# Run lint on simple system
- bash: |
fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_simple_system
fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:cve2:cve2_simple_system
if [ $? != 0 ]; then
echo -n "##vso[task.logissue type=error]"
echo "Verilog lint with Verilator failed. Run 'fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_simple_system' to check and fix all errors."
echo "Verilog lint with Verilator failed. Run 'fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:cve2:cve2_simple_system' to check and fix all errors."
exit 1
fi
displayName: Run Verilator lint on simple system
- bash: |
fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_simple_system
fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:cve2:cve2_simple_system
if [ $? != 0 ]; then
echo -n "##vso[task.logissue type=error]"
echo "Verilog lint with Verible failed. Run 'fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_simple_system' to check and fix all errors."
echo "Verilog lint with Verible failed. Run 'fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:cve2:cve2_simple_system' to check and fix all errors."
exit 1
fi
displayName: Run Verible lint on simple system

32
ci/ibex-rtl-ci-steps.yml → ci/cve2-rtl-ci-steps.yml
View file

@ -1,39 +1,39 @@
parameters:
ibex_configs: []
cve2_configs: []
steps:
- ${{ each config in parameters.ibex_configs }}:
# ibex_config.py will exit with error code 1 on any error which will cause
- ${{ each config in parameters.cve2_configs }}:
# cve2_config.py will exit with error code 1 on any error which will cause
# the CI to fail if there's an issue with the configuration file or an
# incorrect configuration name being used
- bash: |
set -e
IBEX_CONFIG_OPTS=`./util/ibex_config.py ${{ config }} fusesoc_opts`
echo $IBEX_CONFIG_OPTS
echo "##vso[task.setvariable variable=ibex_config_opts]" $IBEX_CONFIG_OPTS
CVE2_CONFIG_OPTS=`./util/cve2_config.py ${{ config }} fusesoc_opts`
echo $CVE2_CONFIG_OPTS
echo "##vso[task.setvariable variable=cve2_config_opts]" $CVE2_CONFIG_OPTS
displayName: Test and display fusesoc config for ${{ config }}
- bash: |
fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_top_tracing $IBEX_CONFIG_OPTS
fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:cve2:cve2_top_tracing $CVE2_CONFIG_OPTS
if [ $? != 0 ]; then
echo -n "##vso[task.logissue type=error]"
echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_top_tracing $IBEX_CONFIG_OPTS' to check and fix all errors."
echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:cve2:cve2_top_tracing $CVE2_CONFIG_OPTS' to check and fix all errors."
exit 1
fi
displayName: Lint Verilog source files with Verilator for ${{ config }}
- bash: |
fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_top_tracing $IBEX_CONFIG_OPTS
fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:cve2:cve2_top_tracing $CVE2_CONFIG_OPTS
if [ $? != 0 ]; then
echo -n "##vso[task.logissue type=error]"
echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:ibex:ibex_top_tracing $IBEX_CONFIG_OPTS' to check and fix all errors."
echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint --tool=veriblelint lowrisc:cve2:cve2_top_tracing $CVE2_CONFIG_OPTS' to check and fix all errors."
exit 1
fi
displayName: Lint Verilog source files with Verible Verilog Lint for ${{ config }}
- bash: |
# Build simulation model of Ibex
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_riscv_compliance $IBEX_CONFIG_OPTS
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:cve2:cve2_riscv_compliance $CVE2_CONFIG_OPTS
if [ $? != 0 ]; then
echo -n "##vso[task.logissue type=error]"
echo "Unable to build Verilator model of Ibex for compliance testing."
@ -41,7 +41,7 @@ steps:
fi
# Run compliance test suite
export TARGET_SIM=$PWD/build/lowrisc_ibex_ibex_riscv_compliance_0.1/sim-verilator/Vibex_riscv_compliance
export TARGET_SIM=$PWD/build/lowrisc_cve2_cve2_riscv_compliance_0.1/sim-verilator/Vcve2_riscv_compliance
export RISCV_PREFIX=riscv32-unknown-elf-
export RISCV_TARGET=ibex
export RISCV_DEVICE=rv32imc
@ -68,18 +68,18 @@ steps:
- bash: |
# Setup environment to use cosim with Simple System
export IBEX_COSIM_ISS_ROOT=/opt/spike-cosim
export CVE2_COSIM_ISS_ROOT=/opt/spike-cosim
export LD_LIBRARY_PATH=/opt/spike-cosim/lib:$LD_LIBRARY_PATH
# Build simple system with co-simulation
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system_cosim $IBEX_CONFIG_OPTS
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:cve2:cve2_simple_system_cosim $CVE2_CONFIG_OPTS
if [ $? != 0 ]; then
echo -n "##vso[task.logissue type=error]"
echo "Build Simple System with co-simulation failed. Run fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system_cosim $IBEX_CONFIG_OPTS to check and fix all errors."
echo "Build Simple System with co-simulation failed. Run fusesoc --cores-root=. run --target=sim --setup --build lowrisc:cve2:cve2_simple_system_cosim $CVE2_CONFIG_OPTS to check and fix all errors."
fi
build/lowrisc_ibex_ibex_simple_system_cosim_0/sim-verilator/Vibex_simple_system --meminit=ram,examples/sw/benchmarks/coremark/coremark.elf
build/lowrisc_cve2_cve2_simple_system_cosim_0/sim-verilator/Vcve2_simple_system --meminit=ram,examples/sw/benchmarks/coremark/coremark.elf
if [ $? != 0 ]; then
echo -n "##vso[task.logissue type=error]"
echo "Running CoreMark failed co-simulation testing"

58
cv32e20_manifest.flist
View file

@ -33,37 +33,37 @@
+incdir+${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl
+incdir+${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/dv/sv/dv_utils
${DESIGN_RTL_DIR}/ibex_pkg.sv
${DESIGN_RTL_DIR}/ibex_tracer_pkg.sv
${DESIGN_RTL_DIR}/cve2_pkg.sv
${DESIGN_RTL_DIR}/cve2_tracer_pkg.sv
${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
${DESIGN_RTL_DIR}/ibex_alu.sv
${DESIGN_RTL_DIR}/ibex_branch_predict.sv
${DESIGN_RTL_DIR}/ibex_compressed_decoder.sv
${DESIGN_RTL_DIR}/ibex_controller.sv
${DESIGN_RTL_DIR}/ibex_cs_registers.sv
${DESIGN_RTL_DIR}/ibex_csr.sv
${DESIGN_RTL_DIR}/ibex_counter.sv
${DESIGN_RTL_DIR}/ibex_decoder.sv
${DESIGN_RTL_DIR}/ibex_ex_block.sv
${DESIGN_RTL_DIR}/ibex_fetch_fifo.sv
${DESIGN_RTL_DIR}/ibex_id_stage.sv
${DESIGN_RTL_DIR}/ibex_if_stage.sv
${DESIGN_RTL_DIR}/ibex_load_store_unit.sv
${DESIGN_RTL_DIR}/ibex_multdiv_fast.sv
${DESIGN_RTL_DIR}/ibex_multdiv_slow.sv
${DESIGN_RTL_DIR}/ibex_prefetch_buffer.sv
${DESIGN_RTL_DIR}/ibex_pmp.sv
${DESIGN_RTL_DIR}/ibex_register_file_ff.sv
${DESIGN_RTL_DIR}/ibex_wb_stage.sv
${DESIGN_RTL_DIR}/ibex_dummy_instr.sv
${DESIGN_RTL_DIR}/ibex_core.sv
${DESIGN_RTL_DIR}/ibex_top.sv
${DESIGN_RTL_DIR}/ibex_top_tracing.sv
${DESIGN_RTL_DIR}/ibex_tracer.sv
${DESIGN_RTL_DIR}/cve2_alu.sv
${DESIGN_RTL_DIR}/cve2_branch_predict.sv
${DESIGN_RTL_DIR}/cve2_compressed_decoder.sv
${DESIGN_RTL_DIR}/cve2_controller.sv
${DESIGN_RTL_DIR}/cve2_cs_registers.sv
${DESIGN_RTL_DIR}/cve2_csr.sv
${DESIGN_RTL_DIR}/cve2_counter.sv
${DESIGN_RTL_DIR}/cve2_decoder.sv
${DESIGN_RTL_DIR}/cve2_ex_block.sv
${DESIGN_RTL_DIR}/cve2_fetch_fifo.sv
${DESIGN_RTL_DIR}/cve2_id_stage.sv
${DESIGN_RTL_DIR}/cve2_if_stage.sv
${DESIGN_RTL_DIR}/cve2_load_store_unit.sv
${DESIGN_RTL_DIR}/cve2_multdiv_fast.sv
${DESIGN_RTL_DIR}/cve2_multdiv_slow.sv
${DESIGN_RTL_DIR}/cve2_prefetch_buffer.sv
${DESIGN_RTL_DIR}/cve2_pmp.sv
${DESIGN_RTL_DIR}/cve2_register_file_ff.sv
${DESIGN_RTL_DIR}/cve2_wb_stage.sv
${DESIGN_RTL_DIR}/cve2_dummy_instr.sv
${DESIGN_RTL_DIR}/cve2_core.sv
${DESIGN_RTL_DIR}/cve2_top.sv
${DESIGN_RTL_DIR}/cve2_top_tracing.sv
${DESIGN_RTL_DIR}/cve2_tracer.sv
${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv
${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv
${DESIGN_RTL_DIR}/../dv/uvm/core_ibex/common/prim/prim_pkg.sv
${DESIGN_RTL_DIR}/../dv/uvm/core_ibex/common/prim/prim_clock_gating.sv
${DESIGN_RTL_DIR}/../dv/uvm/core_ibex/common/prim/prim_buf.sv
${DESIGN_RTL_DIR}/../dv/uvm/core_cve2/common/prim/prim_pkg.sv
${DESIGN_RTL_DIR}/../dv/uvm/core_cve2/common/prim/prim_clock_gating.sv
${DESIGN_RTL_DIR}/../dv/uvm/core_cve2/common/prim/prim_buf.sv

64
ibex_configs.yaml → cve2_configs.yaml
View file

@ -9,9 +9,9 @@
# (4 cycles for mulh), resulting in 2 stall cycles for mul (3 for mulh)
small:
RV32E : 0
RV32M : "ibex_pkg::RV32MFast"
RV32B : "ibex_pkg::RV32BNone"
RegFile : "ibex_pkg::RegFileFF"
RV32M : "cve2_pkg::RV32MFast"
RV32B : "cve2_pkg::RV32BNone"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 0
WritebackStage : 0
ICache : 0
@ -20,15 +20,15 @@ small:
PMPEnable : 0
PMPGranularity : 0
PMPNumRegions : 4
SecureIbex : 0
SecureCVE2 : 0
ICacheScramble : 0
# Configuration to match that used in the OpenTitan project
opentitan:
RV32E : 0
RV32M : "ibex_pkg::RV32MSingleCycle"
RV32B : "ibex_pkg::RV32BOTEarlGrey"
RegFile : "ibex_pkg::RegFileFF"
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BOTEarlGrey"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 1
@ -37,7 +37,7 @@ opentitan:
PMPEnable : 1
PMPGranularity : 0
PMPNumRegions : 16
SecureIbex : 1
SecureCVE2 : 1
ICacheScramble : 0
# ===============================
@ -49,9 +49,9 @@ opentitan:
# maximum performance configuration.
experimental-maxperf:
RV32E : 0
RV32M : "ibex_pkg::RV32MSingleCycle"
RV32B : "ibex_pkg::RV32BNone"
RegFile : "ibex_pkg::RegFileFF"
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BNone"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
@ -60,15 +60,15 @@ experimental-maxperf:
PMPEnable : 0
PMPGranularity : 0
PMPNumRegions : 4
SecureIbex : 0
SecureCVE2 : 0
ICacheScramble : 0
# experimental-maxperf config above plus PMP enabled with 16 regions.
experimental-maxperf-pmp:
RV32E : 0
RV32M : "ibex_pkg::RV32MSingleCycle"
RV32B : "ibex_pkg::RV32BNone"
RegFile : "ibex_pkg::RegFileFF"
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BNone"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
@ -77,15 +77,15 @@ experimental-maxperf-pmp:
PMPEnable : 1
PMPGranularity : 0
PMPNumRegions : 16
SecureIbex : 0
SecureCVE2 : 0
ICacheScramble : 0
# experimental-maxperf-pmp config above with balanced bitmanip extension
experimental-maxperf-pmp-bmbalanced:
RV32E : 0
RV32M : "ibex_pkg::RV32MSingleCycle"
RV32B : "ibex_pkg::RV32BBalanced"
RegFile : "ibex_pkg::RegFileFF"
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BBalanced"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
@ -94,15 +94,15 @@ experimental-maxperf-pmp-bmbalanced:
PMPEnable : 1
PMPGranularity : 0
PMPNumRegions : 16
SecureIbex : 0
SecureCVE2 : 0
ICacheScramble : 0
# experimental-maxperf-pmp config above with full bitmanip extension
experimental-maxperf-pmp-bmfull:
RV32E : 0
RV32M : "ibex_pkg::RV32MSingleCycle"
RV32B : "ibex_pkg::RV32BFull"
RegFile : "ibex_pkg::RegFileFF"
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BFull"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
@ -111,15 +111,15 @@ experimental-maxperf-pmp-bmfull:
PMPEnable : 1
PMPGranularity : 0
PMPNumRegions : 16
SecureIbex : 0
SecureCVE2 : 0
ICacheScramble : 0
# experimental-maxperf-pmp-bmfull config above with icache enabled
experimental-maxperf-pmp-bmfull-icache:
RV32E : 0
RV32M : "ibex_pkg::RV32MSingleCycle"
RV32B : "ibex_pkg::RV32BFull"
RegFile : "ibex_pkg::RegFileFF"
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BFull"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 1
@ -128,7 +128,7 @@ experimental-maxperf-pmp-bmfull-icache:
PMPEnable : 1
PMPGranularity : 0
PMPNumRegions : 16
SecureIbex : 0
SecureCVE2 : 0
ICacheScramble : 0
# experimental-maxperf with branch predictor switched on. This exists to allow
@ -137,9 +137,9 @@ experimental-maxperf-pmp-bmfull-icache:
# development.
experimental-branch-predictor:
RV32E : 0
RV32M : "ibex_pkg::RV32MSingleCycle"
RV32B : "ibex_pkg::RV32BNone"
RegFile : "ibex_pkg::RegFileFF"
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BNone"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
@ -148,6 +148,6 @@ experimental-branch-predictor:
PMPEnable : 0
PMPGranularity : 0
PMPNumRegions : 4
SecureIbex : 0
SecureCVE2 : 0
ICacheScramble : 0

66
ibex_core.core → cve2_core.core
View file

@ -2,7 +2,7 @@ CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_core:0.1"
name: "lowrisc:cve2:cve2_core:0.1"
description: "Ibex CPU Core Components"
filesets:
@ -11,31 +11,31 @@ filesets:
- lowrisc:prim:assert
- lowrisc:prim:clock_gating
- lowrisc:prim:lfsr
- lowrisc:ibex:ibex_pkg
- lowrisc:ibex:ibex_icache
- lowrisc:cve2:cve2_pkg
- lowrisc:cve2:cve2_icache
- lowrisc:dv:dv_fcov_macros
files:
- rtl/ibex_alu.sv
- rtl/ibex_branch_predict.sv
- rtl/ibex_compressed_decoder.sv
- rtl/ibex_controller.sv
- rtl/ibex_cs_registers.sv
- rtl/ibex_csr.sv
- rtl/ibex_counter.sv
- rtl/ibex_decoder.sv
- rtl/ibex_ex_block.sv
- rtl/ibex_fetch_fifo.sv
- rtl/ibex_id_stage.sv
- rtl/ibex_if_stage.sv
- rtl/ibex_load_store_unit.sv
- rtl/ibex_multdiv_fast.sv
- rtl/ibex_multdiv_slow.sv
- rtl/ibex_prefetch_buffer.sv
- rtl/ibex_pmp.sv
- rtl/ibex_wb_stage.sv
- rtl/ibex_dummy_instr.sv
- rtl/ibex_core.sv
- rtl/ibex_pmp_reset_default.svh: {is_include_file: true}
- rtl/cve2_alu.sv
- rtl/cve2_branch_predict.sv
- rtl/cve2_compressed_decoder.sv
- rtl/cve2_controller.sv
- rtl/cve2_cs_registers.sv
- rtl/cve2_csr.sv
- rtl/cve2_counter.sv
- rtl/cve2_decoder.sv
- rtl/cve2_ex_block.sv
- rtl/cve2_fetch_fifo.sv
- rtl/cve2_id_stage.sv
- rtl/cve2_if_stage.sv
- rtl/cve2_load_store_unit.sv
- rtl/cve2_multdiv_fast.sv
- rtl/cve2_multdiv_slow.sv
- rtl/cve2_prefetch_buffer.sv
- rtl/cve2_pmp.sv
- rtl/cve2_wb_stage.sv
- rtl/cve2_dummy_instr.sv
- rtl/cve2_core.sv
- rtl/cve2_pmp_reset_default.svh: {is_include_file: true}
file_type: systemVerilogSource
files_lint_verilator:
@ -72,21 +72,21 @@ parameters:
RV32M:
datatype: str
default: ibex_pkg::RV32MFast
default: cve2_pkg::RV32MFast
paramtype: vlogdefine
description: "RV32M implementation parameter enum. See the ibex_pkg::rv32m_e enum in ibex_pkg.sv for permitted values."
description: "RV32M implementation parameter enum. See the cve2_pkg::rv32m_e enum in cve2_pkg.sv for permitted values."
RV32B:
datatype: str
default: ibex_pkg::RV32BNone
default: cve2_pkg::RV32BNone
paramtype: vlogdefine
description: "Bitmanip implementation parameter enum. See the ibex_pkg::rv32b_e enum in ibex_pkg.sv for permitted values."
description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values."
RegFile:
datatype: str
default: ibex_pkg::RegFileFF
default: cve2_pkg::RegFileFF
paramtype: vlogdefine
description: "Register file implementation parameter enum. See the ibex_pkg::regfile_e enum in ibex_pkg.sv for permitted values."
description: "Register file implementation parameter enum. See the cve2_pkg::regfile_e enum in cve2_pkg.sv for permitted values."
ICache:
datatype: int
@ -118,7 +118,7 @@ parameters:
default: 0
description: "Enables static branch prediction (EXPERIMENTAL)"
SecureIbex:
SecureCVE2:
datatype: int
default: 0
paramtype: vlogparam
@ -149,7 +149,7 @@ targets:
- tool_veriblelint ? (files_lint_verible)
- files_rtl
- files_check_tool_requirements
toplevel: ibex_core
toplevel: cve2_core
parameters:
- tool_vivado ? (FPGA_XILINX=true)
lint:
@ -173,7 +173,7 @@ targets:
- SYNTHESIS=true
- RVFI=true
default_tool: veribleformat
toplevel: ibex_core
toplevel: cve2_core
tools:
veribleformat:
verible_format_args:

8
ibex_icache.core → cve2_icache.core
View file

@ -2,21 +2,21 @@ CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_icache:0.1"
name: "lowrisc:cve2:cve2_icache:0.1"
description: "Ibex instruction cache"
filesets:
files_rtl:
depend:
- lowrisc:prim:secded
- lowrisc:prim:assert
- lowrisc:ibex:ibex_pkg
- lowrisc:cve2:cve2_pkg
files:
- rtl/ibex_icache.sv
- rtl/cve2_icache.sv
file_type: systemVerilogSource
targets:
default: &default_target
filesets:
- files_rtl
toplevel: ibex_icache
toplevel: cve2_icache
default_tool: vcs

8
ibex_multdiv.core → cve2_multdiv.core
View file

@ -2,17 +2,17 @@ CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_multdiv:0.1"
name: "lowrisc:cve2:cve2_multdiv:0.1"
description: "Multiplier and divider"
filesets:
files_rtl:
depend:
- lowrisc:prim:assert
- lowrisc:ibex:ibex_pkg
- lowrisc:cve2:cve2_pkg
files:
- rtl/ibex_multdiv_fast.sv
- rtl/ibex_multdiv_slow.sv
- rtl/cve2_multdiv_fast.sv
- rtl/cve2_multdiv_slow.sv
file_type: systemVerilogSource
parameters:

6
ibex_pkg.core → cve2_pkg.core
View file

@ -2,13 +2,13 @@ CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_pkg:0.1"
description: "Header package for Ibex"
name: "lowrisc:cve2:cve2_pkg:0.1"
description: "Header package for CVE2"
filesets:
files_rtl:
files:
- rtl/ibex_pkg.sv
- rtl/cve2_pkg.sv
file_type: systemVerilogSource
targets:

34
ibex_top.core → cve2_top.core
View file

@ -2,24 +2,24 @@ CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_top:0.1"
name: "lowrisc:cve2:cve2_top:0.1"
description: "Ibex, a small RV32 CPU core"
filesets:
files_rtl:
depend:
- lowrisc:ibex:ibex_pkg
- lowrisc:ibex:ibex_core
- lowrisc:cve2:cve2_pkg
- lowrisc:cve2:cve2_core
- lowrisc:prim:buf
- lowrisc:prim:clock_mux2
- lowrisc:prim:flop
- lowrisc:prim:ram_1p_scr
files:
- rtl/ibex_register_file_ff.sv # generic FF-based
- rtl/ibex_register_file_fpga.sv # FPGA
- rtl/ibex_register_file_latch.sv # ASIC
- rtl/ibex_lockstep.sv
- rtl/ibex_top.sv
- rtl/cve2_register_file_ff.sv # generic FF-based
- rtl/cve2_register_file_fpga.sv # FPGA
- rtl/cve2_register_file_latch.sv # ASIC
- rtl/cve2_lockstep.sv
- rtl/cve2_top.sv
file_type: systemVerilogSource
files_lint_verilator:
@ -56,21 +56,21 @@ parameters:
RV32M:
datatype: str
default: ibex_pkg::RV32MFast
default: cve2_pkg::RV32MFast
paramtype: vlogdefine
description: "RV32M implementation parameter enum. See the ibex_pkg::rv32m_e enum in ibex_pkg.sv for permitted values."
description: "RV32M implementation parameter enum. See the cve2_pkg::rv32m_e enum in cve2_pkg.sv for permitted values."
RV32B:
datatype: str
default: ibex_pkg::RV32BNone
default: cve2_pkg::RV32BNone
paramtype: vlogdefine
description: "Bitmanip implementation parameter enum. See the ibex_pkg::rv32b_e enum in ibex_pkg.sv for permitted values."
description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values."
RegFile:
datatype: str
default: ibex_pkg::RegFileFF
default: cve2_pkg::RegFileFF
paramtype: vlogdefine
description: "Register file implementation parameter enum. See the ibex_pkg::regfile_e enum in ibex_pkg.sv for permitted values."
description: "Register file implementation parameter enum. See the cve2_pkg::regfile_e enum in cve2_pkg.sv for permitted values."
ICache:
datatype: int
@ -102,7 +102,7 @@ parameters:
default: 0
description: "Enables static branch prediction (EXPERIMENTAL)"
SecureIbex:
SecureCVE2:
datatype: int
default: 0
paramtype: vlogparam
@ -139,7 +139,7 @@ targets:
- tool_veriblelint ? (files_lint_verible)
- files_rtl
- files_check_tool_requirements
toplevel: ibex_top
toplevel: cve2_top
parameters:
- tool_vivado ? (FPGA_XILINX=true)
lint:
@ -163,7 +163,7 @@ targets:
- SYNTHESIS=true
- RVFI=true
default_tool: veribleformat
toplevel: ibex_top
toplevel: cve2_top
tools:
veribleformat:
verible_format_args:

28
ibex_top_tracing.core → cve2_top_tracing.core
View file

@ -2,15 +2,15 @@ CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_top_tracing:0.1"
name: "lowrisc:cve2:cve2_top_tracing:0.1"
description: "Ibex, a small RV32 CPU core with tracing enabled"
filesets:
files_rtl:
depend:
- lowrisc:ibex:ibex_top
- lowrisc:ibex:ibex_tracer
- lowrisc:cve2:cve2_top
- lowrisc:cve2:cve2_tracer
files:
- rtl/ibex_top_tracing.sv
- rtl/cve2_top_tracing.sv
file_type: systemVerilogSource
parameters:
@ -31,21 +31,21 @@ parameters:
RV32M:
datatype: str
default: ibex_pkg::RV32MFast
default: cve2_pkg::RV32MFast
paramtype: vlogdefine
description: "RV32M implementation parameter enum. See the ibex_pkg::rv32m_e enum in ibex_pkg.sv for permitted values."
description: "RV32M implementation parameter enum. See the cve2_pkg::rv32m_e enum in cve2_pkg.sv for permitted values."
RV32B:
datatype: str
default: ibex_pkg::RV32BNone
default: cve2_pkg::RV32BNone
paramtype: vlogdefine
description: "Bitmanip implementation parameter enum. See the ibex_pkg::rv32b_e enum in ibex_pkg.sv for permitted values."
description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values."
RegFile:
datatype: str
default: ibex_pkg::RegFileFF
default: cve2_pkg::RegFileFF
paramtype: vlogdefine
description: "Register file implementation parameter enum. See the ibex_pkg::regfile_e enum in ibex_pkg.sv for permitted values."
description: "Register file implementation parameter enum. See the cve2_pkg::regfile_e enum in cve2_pkg.sv for permitted values."
ICache:
datatype: int
@ -77,7 +77,7 @@ parameters:
default: 0
description: "Enables static branch prediction (EXPERIMENTAL)"
SecureIbex:
SecureCVE2:
datatype: int
default: 0
paramtype: vlogparam
@ -113,7 +113,7 @@ targets:
- files_rtl
parameters:
- RVFI=true
toplevel: ibex_top_tracing
toplevel: cve2_top_tracing
lint:
<<: *default_target
@ -129,7 +129,7 @@ targets:
- BranchTargetALU
- WritebackStage
- BranchPredictor
- SecureIbex
- SecureCVE2
- ICacheScramble
- PMPEnable
- PMPGranularity
@ -150,7 +150,7 @@ targets:
- SYNTHESIS=true
- RVFI=true
default_tool: veribleformat
toplevel: ibex_top_tracing
toplevel: cve2_top_tracing
tools:
veribleformat:
verible_format_args:

8
ibex_tracer.core → cve2_tracer.core
View file

@ -2,16 +2,16 @@ CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_tracer:0.1"
name: "lowrisc:cve2:cve2_tracer:0.1"
description: "Tracer for use with Ibex using the RVFI interface"
filesets:
files_rtl:
depend:
- lowrisc:prim:assert
- lowrisc:ibex:ibex_pkg
- lowrisc:cve2:cve2_pkg
files:
- rtl/ibex_tracer_pkg.sv
- rtl/ibex_tracer.sv
- rtl/cve2_tracer_pkg.sv
- rtl/cve2_tracer.sv
file_type: systemVerilogSource
targets:

2
doc/01_overview/index.rst
View file

@ -1,4 +1,4 @@
Introduction to Ibex
Introduction to CVE2
====================
Ibex is a production-quality open source 32-bit RISC-V CPU core written in SystemVerilog.

6
doc/02_user/getting_started.rst
View file

@ -8,8 +8,8 @@ This page discusses initial steps and requirements to start using Ibex in your d
Register File
-------------
Ibex comes with three different register file implementations that can be selected using the enumerated parameter ``RegFile`` defined in :file:`rtl/ibex_pkg.sv`.
Depending on the target technology, either the flip-flop-based ("ibex_pkg::RegFileFF", default), the latch-based ("ibex_pkg::RegFileLatch") or an FPGA-targeted ("ibex_pkg::RegFileFPGA") implementation should be selected.
Ibex comes with three different register file implementations that can be selected using the enumerated parameter ``RegFile`` defined in :file:`rtl/cve2_pkg.sv`.
Depending on the target technology, either the flip-flop-based ("cve2_pkg::RegFileFF", default), the latch-based ("cve2_pkg::RegFileLatch") or an FPGA-targeted ("cve2_pkg::RegFileFPGA") implementation should be selected.
For more information about the three register file implementations and their trade-offs, check out :ref:`register-file`.
Identification CSRs
@ -17,7 +17,7 @@ Identification CSRs
The RISC-V Privileged Architecture specifies several read-only CSRs that identify the vendor and micro-architecture of a CPU.
These are ``mvendorid``, ``marchid`` and ``mimpid``.
The fixed, read-only values for these CSRs are defined in :file:`rtl/ibex_pkg.sv`.
The fixed, read-only values for these CSRs are defined in :file:`rtl/cve2_pkg.sv`.
Implementers should carefully consider appropriate values for these registers.
Ibex, as an open source implementation, has an assigned architecture ID (``marchid``) of 22.
(Allocations are specified in `marchid.md of the riscv-isa-manual repository <https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md>`_.)

48
doc/02_user/integration.rst
View file

@ -3,8 +3,8 @@
Core Integration
================
The main module is named ``ibex_top`` and can be found in ``ibex_top.sv``.
Note that the core logic is split-out from the register file and RAMs under ``ibex_top``.
The main module is named ``cve2_top`` and can be found in ``cve2_top.sv``.
Note that the core logic is split-out from the register file and RAMs under ``cve2_top``.
This is to facilitate a dual-core lockstep implementation (see :ref:`security`).
Below, the instantiation template is given and the parameters and interfaces are described.
@ -14,23 +14,23 @@ Instantiation Template
.. code-block:: verilog
ibex_top #(
cve2_top #(
.PMPEnable ( 0 ),
.PMPGranularity ( 0 ),
.PMPNumRegions ( 4 ),
.MHPMCounterNum ( 0 ),
.MHPMCounterWidth ( 40 ),
.RV32E ( 0 ),
.RV32M ( ibex_pkg::RV32MFast ),
.RV32B ( ibex_pkg::RV32BNone ),
.RegFile ( ibex_pkg::RegFileFF ),
.RV32M ( cve2_pkg::RV32MFast ),
.RV32B ( cve2_pkg::RV32BNone ),
.RegFile ( cve2_pkg::RegFileFF ),
.ICache ( 0 ),
.ICacheECC ( 0 ),
.ICacheScramble ( 0 ),
.BranchPrediction ( 0 ),
.SecureIbex ( 0 ),
.RndCnstLfsrSeed ( ibex_pkg::RndCnstLfsrSeedDefault ),
.RndCnstLfsrPerm ( ibex_pkg::RndCnstLfsrPermDefault ),
.RndCnstLfsrSeed ( cve2_pkg::RndCnstLfsrSeedDefault ),
.RndCnstLfsrPerm ( cve2_pkg::RndCnstLfsrPermDefault ),
.DbgTriggerEn ( 0 ),
.DmHaltAddr ( 32'h1A110800 ),
.DmExceptionAddr ( 32'h1A110808 )
@ -105,22 +105,22 @@ Parameters
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``RV32E`` | bit | 0 | RV32E mode enable (16 integer registers only) |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``RV32M`` | ibex_pkg::rv32m_e | RV32MFast | M(ultiply) extension select: |
| | | | "ibex_pkg::RV32MNone": No M-extension |
| | | | "ibex_pkg::RV32MSlow": Slow multi-cycle multiplier, iterative divider |
| | | | "ibex_pkg::RV32MFast": 3-4 cycle multiplier, iterative divider |
| | | | "ibex_pkg::RV32MSingleCycle": 1-2 cycle multiplier, iterative divider |
| ``RV32M`` | cve2_pkg::rv32m_e | RV32MFast | M(ultiply) extension select: |
| | | | "cve2_pkg::RV32MNone": No M-extension |
| | | | "cve2_pkg::RV32MSlow": Slow multi-cycle multiplier, iterative divider |
| | | | "cve2_pkg::RV32MFast": 3-4 cycle multiplier, iterative divider |
| | | | "cve2_pkg::RV32MSingleCycle": 1-2 cycle multiplier, iterative divider |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``RV32B`` | ibex_pkg::rv32b_e | RV32BNone | B(itmanipulation) extension select: |
| | | | "ibex_pkg::RV32BNone": No B-extension |
| | | | "ibex_pkg::RV32BBalanced": Sub-extensions Zba, Zbb, Zbs, Zbf and Zbt |
| | | | "ibex_pkg::RV32BOTEarlGrey": All sub-extensions except Zbe |
| | | | "ibex_pkg::RV32BFull": All sub-extensions |
| ``RV32B`` | cve2_pkg::rv32b_e | RV32BNone | B(itmanipulation) extension select: |
| | | | "cve2_pkg::RV32BNone": No B-extension |
| | | | "cve2_pkg::RV32BBalanced": Sub-extensions Zba, Zbb, Zbs, Zbf and Zbt |
| | | | "cve2_pkg::RV32BOTEarlGrey": All sub-extensions except Zbe |
| | | | "cve2_pkg::RV32BFull": All sub-extensions |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``RegFile`` | ibex_pkg::regfile_e | RegFileFF | Register file implementation select: |
| | | | "ibex_pkg::RegFileFF": Generic flip-flop-based register file |
| | | | "ibex_pkg::RegFileFPGA": Register file for FPGA targets |
| | | | "ibex_pkg::RegFileLatch": Latch-based register file for ASIC targets |
| ``RegFile`` | cve2_pkg::regfile_e | RegFileFF | Register file implementation select: |
| | | | "cve2_pkg::RegFileFF": Generic flip-flop-based register file |
| | | | "cve2_pkg::RegFileFPGA": Register file for FPGA targets |
| | | | "cve2_pkg::RegFileLatch": Latch-based register file for ASIC targets |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``BranchTargetALU`` | bit | 0 | *EXPERIMENTAL* - Enables branch target ALU removing a stall |
| | | | cycle from taken branches |
@ -141,7 +141,7 @@ Parameters
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``SecureIbex`` | bit | 0 | *EXPERIMENTAL* Enable various additional features targeting |
| | | | secure code execution. Note: SecureIbex == 1'b1 and |
| | | | RV32M == ibex_pkg::RV32MNone is an illegal combination. |
| | | | RV32M == cve2_pkg::RV32MNone is an illegal combination. |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``RndCnstLfsrSeed`` | lfsr_seed_t | see above | Set the starting seed of the LFSR used to generate dummy instructions |
| | | | (only relevant when SecureIbex == 1'b1) |
@ -213,7 +213,7 @@ Interfaces
| | | | pause fetching new instructions. A |
| | | | multi-bit encoding scheme is used. See |
| | | | `FetchEnableOn` / `FetchEnableOff` in |
| | | | :file:`rtl/ibex_pkg.sv` |
| | | | :file:`rtl/cve2_pkg.sv` |
+----------------------------+-------------------------+-----+----------------------------------------+
| ``core_sleep_o`` | 1 | out | Core in WFI with no outstanding data |
| | | | or instruction accesses. Deasserts |

20
doc/03_reference/cosim.rst
View file

@ -31,10 +31,10 @@ Follow the Spike build instructions to build and install Spike.
The build will install multiple header files and libraries, it is recommended a custom install location (using ``--prefix=<path>`` with ``configure``) is used to avoid cluttering system directories.
The ``--enable-commitlog`` and ``--enable-misaligned`` options must be passed to ``configure``.
Once built, the ``IBEX_COSIM_ISS_ROOT`` environment variable must be set to the Spike root install directory (as given by ``--prefix=<path>`` to ``configure``) in order to build either the UVM DV environment or Simple System with co-simulation support.
Once built, the ``CVE2_COSIM_ISS_ROOT`` environment variable must be set to the Spike root install directory (as given by ``--prefix=<path>`` to ``configure``) in order to build either the UVM DV environment or Simple System with co-simulation support.
To build/run the UVM DV environment with the co-simulator add the ``COSIM=1`` argument to the make command.
To build Simple System with the co-simulator build the ``lowrisc:ibex:ibex_simple_system_cosim`` core.
To build Simple System with the co-simulator build the ``lowrisc:cve2:cve2_simple_system_cosim`` core.
Quick Build and Run Instructions
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@ -44,7 +44,7 @@ Build and install the co-simulator
.. code-block:: bash
# Get the Ibex co-simulation spike branch
git clone -b ibex_cosim https://github.com/lowRISC/riscv-isa-sim.git riscv-isa-sim-cosim
git clone -b cve2_cosim https://github.com/lowRISC/riscv-isa-sim.git riscv-isa-sim-cosim
# Setup build directory
cd riscv-isa-sim-cosim
@ -55,15 +55,15 @@ Build and install the co-simulator
../configure --enable-commitlog --enable-misaligned --prefix=/opt/spike-cosim
sudo make -j8 install
# Setup IBEX_COSIM_ISS_ROOT so build flow can find the co-simulator
export IBEX_COSIM_ISS_ROOT=/opt/spike-cosim
# Setup CVE2_COSIM_ISS_ROOT so build flow can find the co-simulator
export CVE2_COSIM_ISS_ROOT=/opt/spike-cosim
Run the UVM DV regression with co-simulation enabled
.. code-block:: bash
# Run regression with co-simulation enabled
cd <ibex_area>/dv/uvm/core_ibex
cd <cve2_area>/dv/uvm/core_cve2
make COSIM=1
Build and run Simple System with the co-simulation enabled
@ -71,7 +71,7 @@ Build and run Simple System with the co-simulation enabled
.. code-block:: bash
# Build simulator
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system_cosim --RV32E=0 --RV32M=ibex_pkg::RV32MFast
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:cve2:cve2_simple_system_cosim --RV32E=0 --RV32M=cve2_pkg::RV32MFast
# Build coremark test binary, with performance counter dump disabled. The
# co-simulator system doesn't produce matching performance counters in spike so
@ -82,7 +82,7 @@ Build and run Simple System with the co-simulation enabled
export LD_LIBRARY_PATH=/opt/spike-cosim/lib:$LD_LIBRARY_PATH
# Run coremark binary with co-simulation checking
build/lowrisc_ibex_ibex_simple_system_cosim_0/sim-verilator/Vibex_simple_system --meminit=ram,examples/sw/benchmarks/coremark/coremark.elf
build/lowrisc_cve2_cve2_simple_system_cosim_0/sim-verilator/Vcve2_simple_system --meminit=ram,examples/sw/benchmarks/coremark/coremark.elf
Co-simulation details
----------------------
@ -143,7 +143,7 @@ The DV environment is responsible for determining when to call ``set_mip``, ``se
The state of the incoming interrupts and debug request is sampled when an instruction moves from IF to ID/EX.
The sampled state is tracked with the rest of the RVFI pipeline and used to call ``set_mip``, ``set_debug_req`` and ``set_nmi`` when the instruction is output by the RVFI.
See the comments in :file:`rtl/ibex_core.sv`, around the ``new_debug_req``, ``new_nmi`` and ``new_irq`` signals for further details.
See the comments in :file:`rtl/cve2_core.sv`, around the ``new_debug_req``, ``new_nmi`` and ``new_irq`` signals for further details.
Memory Access Checking and Bus Errors
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@ -163,7 +163,7 @@ The co-simulation system will produce an instruction fault trap if it attempts t
Two methods are available for dealing with bus errors on the Iside, they differ in where they probe.
One probes on the external instr_X memory interface, the other probes internally within the IF stage.
The probe used is selected by the ``probe_imem_for_err`` field of the ``core_ibex_cosim_cfg`` structure.
The probe used is selected by the ``probe_imem_for_err`` field of the ``core_cve2_cosim_cfg`` structure.
When set external probing is used, otherwise internal probing is used.
Both probe points look for addresses that have seen bus errors.

6
doc/03_reference/coverage_plan.rst
View file

@ -47,7 +47,7 @@ Some categories are just a single instruction, which is named without further de
* **ALU** - All of the reg/reg reg/imm instructions that use the ALU.
This is any RISC-V instruction with an opcode of ``7'b0010011`` or ``7'b0110011`` (``ibex_pkg::OPCODE_OP`` and ``ibex_pkg::OPCODE_OP_IMM``) other than the ``MUL*`` and ``DIV*`` family of instructions (from RV32M).
This is any RISC-V instruction with an opcode of ``7'b0010011`` or ``7'b0110011`` (``cve2_pkg::OPCODE_OP`` and ``cve2_pkg::OPCODE_OP_IMM``) other than the ``MUL*`` and ``DIV*`` family of instructions (from RV32M).
* **Mul** - Any ``MUL*`` instruction (from RV32M).
* **Div** - Any ``DIV*`` instruction (from RV32M).
* **Branch** - Any ``B*`` family branch instruction.
@ -262,8 +262,8 @@ Basic read/write functionality must be tested on all implemented CSRs.
* Access to CSR disallowed due to privilege level/debug mode.
* Read and write from/to an unimplemented CSR
CSRs addresses do not need to be crossed with the variety of CSR instructions as these all use the same basic read & write interface into ``ibex_cs_registers``.
Coverage of the above points will be sampled at the ``ibex_cs_registers`` interface (as opposed to sampling CSR instructions).
CSRs addresses do not need to be crossed with the variety of CSR instructions as these all use the same basic read & write interface into ``cve2_cs_registers``.
Coverage of the above points will be sampled at the ``cve2_cs_registers`` interface (as opposed to sampling CSR instructions).
Miscellaneous
^^^^^^^^^^^^^

6
doc/03_reference/cs_registers.rst
View file

@ -597,7 +597,7 @@ CSR Address: ``0xF11``
Reset Value: ``0x0000_0000``
Use the ``CSR_MVENDORID_VALUE`` parameter in :file:`rtl/ibex_pkg.sv` to change the fixed value.
Use the ``CSR_MVENDORID_VALUE`` parameter in :file:`rtl/cve2_pkg.sv` to change the fixed value.
Details of what the ID represents can be found in the RISC-V Privileged Specification.
Machine Architecture ID (marchid)
@ -607,7 +607,7 @@ CSR Address: ``0xF12``
Reset Value: ``0x0000_0016``
Use the ``CSR_MARCHID_VALUE`` parameter in :file:`rtl/ibex_pkg.sv` to change the fixed value.
Use the ``CSR_MARCHID_VALUE`` parameter in :file:`rtl/cve2_pkg.sv` to change the fixed value.
The value used is allocated specifically to Ibex.
If significant changes are made a different ID should be used.
Details of what the ID represents can be found in the RISC-V Privileged Specification.
@ -619,7 +619,7 @@ CSR Address: ``0xF13``
Reset Value: ``0x0000_0000``
Use the ``CSR_MIMPID_VALUE`` parameter in :file:`rtl/ibex_pkg.sv` to change the fixed value.
Use the ``CSR_MIMPID_VALUE`` parameter in :file:`rtl/cve2_pkg.sv` to change the fixed value.
Details of what the ID represents can be found in the RISC-V Privileged Specification.
.. _csr-mhartid:

4
doc/03_reference/icache.rst
View file

@ -2,7 +2,7 @@
Instruction Cache
=================
:file:`rtl/ibex_icache.sv.`
:file:`rtl/cve2_icache.sv.`
NOTE - This module is currently DRAFT
@ -213,7 +213,7 @@ This isn't an attempt to describe the cache's performance characteristics.
The I$ has a single clock (``clk_i``) and asynchronous reset (``rst_ni``).
Data is requested from the instruction memory with the ports prefixed by ``instr_``. These work as described in :ref:`instruction-fetch`.
Note that there's one extra port on the I$, which doesn't appear at the ``ibex_top`` top-level.
Note that there's one extra port on the I$, which doesn't appear at the ``cve2_top`` top-level.
This is ``instr_pmp_err_i``.
If the PMP block disallows a fetch for a certain address, it will squash the outgoing memory request entirely and set ``instr_pmp_err_i``.
If that happens, the cache drops ``instr_req_o`` and stops making any further requests for that cache line.

24
doc/03_reference/images/tb2.svg
View file

@ -315,7 +315,7 @@
style="fill:#000000;stroke-width:0.26458332px"
x="50.900173"
y="70.702904"
id="tspan861">core_ibex_base_test</tspan></text>
id="tspan861">core_cve2_base_test</tspan></text>
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id="g947"
transform="matrix(0.26458333,0,0,0.26458333,-15.697697,79.233817)">
@ -349,7 +349,7 @@
sodipodi:role="line"
id="tspan1030"
x="90.395103"
y="498.28259">In the UVM run phase, the core_ibex_base_test</tspan><tspan
y="498.28259">In the UVM run phase, the core_cve2_base_test</tspan><tspan
sodipodi:role="line"
x="90.395103"
y="516.61591"
@ -361,7 +361,7 @@
sodipodi:role="line"
x="90.395103"
y="553.28259"
id="tspan1038">derive from core_ibex_base_test and override</tspan><tspan
id="tspan1038">derive from core_cve2_base_test and override</tspan><tspan
sodipodi:role="line"
x="90.395103"
y="571.61591"
@ -412,7 +412,7 @@
id="tspan983"
y="90.343819"
x="34.48238"
style="fill:#000000;stroke-width:0.26458097px">core_ibex_env</tspan></text>
style="fill:#000000;stroke-width:0.26458097px">core_cve2_env</tspan></text>
<g
transform="translate(0.26727063,-15.478201)"
id="g2312">
@ -442,7 +442,7 @@
id="text1015"><tspan
x="189.98438"
y="378.39615"
id="tspan1013">ibex_mem_intf_agent (dside)</tspan></text>
id="tspan1013">cve2_mem_intf_agent (dside)</tspan></text>
</g>
</g>
<g
@ -471,7 +471,7 @@
id="tspan1013-5"
y="104.25224"
x="34.569"
style="stroke-width:0.26458332px">ibex_cosim_agent</tspan></text>
style="stroke-width:0.26458332px">cve2_cosim_agent</tspan></text>
<g
id="g2293"
transform="translate(3.3545413,1.1339286)">
@ -498,7 +498,7 @@
style="stroke-width:0.26458332px"
x="30.930977"
y="109.68816"
id="tspan997">ibex_cosim_scoreboard</tspan></text>
id="tspan997">cve2_cosim_scoreboard</tspan></text>
</g>
</g>
<g
@ -527,7 +527,7 @@
id="text1015-74"><tspan
x="189.98438"
y="378.39615"
id="tspan1013-7">ibex_mem_intf_agent (iside)</tspan></text>
id="tspan1013-7">cve2_mem_intf_agent (iside)</tspan></text>
</g>
<g
style="stroke-linecap:butt"
@ -555,7 +555,7 @@
id="text1015-74-0"><tspan
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y="378.39615"
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id="tspan1013-7-8">cve2_irq_agent</tspan></text>
</g>
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@ -581,7 +581,7 @@
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y="161.96948"
id="tspan867-8">core_ibex_env_cfg</tspan></text>
id="tspan867-8">core_cve2_env_cfg</tspan></text>
</g>
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@ -922,7 +922,7 @@
sodipodi:role="line"
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y="187.71576">core_cve2_ifetch_if ifetch_vif</tspan></text>
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@ -959,7 +959,7 @@
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38
doc/03_reference/instruction_decode_execute.rst
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@ -15,7 +15,7 @@ The stage is made up of multiple sub-blocks which are described below.
Instruction Decode Block (ID)
-----------------------------
Source File: :file:`rtl/ibex_id_stage.sv`
Source File: :file:`rtl/cve2_id_stage.sv`
The Instruction Decode (ID) controls the overall decode/execution process.
It contains the muxes to choose what is sent to the ALU inputs and where the write data for the register file comes from.
@ -23,7 +23,7 @@ A small state machine is used to control multi-cycle instructions (see :ref:`pip
Controller
----------
Source File: :file:`rtl/ibex_controller.sv`
Source File: :file:`rtl/cve2_controller.sv`
The Controller contains the state machine that controls the overall execution of the processor.
It is responsible for:
@ -36,25 +36,25 @@ It is responsible for:
Decoder
-------
Source File: :file:`rtl/ibex_decoder.sv`
Source File: :file:`rtl/cve2_decoder.sv`
The decoder takes uncompressed instruction data and issues appropriate control signals to the other blocks to execute the instruction.
Register File
-------------
Source Files: :file:`rtl/ibex_register_file_ff.sv` :file:`rtl/ibex_register_file_fpga.sv` :file:`rtl/ibex_register_file_latch.sv`
Source Files: :file:`rtl/cve2_register_file_ff.sv` :file:`rtl/cve2_register_file_fpga.sv` :file:`rtl/cve2_register_file_latch.sv`
See :ref:`register-file` for more details.
Execute Block
-------------
Source File: :file:`rtl/ibex_ex_block.sv`
Source File: :file:`rtl/cve2_ex_block.sv`
The execute block contains the ALU and the multiplier/divider blocks, it does little beyond wiring and instantiating these blocks.
Arithmetic Logic Unit (ALU)
---------------------------
Source File: :file:`rtl/ibex_alu.sv`
Source File: :file:`rtl/cve2_alu.sv`
The Arithmetic Logic Logic (ALU) is a purely combinational block that implements operations required for the Integer Computational Instructions and the comparison operations required for the Control Transfer Instructions in the RV32I RISC-V Specification.
Other blocks use the ALU for the following tasks:
@ -66,15 +66,15 @@ Other blocks use the ALU for the following tasks:
Bit-Manipulation Extension
Support for the `RISC-V Bit-Manipulation Extension version 1.0.0 <https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf>`_ and `draft version 0.93 from January 10, 2021 <https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf>`_ is optional. [#B_draft]_
It can be enabled via the enumerated parameter ``RV32B`` defined in :file:`rtl/ibex_pkg.sv`.
By default, this parameter is set to "ibex_pkg::RV32BNone" to disable the bit-manipulation extension.
It can be enabled via the enumerated parameter ``RV32B`` defined in :file:`rtl/cve2_pkg.sv`.
By default, this parameter is set to "cve2_pkg::RV32BNone" to disable the bit-manipulation extension.
There are three versions of the bit-manipulation extension available:
The balanced version comprises a set of sub-extensions aiming for good benefits at a reasonable area overhead.
It can be selected by setting the ``RV32B`` parameter to "ibex_pkg::RV32BBalanced".
It can be selected by setting the ``RV32B`` parameter to "cve2_pkg::RV32BBalanced".
The OTEarlGrey version comprises all sub-extensions except for the Zbe.
This version can be selected by setting the ``RV32B`` parameter to "ibex_pkg::RV32BOTEarlGrey".
The full version comprises all sub-extensions and can be selected by setting the ``RV32B`` parameter to "ibex_pkg::RV32BFull".
This version can be selected by setting the ``RV32B`` parameter to "cve2_pkg::RV32BOTEarlGrey".
The full version comprises all sub-extensions and can be selected by setting the ``RV32B`` parameter to "cve2_pkg::RV32BFull".
The following table gives an overview of which sub-extensions are implemented in each version and of which instructions are implemented as multi-cycle instructions.
Multi-cycle instructions are completed in 2 cycles.
All remaining instructions complete in a single cycle.
@ -109,16 +109,16 @@ Bit-Manipulation Extension
Multiplier/Divider Block (MULT/DIV)
-----------------------------------
Source Files: :file:`rtl/ibex_multdiv_slow.sv` :file:`rtl/ibex_multdiv_fast.sv`
Source Files: :file:`rtl/cve2_multdiv_slow.sv` :file:`rtl/cve2_multdiv_fast.sv`
The Multiplier/Divider (MULT/DIV) is a state machine driven block to perform multiplication and division.
The fast and slow versions differ in multiplier only. All versions implement the same form of long division algorithm. The ALU block is used by the long division algorithm in all versions.
Multiplier
The multiplier can be implemented in three variants controlled via the enumerated parameter ``RV32M`` defined in :file:`rtl/ibex_pkg.sv`.
The multiplier can be implemented in three variants controlled via the enumerated parameter ``RV32M`` defined in :file:`rtl/cve2_pkg.sv`.
Single-Cycle Multiplier
This implementation is chosen by setting the ``RV32M`` parameter to "ibex_pkg::RV32MSingleCycle".
This implementation is chosen by setting the ``RV32M`` parameter to "cve2_pkg::RV32MSingleCycle".
The single-cycle multiplier makes use of three parallel multiplier units, designed to be mapped to hardware multiplier primitives on FPGAs.
It is therefore the **first choice for FPGA synthesis**.
@ -128,7 +128,7 @@ Multiplier
- ASIC synthesis has not yet been tested but is expected to consume 3-4x the area of the fast multiplier for ASIC.
Fast Multi-Cycle Multiplier
This implementation is chosen by setting the ``RV32M`` parameter to "ibex_pkg::RV32MFast".
This implementation is chosen by setting the ``RV32M`` parameter to "cve2_pkg::RV32MFast".
The fast multi-cycle multiplier provides a reasonable trade-off between area and performance. It is the **first choice for ASIC synthesis**.
- Completes multiply in 3-4 cycles using a MAC (multiply accumulate) which is capable of a 17-bit x 17-bit multiplication with a 34-bit accumulator.
@ -138,7 +138,7 @@ Multiplier
- In some cases it may be desirable to replace this with a specific implementation such as an explicit gate level implementation.
Slow Multi-Cycle Multiplier
To select the slow multi-cycle multiplier, set the ``RV32M`` parameter to "ibex_pkg::RV32MSlow".
To select the slow multi-cycle multiplier, set the ``RV32M`` parameter to "cve2_pkg::RV32MSlow".
- Completes multiply in clog2(``op_b``) + 1 cycles (for MUL) or 33 cycles (for MULH) using a Baugh-Wooley multiplier.
- The ALU block is used to compute additions.
@ -151,11 +151,11 @@ Divider
- Cycle 2: Compute absolute value of operand B
- Cycles 4 - 36: Perform long division as described here: https://en.wikipedia.org/wiki/Division_algorithm#Integer_division_(unsigned)_with_remainder.
By setting the ``RV32M`` parameter to "ibex_pkg::RV32MNone", the M-extension can be disabled completely.
By setting the ``RV32M`` parameter to "cve2_pkg::RV32MNone", the M-extension can be disabled completely.
Control and Status Register Block (CSR)
---------------------------------------
Source File: :file:`rtl/ibex_cs_registers.sv`
Source File: :file:`rtl/cve2_cs_registers.sv`
The CSR contains all of the CSRs (control/status registers).
Any CSR read/write is handled through this block.
@ -165,7 +165,7 @@ Further detail on the implemented CSRs can be found in :ref:`cs-registers`
Load-Store Unit (LSU)
---------------------
Source File: :file:`rtl/ibex_load_store_unit.sv`
Source File: :file:`rtl/cve2_load_store_unit.sv`
The Load-Store Unit (LSU) interfaces with main memory to perform load and store operations.
See :ref:`load-store-unit` for more details.

6
doc/03_reference/instruction_fetch.rst
View file

@ -2,7 +2,7 @@
Instruction Fetch
=================
:file:`rtl/ibex_if_stage.sv.`
:file:`rtl/cve2_if_stage.sv.`
.. figure:: images/if_stage.svg
:name: if_stage
@ -12,9 +12,9 @@ Instruction Fetch
The Instruction Fetch (IF) stage of the core is able to supply one instruction to the Instruction-Decode (ID) stage per cycle if the instruction cache or the instruction memory is able to serve one instruction per cycle.
Instructions are fetched into a prefetch buffer (:file:`rtl/ibex_prefetch_buffer.sv`) for optimal performance and timing closure reasons.
Instructions are fetched into a prefetch buffer (:file:`rtl/cve2_prefetch_buffer.sv`) for optimal performance and timing closure reasons.
This buffer simply fetches instructions linearly until it is full.
The instructions themselves are stored along with the Program Counter (PC) they came from in the fetch FIFO (:file:`rtl/ibex_fetch_fifo.sv`).
The instructions themselves are stored along with the Program Counter (PC) they came from in the fetch FIFO (:file:`rtl/cve2_fetch_fifo.sv`).
The fetch FIFO has a feedthrough path so when empty a new instruction entering the FIFO is immediately made available on the FIFO output.
A localparam ``DEPTH`` gives a configurable depth which is set to 3 by default.

2
doc/03_reference/load_store_unit.rst
View file

@ -2,7 +2,7 @@
Load-Store Unit
===============
:file:`rtl/ibex_load_store_unit.sv`
:file:`rtl/cve2_load_store_unit.sv`
The Load-Store Unit (LSU) of the core takes care of accessing the data memory.
Loads and stores of words (32 bit), half words (16 bit) and bytes (8 bit) are supported.

4
doc/03_reference/pmp.rst
View file

@ -50,5 +50,5 @@ Custom Reset Values
By default all PMP CSRs (include ``mseccfg``) are reset to 0.
Some applications may want other reset values.
Default reset values are defined in :file:`ibex_pmp_reset_default.svh`.
An implementation can either modify this file or define ``IBEX_CUSTOM_PMP_RESET_VALUES`` and place a copy of :file:`ibex_pmp_result_default.svh` in a new file, :file:`ibex_pmp_reset.svh`, changing the values as required and adding the new file to the include path of whatever build flow is being used.
Default reset values are defined in :file:`cve2_pmp_reset_default.svh`.
An implementation can either modify this file or define ``CVE2_CUSTOM_PMP_RESET_VALUES`` and place a copy of :file:`cve2_pmp_result_default.svh` in a new file, :file:`cve2_pmp_reset.svh`, changing the values as required and adding the new file to the include path of whatever build flow is being used.

10
doc/03_reference/register_file.rst
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@ -2,7 +2,7 @@
Register File
=============
Source Files: :file:`rtl/ibex_register_file_ff.sv` :file:`rtl/ibex_register_file_fpga.sv` :file:`rtl/ibex_register_file_latch.sv`
Source Files: :file:`rtl/cve2_register_file_ff.sv` :file:`rtl/cve2_register_file_fpga.sv` :file:`rtl/cve2_register_file_latch.sv`
Ibex has either 31 or 15 32-bit registers if the RV32E extension is disabled or enabled, respectively.
Register ``x0`` is statically bound to 0 and can only be read, it does not contain any sequential logic.
@ -11,7 +11,7 @@ The register file has two read ports and one write port, register file data is a
There is no write to read forwarding path so if one register is being both read and written the read will return the current value rather than the value being written.
There are three flavors of register file available, each having their own benefits and trade-offs.
The register file flavor is selected via the enumerated parameter ``RegFile`` defined in :file:`rtl/ibex_pkg.sv`.
The register file flavor is selected via the enumerated parameter ``RegFile`` defined in :file:`rtl/cve2_pkg.sv`.
Flip-Flop-Based Register File
-----------------------------
@ -20,7 +20,7 @@ The flip-flop-based register file uses regular, positive-edge-triggered flip-flo
This makes it the **first choice when simulating the design using Verilator**.
This implementation can be selected by setting the ``RegFile`` parameter to "ibex_pkg::RegFileFF".
This implementation can be selected by setting the ``RegFile`` parameter to "cve2_pkg::RegFileFF".
It is the default selection.
FPGA Register File
@ -32,7 +32,7 @@ For Xilinx FPGAs, synthesis results in an implementation using RAM32M primitives
This makes it the **first choice for FPGA synthesis**.
To select the FPGA register file, set the ``RegFile`` parameter to "ibex_pkg::RegFileFPGA".
To select the FPGA register file, set the ``RegFile`` parameter to "cve2_pkg::RegFileFPGA".
Latch-Based Register File
-------------------------
@ -46,7 +46,7 @@ Simulation of the latch-based register file is possible using commercial tools.
The latch-based register file can also be used for FPGA synthesis, but this is not recommended as FPGAs usually do not well support latches.
To select the latch-based register file, set the ``RegFile`` parameter to "ibex_pkg::RegFileLatch".
To select the latch-based register file, set the ``RegFile`` parameter to "cve2_pkg::RegFileLatch".
In addition, a technology-specific clock gating cell must be provided to keep the clock inactive when the latches are not written.
This cell must be wrapped in a module called ``prim_clock_gating``.
For more information regarding the clock gating cell, checkout :ref:`getting-started`.

4
doc/03_reference/security.rst
View file

@ -10,7 +10,7 @@ Outputs
-------
Ibex has three alert outputs for signalling security issues.
The internal major alert (**alert_major_internal_o**) indicates a critical security issue from which the core cannot recover which was detected internally in `ibex_top`.
The internal major alert (**alert_major_internal_o**) indicates a critical security issue from which the core cannot recover which was detected internally in `cve2_top`.
The bus major alert (**alert_major_internal_o**) indicates a critical security issue from which the core cannot recover which was detected on incoming bus data.
The minor alert (**alert_minor_o**) indicates potential security issues which can be monitored over time by a system.
@ -65,7 +65,7 @@ Sofware can periodically re-seed this LFSR with true random numbers (if availabl
This will make the insertion interval of dummy instructions much harder for an attacker to predict.
Note that the dummy instruction feature inserts multiply and divide instructions.
The core must be configured with a multiplier (`RV32M != ibex_pkg::RV32MNone`) or errors will occur using this feature.
The core must be configured with a multiplier (`RV32M != cve2_pkg::RV32MNone`) or errors will occur using this feature.
Bus integrity checking
----------------------

8
doc/03_reference/testplan.rst
View file

@ -30,7 +30,7 @@ Testbench Architecture
Ibex utilises a co-simulation checking approach described in detail in :ref:`cosim`.
With the co-simulation system all instructions Ibex executes and all external events such as an interrupts or memory errors are fed to a golden model.
The results of every instruction execution and every memory access are crossed checked against the golden model with any mismatches resulting in a test failure.
The aim is to check all possible externally observable behaviours of ``ibex_top`` against the golden model.
The aim is to check all possible externally observable behaviours of ``cve2_top`` against the golden model.
The golden model used is the `Spike RISC-V ISS <https://github.com/riscv-software-src/riscv-isa-sim>`_.
The testbench uses UVM.
@ -88,16 +88,16 @@ Tests
As with stimulus, test sequence development uses a coverage based approach.
Tests will be added such that all coverage in the :ref:`coverage-plan` can be hit.
Not all the details of specific tests will be documented here.
The test list (`dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml <https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml>`_), provides an exhaustive list of all tests along with a brief description of what the test does.
The test list (`dv/uvm/core_cve2/riscv_dv_extension/testlist.yaml <https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_cve2/riscv_dv_extension/testlist.yaml>`_), provides an exhaustive list of all tests along with a brief description of what the test does.
A test will execute a binary whilst running zero or more sequences that provide stimulus to external interfaces of ``ibex_top``.
A test will execute a binary whilst running zero or more sequences that provide stimulus to external interfaces of ``cve2_top``.
As the memory interfaces are all driven by Ibex, with any testbench generated activity in response to a request from Ibex, they do not require explicit sequences run by the test.
Instead the test can configure the randomisation of memory delays as it wishes.
Memory errors can be configured to always occur in statically defined areas of the memory map or a sequence can be used to inject them via the memory interface agent.
The following sequences are available for tests to use.
Each sequence is derived from a base sequence which provides controls to repeat the sequence at fixed or random internals, forever or after a random number of repeats.
Full details can be found in `dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv <https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/tests/core_ibex_seq_lib.sv>`_.
Full details can be found in `dv/uvm/core_cve2/tests/core_cve2_seq_lib.sv <https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_cve2/tests/core_cve2_seq_lib.sv>`_.
* ``irq_raise_seq`` - Raises one or more interrupts.
The testbench binary can write to a special memory location to acknowledge the interrupt and cause it to drop.

12
doc/03_reference/tracer.rst
View file

@ -3,8 +3,8 @@
Tracer
======
The module ``ibex_tracer`` can be used to create a log of the executed instructions.
It is used by ``ibex_top_tracing`` which forwards the `RVFI signals <https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md>`_ to the tracer (see also :ref:`rvfi`).
The module ``cve2_tracer`` can be used to create a log of the executed instructions.
It is used by ``cve2_top_tracing`` which forwards the `RVFI signals <https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md>`_ to the tracer (see also :ref:`rvfi`).
Output file
-----------
@ -12,8 +12,8 @@ Output file
All traced instructions are written to a log file.
By default, the log file is named ``trace_core_<HARTID>.log``, with ``<HARTID>`` being the 8 digit hart ID of the core being traced.
The file name base, defaulting to ``trace_core`` can be set using the ``ibex_tracer_file_base`` plusarg passed to the simulation.
For example, ``+ibex_tracer_file_base=ibex_my_trace`` will produce log files named ``ibex_my_trace_<HARTID>.log``.
The file name base, defaulting to ``trace_core`` can be set using the ``cve2_tracer_file_base`` plusarg passed to the simulation.
For example, ``+cve2_tracer_file_base=cve2_my_trace`` will produce log files named ``cve2_my_trace_<HARTID>.log``.
The exact syntax of passing plusargs to a simulation depends on the simulator.
Disabling the tracer
@ -21,9 +21,9 @@ Disabling the tracer
If the instruction log is not needed for a specific simulation run, the tracer can be disabled.
The plusarg ``ibex_tracer_enable`` controls the tracer.
The plusarg ``cve2_tracer_enable`` controls the tracer.
The tracer is enabled by default.
To disable the tracer use ``ibex_tracer_enable=0`` with the correct plusarg syntax of the simulator.
To disable the tracer use ``cve2_tracer_enable=0`` with the correct plusarg syntax of the simulator.
Trace output format
-------------------

44
doc/03_reference/verification.rst
View file

@ -11,7 +11,7 @@ Ibex Core
Overview
^^^^^^^^
This is a SV/UVM testbench for verification of the Ibex core, located in `dv/uvm/core_ibex`.
This is a SV/UVM testbench for verification of the Ibex core, located in `dv/uvm/core_cve2`.
At a high level, this testbench uses the open source `RISCV-DV random instruction generator
<https://github.com/google/riscv-dv>`_ to generate compiled instruction binaries, loads them into a
simple memory model, stimulates the Ibex core to run this program in memory, and then compares the
@ -32,8 +32,8 @@ A block diagram of the testbench is below.
Memory Interface Agents
"""""""""""""""""""""""
The code can be found in the `dv/uvm/core_ibex/common/ibex_mem_intf_agent
<https://github.com/lowRISC/ibex/tree/master/dv/uvm/core_ibex/common/ibex_mem_intf_agent>`_ directory.
The code can be found in the `dv/uvm/core_cve2/common/cve2_mem_intf_agent
<https://github.com/lowRISC/ibex/tree/master/dv/uvm/core_cve2/common/cve2_mem_intf_agent>`_ directory.
Two of these agents are instantiated within the testbench, one for the instruction fetch interface,
and the second for the LSU interface.
These agents run slave sequences that wait for memory requests from the core, and then grant the
@ -43,7 +43,7 @@ Interrupt Interface Agent
"""""""""""""""""""""""""
The code can be found in the
`dv/uvm/core_ibex/common/irq_agent <https://github.com/lowRISC/ibex/tree/master/dv/uvm/core_ibex/common/irq_agent>`_ directory.
`dv/uvm/core_cve2/common/irq_agent <https://github.com/lowRISC/ibex/tree/master/dv/uvm/core_cve2/common/irq_agent>`_ directory.
This agent is used to drive stimulus onto the Ibex core's interrupt pins randomly during test
execution.
@ -62,10 +62,10 @@ Test and Sequence Library
"""""""""""""""""""""""""
The code can be found in the
`dv/uvm/core_ibex/tests <https://github.com/lowRISC/ibex/tree/master/dv/uvm/core_ibex/tests>`_ directory.
`dv/uvm/core_cve2/tests <https://github.com/lowRISC/ibex/tree/master/dv/uvm/core_cve2/tests>`_ directory.
The tests here are the main sources of external stimulus generation and checking for this testbench,
as the memory interface slave sequences simply serve the core's memory requests.
The tests here are all extended from ``core_ibex_base_test``, and coordinate the entire flow for a
The tests here are all extended from ``core_cve2_base_test``, and coordinate the entire flow for a
single test, from loading the compiled assembly binary program into the testbench memory model, to
checking the Ibex core status during the test and dealing with test timeouts.
The sequences here are used to drive interrupt and debug stimulus into the core.
@ -76,8 +76,8 @@ Testplan
The goal of this bench is to fully verify the Ibex core with 100%
coverage. This includes testing all RV32IMCB instructions, privileged
spec compliance, exception and interrupt testing, Debug Mode operation etc.
The complete test list can be found in the file `dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml>`_.
The complete test list can be found in the file `dv/uvm/core_cve2/riscv_dv_extension/testlist.yaml
<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_cve2/riscv_dv_extension/testlist.yaml>`_.
For details on coverage see the :ref:`coverage-plan`.
Please note that verification is still a work in progress.
@ -123,7 +123,7 @@ to tell the RISCV-DV code where to find them:
export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv32-unknown-elf-objcopy"
export SPIKE_PATH=/path/to/spike/bin
.. _LRSpike: https://github.com/lowRISC/riscv-isa-sim/tree/ibex_cosim
.. _LRSpike: https://github.com/lowRISC/riscv-isa-sim/tree/cve2_cosim
.. _riscv-toolchain-source: https://github.com/riscv/riscv-gnu-toolchain
.. _riscv-toolchain-releases: https://github.com/lowRISC/lowrisc-toolchains/releases
.. _bitmanip-patches: https://github.com/lowRISC/lowrisc-toolchains#how-to-generate-the-bitmanip-patches
@ -154,12 +154,12 @@ any analysis that is required to increase verification effectiveness.
This mechanism is explained in detail at https://github.com/google/riscv-dv/blob/master/HANDSHAKE.md.
As a sidenote, the signature address that this testbench uses for the handshaking is ``0x8ffffffc``.
Additionally, as is mentioned in the RISCV-DV documentation of this handshake, a small set of API
tasks are provided in `dv/uvm/core_ibex/tests/core_ibex_base_test.sv
<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/tests/core_ibex_base_tests.sv>`_ to enable easy
tasks are provided in `dv/uvm/core_cve2/tests/core_cve2_base_test.sv
<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_cve2/tests/core_cve2_base_tests.sv>`_ to enable easy
and efficient integration and usage of this mechanism in this test environment.
To see how this handshake is used during real simulations, look in
`dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv>`_.
`dv/uvm/core_cve2/tests/core_cve2_test_lib.sv
<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_cve2/tests/core_cve2_test_lib.sv>`_.
As can be seen, this mechanism is extensively used to provide runtime verification for situations involving external debug
requests, interrupt assertions, and memory faults.
To add another layer of correctness checking to the checking already provided by the handshake
@ -171,11 +171,11 @@ against each other, since any code executed in the debug ROM and trap handlers s
register state in the rest of the program.
The entirety of this flow is controlled by the Makefile found at
`dv/uvm/core_ibex/Makefile <https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/Makefile>`_; here is a list of frequently used commands:
`dv/uvm/core_cve2/Makefile <https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_cve2/Makefile>`_; here is a list of frequently used commands:
.. code-block:: bash
cd dv/uvm/core_ibex
cd dv/uvm/core_cve2
# Run a full regression
make
@ -216,8 +216,8 @@ The entirety of this flow is controlled by the Makefile found at
Run with a different RTL simulator
""""""""""""""""""""""""""""""""""
You can add any compile/runtime options in `dv/uvm/core_ibex/yaml/simulator.yaml
<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_ibex/yaml/rtl_simulation.yaml>`_.
You can add any compile/runtime options in `dv/uvm/core_cve2/yaml/simulator.yaml
<https://github.com/lowRISC/ibex/blob/master/dv/uvm/core_cve2/yaml/rtl_simulation.yaml>`_.
.. code-block:: bash
@ -244,10 +244,10 @@ classes that provides basic UVM testbench functionality and components.
This DV environment will be compiled and simulated using the `dvsim simulation tool
<https://github.com/lowRISC/opentitan/tree/master/util/dvsim>`_.
The master ``.hjson`` file that controls simulation with ``dvsim`` can be found
at `dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson
<https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson>`_.
The associated testplan ``.hjson`` file is located at `dv/uvm/icache/data/ibex_icache_testplan.hjson
<https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/data/ibex_icache_testplan.hjson>`_.
at `dv/uvm/icache/dv/cve2_icache_sim_cfg.hjson
<https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/dv/cve2_icache_sim_cfg.hjson>`_.
The associated testplan ``.hjson`` file is located at `dv/uvm/icache/data/cve2_icache_testplan.hjson
<https://github.com/lowRISC/ibex/blob/master/dv/uvm/icache/data/cve2_icache_testplan.hjson>`_.
As this testbench is still in its infancy, it is currently only able to be compiled, as no tests or
sequences are implemented, nor are there any entries in the testplan file.
To build the testbench locally using the VCS simulator, run the following command from the root of
@ -255,7 +255,7 @@ the Ibex repository:
.. code-block:: bash
./vendor/lowrisc_ip/util/dvsim/dvsim.py dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson --build-only
./vendor/lowrisc_ip/util/dvsim/dvsim.py dv/uvm/icache/dv/cve2_icache_sim_cfg.hjson --build-only
--skip-ral --purge --sr sim_out
Specify the intended output directory using either the ``--sr`` or ``-scratch-root`` option.

6
dv/riscv_compliance/README.md
View file

@ -37,13 +37,13 @@ How to run RISC-V Compliance on Ibex
```sh
cd $IBEX_REPO_BASE
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_riscv_compliance --RV32E=0 --RV32M=ibex_pkg::RV32MNone
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:cve2:cve2_riscv_compliance --RV32E=0 --RV32M=cve2_pkg::RV32MNone
```
You can use the two compile-time options `--RV32M` and `--RV32E` to
enable/disable the M and E ISA extensions, respectively.
You can now find the compiled simulation at `build/lowrisc_ibex_ibex_riscv_compliance_0.1/sim-verilator/Vibex_riscv_compliance`.
You can now find the compiled simulation at `build/lowrisc_cve2_cve2_riscv_compliance_0.1/sim-verilator/Vcve2_riscv_compliance`.
2. Get the RISC-V Compliance test suite
@ -60,7 +60,7 @@ How to run RISC-V Compliance on Ibex
# adjust to match your compiler name
export RISCV_PREFIX=riscv32-unknown-elf-
# give the absolute path to the simulation binary compiled in step 1
export TARGET_SIM=/path/to/your/Vibex_riscv_compliance
export TARGET_SIM=/path/to/your/Vcve2_riscv_compliance
export RISCV_DEVICE=rv32imc
export RISCV_TARGET=ibex

4
dv/riscv_compliance/ibex_riscv_compliance.cc → dv/riscv_compliance/cve2_riscv_compliance.cc
View file

@ -7,14 +7,14 @@
#include "verilator_sim_ctrl.h"
int main(int argc, char **argv) {
ibex_riscv_compliance top;
cve2_riscv_compliance top;
VerilatorMemUtil memutil;
VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
simctrl.SetTop(&top, &top.IO_CLK, &top.IO_RST_N,
VerilatorSimCtrlFlags::ResetPolarityNegative);
MemArea ram(
"TOP.ibex_riscv_compliance.u_ram.u_ram.gen_generic.u_impl_generic",
"TOP.cve2_riscv_compliance.u_ram.u_ram.gen_generic.u_impl_generic",
64 * 1024 / 4, 4);
memutil.RegisterMemoryArea("ram", 0x0, &ram);

26
dv/riscv_compliance/ibex_riscv_compliance.core → dv/riscv_compliance/cve2_riscv_compliance.core
View file

@ -2,15 +2,15 @@ CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_riscv_compliance:0.1"
name: "lowrisc:cve2:cve2_riscv_compliance:0.1"
description: "Ibex simulation for RISC-V compliance testing (using Verilator)"
filesets:
files_sim:
depend:
- lowrisc:ibex:ibex_top_tracing
- lowrisc:ibex:sim_shared
- lowrisc:cve2:cve2_top_tracing
- lowrisc:cve2:sim_shared
files:
- rtl/ibex_riscv_compliance.sv
- rtl/cve2_riscv_compliance.sv
- rtl/riscv_testutil.sv
file_type: systemVerilogSource
@ -19,7 +19,7 @@ filesets:
- lowrisc:dv_verilator:memutil_verilator
- lowrisc:dv_verilator:simutil_verilator
files:
- ibex_riscv_compliance.cc: { file_type: cppSource }
- cve2_riscv_compliance.cc: { file_type: cppSource }
- lint/verilator_waiver.vlt: {file_type: vlt}
parameters:
@ -31,21 +31,21 @@ parameters:
RV32M:
datatype: str
default: ibex_pkg::RV32MFast
default: cve2_pkg::RV32MFast
paramtype: vlogdefine
description: "RV32M implementation parameter enum. See the ibex_pkg::rv32m_e enum in ibex_pkg.sv for permitted values."
description: "RV32M implementation parameter enum. See the cve2_pkg::rv32m_e enum in cve2_pkg.sv for permitted values."
RV32B:
datatype: str
default: ibex_pkg::RV32BNone
default: cve2_pkg::RV32BNone
paramtype: vlogdefine
description: "Bitmanip implementation parameter enum. See the ibex_pkg::rv32b_e enum in ibex_pkg.sv for permitted values."
description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values."
RegFile:
datatype: str
default: ibex_pkg::RegFileFF
default: cve2_pkg::RegFileFF
paramtype: vlogdefine
description: "Register file implementation parameter enum. See the ibex_pkg::regfile_e enum in ibex_pkg.sv for permitted values."
description: "Register file implementation parameter enum. See the cve2_pkg::regfile_e enum in cve2_pkg.sv for permitted values."
ICache:
datatype: int
@ -128,7 +128,7 @@ targets:
- PMPNumRegions
- SecureIbex
- ICacheScramble
toplevel: ibex_riscv_compliance
toplevel: cve2_riscv_compliance
tools:
verilator:
mode: cc
@ -140,6 +140,6 @@ targets:
- '--trace-structs'
- '--trace-params'
- '--trace-max-array 1024'
- '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_riscv_compliance -g"'
- '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=cve2_riscv_compliance -g"'
- '-LDFLAGS "-pthread -lutil -lelf"'
- "-Wall"

2
dv/riscv_compliance/lint/verilator_waiver.vlt
View file

@ -28,5 +28,5 @@
// matches when you set a 1-bit value to a literal 1, so it won't hide
// silly mistakes like setting it to 2.
//
lint_off -rule WIDTH -file "*/rtl/ibex_riscv_compliance.sv"
lint_off -rule WIDTH -file "*/rtl/cve2_riscv_compliance.sv"
-match "*expects 1 bits*Initial value's CONST '32'h1'*"

12
dv/riscv_compliance/rtl/ibex_riscv_compliance.sv → dv/riscv_compliance/rtl/cve2_riscv_compliance.sv
View file

@ -10,7 +10,7 @@
* simulators (if the top-level clk and rst ports are replaced with a generated
* clock).
*/
module ibex_riscv_compliance (
module cve2_riscv_compliance (
input IO_CLK,
input IO_RST_N
);
@ -19,9 +19,9 @@ module ibex_riscv_compliance (
parameter int unsigned PMPGranularity = 0;
parameter int unsigned PMPNumRegions = 4;
parameter bit RV32E = 1'b0;
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast;
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone;
parameter ibex_pkg::regfile_e RegFile = ibex_pkg::RegFileFF;
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast;
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone;
parameter cve2_pkg::regfile_e RegFile = cve2_pkg::RegFileFF;
parameter bit BranchTargetALU = 1'b0;
parameter bit WritebackStage = 1'b0;
parameter bit ICache = 1'b0;
@ -113,7 +113,7 @@ module ibex_riscv_compliance (
.cfg_device_addr_mask
);
ibex_top_tracing #(
cve2_top_tracing #(
.PMPEnable (PMPEnable ),
.PMPGranularity (PMPGranularity ),
.PMPNumRegions (PMPNumRegions ),
@ -177,7 +177,7 @@ module ibex_riscv_compliance (
.crash_dump_o ( ),
.double_fault_seen_o ( ),
.fetch_enable_i (ibex_pkg::FetchEnableOn),
.fetch_enable_i (cve2_pkg::FetchEnableOn),
.alert_minor_o ( ),
.alert_major_internal_o ( ),
.alert_major_bus_o ( ),

10
examples/fpga/artya7/README.md
View file

@ -53,11 +53,11 @@ Run either of the following commands at the top level to build the respective ha
Both variants of the Arty A7 are supported and can be selected via the `--parts` parameter.
```
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a35ticsg324-1L
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:cve2:top_artya7 --part xc7a35ticsg324-1L
```
```
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:cve2:top_artya7 --part xc7a100tcsg324-1
```
This will create a directory `build` which contains the output files, including
@ -70,7 +70,7 @@ Example use case includes loading `coremark.vmem` which can be used for performa
Please see [CoreMark README](https://github.com/lowRISC/ibex/blob/master/examples/sw/benchmarks/README.md) for compiling CoreMark.
```
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1 --SRAMInitFile=examples/sw/benchmarks/coremark/coremark.vmem
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:cve2:top_artya7 --part xc7a100tcsg324-1 --SRAMInitFile=examples/sw/benchmarks/coremark/coremark.vmem
```
#### Power Analysis Using Vivado
@ -81,7 +81,7 @@ This switching activity is then used to generate a detailed power report.
In order to use it with CoreMark run the command below
```
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1 --SRAMInitFile=examples/sw/benchmarks/coremark/coremark.vmem --FPGAPowerAnalysis=1
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:cve2:top_artya7 --part xc7a100tcsg324-1 --SRAMInitFile=examples/sw/benchmarks/coremark/coremark.vmem --FPGAPowerAnalysis=1
```
## Program
@ -89,7 +89,7 @@ fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya
After the board is connected to the computer it can be programmed with:
```
fusesoc --cores-root=. run --target=synth --run lowrisc:ibex:top_artya7
fusesoc --cores-root=. run --target=synth --run lowrisc:cve2:top_artya7
```
LED1/LED3 and LED0/LED2 should alternately be on after the FPGA programming is finished.

4
examples/fpga/artya7/rtl/top_artya7.sv
View file

@ -35,8 +35,8 @@ module top_artya7 (
logic [31:0] data_wdata;
logic [31:0] data_rdata;
ibex_top #(
.RegFile(ibex_pkg::RegFileFPGA),
cve2_top #(
.RegFile(cve2_pkg::RegFileFPGA),
.DmHaltAddr(32'h00000000),
.DmExceptionAddr(32'h00000000)
) u_top (

6
examples/fpga/artya7/top_artya7.core
View file

@ -2,13 +2,13 @@ CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:top_artya7:0.1"
name: "lowrisc:cve2:top_artya7:0.1"
description: "Ibex example toplevel for Arty A7 boards (both, -35 and -100)"
filesets:
files_rtl_artya7:
depend:
- lowrisc:ibex:ibex_top
- lowrisc:ibex:fpga_xilinx_shared
- lowrisc:cve2:cve2_top
- lowrisc:cve2:fpga_xilinx_shared
files:
- rtl/top_artya7.sv
file_type: systemVerilogSource

6
examples/fpga/artya7/util/vivado_hook_write_bitstream_pre.tcl
View file

@ -1,4 +1,4 @@
open_project ../../lowrisc_ibex_top_artya7_0.1.xpr
open_project ../../lowrisc_cve2_top_artya7_0.1.xpr
set saif_name "detailed_power.saif"
open_run impl_1
@ -18,7 +18,7 @@ close_saif
# Reporting power using .saif generated above
open_run impl_1
set_operating_conditions -process maximum
read_saif "../../lowrisc_ibex_top_artya7_0.1.sim/sim_1/impl/func/xsim/$saif_name"
read_saif "../../lowrisc_ibex_top_artya7_0.1.sim/sim_1/impl/func/xsim/$saif_name" -strip_path top_artya7
read_saif "../../lowrisc_cve2_top_artya7_0.1.sim/sim_1/impl/func/xsim/$saif_name"
read_saif "../../lowrisc_cve2_top_artya7_0.1.sim/sim_1/impl/func/xsim/$saif_name" -strip_path top_artya7
set_units -power uW
report_power -name {detailed_power_report} -verbose -file post_implementation_power_result.log -hierarchical_depth 20

14
examples/simple_system/README.md
View file

@ -31,7 +31,7 @@ The Simple System simulator binary can be built via FuseSoC. From the Ibex
repository root run:
```
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system --RV32E=0 --RV32M=ibex_pkg::RV32MFast
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:cve2:cve2_simple_system --RV32E=0 --RV32M=cve2_pkg::RV32MFast
```
## Building Software
@ -60,7 +60,7 @@ correct compiler binaries.
Having built the simulator and software, from the Ibex repository root run:
```
./build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system [-t] --meminit=ram,<sw_elf_file>
./build/lowrisc_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system [-t] --meminit=ram,<sw_elf_file>
```
`<sw_elf_file>` should be a path to an ELF file (or alternatively a vmem file)
@ -97,8 +97,8 @@ Compressed Instructions: 182
The simulator produces several output files
* `ibex_simple_system.log` - The ASCII output written via the output peripheral
* `ibex_simple_system_pcount.csv` - A CSV of the performance counters
* `cve2_simple_system.log` - The ASCII output written via the output peripheral
* `cve2_simple_system_pcount.csv` - A CSV of the performance counters
* `trace_core_00000000.log` - An instruction trace of execution
## Simulating with Synopsys VCS
@ -106,7 +106,7 @@ The simulator produces several output files
Similar to the Verilator flow the Simple System simulator binary can be built using:
```
fusesoc --cores-root=. run --target=sim --tool=vcs --setup --build lowrisc:ibex:ibex_simple_system --RV32E=0 --RV32M=ibex_pkg::RV32MFast --SRAMInitFile=`<sw_vmem_file>`
fusesoc --cores-root=. run --target=sim --tool=vcs --setup --build lowrisc:cve2:cve2_simple_system --RV32E=0 --RV32M=cve2_pkg::RV32MFast --SRAMInitFile=`<sw_vmem_file>`
```
`<sw_vmem_file>` should be a path to a vmem file built as described above, use
@ -116,7 +116,7 @@ binary.
To run the simulator:
```
./build/lowrisc_ibex_ibex_simple_system_0/sim-vcs/lowrisc_ibex_ibex_simple_system_0
./build/lowrisc_cve2_cve2_simple_system_0/sim-vcs/lowrisc_cve2_cve2_simple_system_0
```
Pass `-gui` to use the DVE GUI.
@ -126,7 +126,7 @@ Pass `-gui` to use the DVE GUI.
To build and run Simple System run:
```
fusesoc --cores-root=. run --target=sim --tool=rivierapro lowrisc:ibex:ibex_simple_system --RV32E=0 --RV32M=ibex_pkg::RV32MFast --SRAMInitFile=\"$(readlink -f <sw_vmem_file>)\"
fusesoc --cores-root=. run --target=sim --tool=rivierapro lowrisc:cve2:cve2_simple_system --RV32E=0 --RV32M=cve2_pkg::RV32MFast --SRAMInitFile=\"$(readlink -f <sw_vmem_file>)\"
```
`<sw_vmem_file>` should be a path to a vmem file built as described above, use

30
examples/simple_system/ibex_simple_system.cc → examples/simple_system/cve2_simple_system.cc
View file

@ -6,9 +6,9 @@
#include <fstream>
#include <iostream>
#include "Vibex_simple_system__Syms.h"
#include "ibex_pcounts.h"
#include "ibex_simple_system.h"
#include "Vcve2_simple_system__Syms.h"
#include "cve2_pcounts.h"
#include "cve2_simple_system.h"
#include "verilated_toplevel.h"
#include "verilator_memutil.h"
#include "verilator_sim_ctrl.h"
@ -34,18 +34,18 @@ int SimpleSystem::Main(int argc, char **argv) {
}
std::string SimpleSystem::GetIsaString() const {
const Vibex_simple_system &top = _top;
assert(top.ibex_simple_system);
const Vcve2_simple_system &top = _top;
assert(top.cve2_simple_system);
std::string base = top.ibex_simple_system->RV32E ? "rv32e" : "rv32i";
std::string base = top.cve2_simple_system->RV32E ? "rv32e" : "rv32i";
std::string extensions = "c";
if (top.ibex_simple_system->RV32M)
if (top.cve2_simple_system->RV32M)
extensions += "m";
// See the equivalent get_isa_string() function in core_ibex_base_test.sv for
// See the equivalent get_isa_string() function in core_cve2_base_test.sv for
// an explanation of the different ISA strings
switch (top.ibex_simple_system->RV32B) {
switch (top.cve2_simple_system->RV32B) {
case 0: // RV32BNone
break;
@ -92,17 +92,17 @@ bool SimpleSystem::Finish() {
return false;
}
// Set the scope to the root scope, the ibex_pcount_string function otherwise
// doesn't know the scope itself. Could be moved to ibex_pcount_string, but
// Set the scope to the root scope, the cve2_pcount_string function otherwise
// doesn't know the scope itself. Could be moved to cve2_pcount_string, but
// would require a way to set the scope name from here, similar to MemUtil.
svSetScope(svGetScopeFromName("TOP.ibex_simple_system"));
svSetScope(svGetScopeFromName("TOP.cve2_simple_system"));
std::cout << "\nPerformance Counters" << std::endl
<< "====================" << std::endl;
std::cout << ibex_pcount_string(false);
std::cout << cve2_pcount_string(false);
std::ofstream pcount_csv("ibex_simple_system_pcount.csv");
pcount_csv << ibex_pcount_string(true);
std::ofstream pcount_csv("cve2_simple_system_pcount.csv");
pcount_csv << cve2_pcount_string(true);
return true;
}

22
examples/simple_system/ibex_simple_system.core → examples/simple_system/cve2_simple_system.core
View file

@ -2,14 +2,14 @@ CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_simple_system"
name: "lowrisc:cve2:cve2_simple_system"
description: "Generic simple system for running binaries on ibex using verilator"
filesets:
files_simple_system:
depend:
- lowrisc:ibex:ibex_simple_system_core
- lowrisc:cve2:cve2_simple_system_core
files:
- ibex_simple_system_main.cc
- cve2_simple_system_main.cc
file_type: cppSource
parameters:
@ -21,21 +21,21 @@ parameters:
RV32M:
datatype: str
default: ibex_pkg::RV32MFast
default: cve2_pkg::RV32MFast
paramtype: vlogdefine
description: "RV32M implementation parameter enum. See the ibex_pkg::rv32m_e enum in ibex_pkg.sv for permitted values."
description: "RV32M implementation parameter enum. See the cve2_pkg::rv32m_e enum in cve2_pkg.sv for permitted values."
RV32B:
datatype: str
default: ibex_pkg::RV32BNone
default: cve2_pkg::RV32BNone
paramtype: vlogdefine
description: "Bitmanip implementation parameter enum. See the ibex_pkg::rv32b_e enum in ibex_pkg.sv for permitted values."
description: "Bitmanip implementation parameter enum. See the cve2_pkg::rv32b_e enum in cve2_pkg.sv for permitted values."
RegFile:
datatype: str
default: ibex_pkg::RegFileFF
default: cve2_pkg::RegFileFF
paramtype: vlogdefine
description: "Register file implementation parameter enum. See the ibex_pkg::regfile_e enum in ibex_pkg.sv for permitted values."
description: "Register file implementation parameter enum. See the cve2_pkg::regfile_e enum in cve2_pkg.sv for permitted values."
ICache:
datatype: int
@ -106,7 +106,7 @@ targets:
default: &default_target
filesets:
- files_simple_system
toplevel: ibex_simple_system
toplevel: cve2_simple_system
parameters:
- RV32E
- RV32M
@ -154,7 +154,7 @@ targets:
- '--trace-structs'
- '--trace-params'
- '--trace-max-array 1024'
- '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_simple_system -g"'
- '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=cve2_simple_system -g"'
- '-LDFLAGS "-pthread -lutil -lelf"'
- "-Wall"
- "-Wwarn-IMPERFECTSCH"

2
examples/simple_system/ibex_simple_system.h → examples/simple_system/cve2_simple_system.h
View file

@ -16,7 +16,7 @@ class SimpleSystem {
std::string GetIsaString() const;
protected:
ibex_simple_system _top;
cve2_simple_system _top;
VerilatorMemUtil _memutil;
MemArea _ram;

14
examples/simple_system/ibex_simple_system_core.core → examples/simple_system/cve2_simple_system_core.core
View file

@ -2,25 +2,25 @@ CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_simple_system_core"
name: "lowrisc:cve2:cve2_simple_system_core"
description: "Generic simple system for running binaries on ibex using verilator"
filesets:
files_sim:
depend:
- lowrisc:ibex:ibex_top_tracing
- lowrisc:ibex:sim_shared
- lowrisc:cve2:cve2_top_tracing
- lowrisc:cve2:sim_shared
files:
- rtl/ibex_simple_system.sv
- rtl/cve2_simple_system.sv
file_type: systemVerilogSource
files_verilator:
depend:
- lowrisc:dv_verilator:memutil_verilator
- lowrisc:dv_verilator:simutil_verilator
- lowrisc:dv_verilator:ibex_pcounts
- lowrisc:dv_verilator:cve2_pcounts
files:
- ibex_simple_system.cc: { file_type: cppSource }
- ibex_simple_system.h: { file_type: cppSource, is_include_file: true}
- cve2_simple_system.cc: { file_type: cppSource }
- cve2_simple_system.h: { file_type: cppSource, is_include_file: true}
- lint/verilator_waiver.vlt: {file_type: vlt}
files_lint_verible:

4
examples/simple_system/ibex_simple_system_main.cc → examples/simple_system/cve2_simple_system_main.cc
View file

@ -2,11 +2,11 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
#include "ibex_simple_system.h"
#include "cve2_simple_system.h"
int main(int argc, char **argv) {
SimpleSystem simple_system(
"TOP.ibex_simple_system.u_ram.u_ram.gen_generic.u_impl_generic",
"TOP.cve2_simple_system.u_ram.u_ram.gen_generic.u_impl_generic",
1024 * 1024);
return simple_system.Main(argc, argv);

2
examples/simple_system/lint/verible_waiver.vbw
View file

@ -1 +1 @@
waive --rule=macro-name-style --location="ibex_simple_system.sv" --regex="RegFile"
waive --rule=macro-name-style --location="cve2_simple_system.sv" --regex="RegFile"

8
examples/simple_system/lint/verilator_waiver.vlt
View file

@ -28,13 +28,13 @@
// matches when you set a 1-bit value to a literal 1, so it won't hide
// silly mistakes like setting it to 2.
//
lint_off -rule WIDTH -file "*/rtl/ibex_simple_system.sv"
lint_off -rule WIDTH -file "*/rtl/cve2_simple_system.sv"
-match "*expects 1 bits*Initial value's CONST '32'h1'*"
// This isn't a waiver, as such, but rather tells Verilator to expose
// the given parameters' values to C++. This allows cosim to figure
// out what flavour of core it is running, which allows us to call
// Spike with the right ISA.
public -module "ibex_simple_system" -var "RV32E"
public -module "ibex_simple_system" -var "RV32M"
public -module "ibex_simple_system" -var "RV32B"
public -module "cve2_simple_system" -var "RV32E"
public -module "cve2_simple_system" -var "RV32M"
public -module "cve2_simple_system" -var "RV32B"

22
examples/simple_system/rtl/ibex_simple_system.sv → examples/simple_system/rtl/cve2_simple_system.sv
View file

@ -7,15 +7,15 @@
// default. Other simulators don't take the detour via `define and can override the corresponding
// parameters directly.
`ifndef RV32M
`define RV32M ibex_pkg::RV32MFast
`define RV32M cve2_pkg::RV32MFast
`endif
`ifndef RV32B
`define RV32B ibex_pkg::RV32BNone
`define RV32B cve2_pkg::RV32BNone
`endif
`ifndef RegFile
`define RegFile ibex_pkg::RegFileFF
`define RegFile cve2_pkg::RegFileFF
`endif
/**
@ -30,7 +30,7 @@
* simulator_ctrl module.
*/
module ibex_simple_system (
module cve2_simple_system (
input IO_CLK,
input IO_RST_N
);
@ -41,9 +41,9 @@ module ibex_simple_system (
parameter int unsigned PMPGranularity = 0;
parameter int unsigned PMPNumRegions = 4;
parameter bit RV32E = 1'b0;
parameter ibex_pkg::rv32m_e RV32M = `RV32M;
parameter ibex_pkg::rv32b_e RV32B = `RV32B;
parameter ibex_pkg::regfile_e RegFile = `RegFile;
parameter cve2_pkg::rv32m_e RV32M = `RV32M;
parameter cve2_pkg::rv32b_e RV32B = `RV32B;
parameter cve2_pkg::regfile_e RegFile = `RegFile;
parameter bit BranchTargetALU = 1'b0;
parameter bit WritebackStage = 1'b0;
parameter bit ICache = 1'b0;
@ -162,7 +162,7 @@ module ibex_simple_system (
.cfg_device_addr_mask
);
ibex_top_tracing #(
cve2_top_tracing #(
.SecureIbex ( SecureIbex ),
.ICacheScramble ( ICacheScramble ),
.PMPEnable ( PMPEnable ),
@ -227,7 +227,7 @@ module ibex_simple_system (
.crash_dump_o (),
.double_fault_seen_o (),
.fetch_enable_i (ibex_pkg::FetchEnableOn),
.fetch_enable_i (cve2_pkg::FetchEnableOn),
.alert_minor_o (),
.alert_major_internal_o (),
.alert_major_bus_o (),
@ -260,7 +260,7 @@ module ibex_simple_system (
);
simulator_ctrl #(
.LogName("ibex_simple_system.log")
.LogName("cve2_simple_system.log")
) u_simulator_ctrl (
.clk_i (clk_sys),
.rst_ni (rst_sys_n),
@ -295,7 +295,7 @@ module ibex_simple_system (
export "DPI-C" function mhpmcounter_get;
function automatic longint unsigned mhpmcounter_get(int index);
return u_top.u_ibex_top.u_ibex_core.cs_registers_i.mhpmcounter[index];
return u_top.u_cve2_top.u_cve2_core.cs_registers_i.mhpmcounter[index];
endfunction
endmodule

6
examples/sw/benchmarks/README.md
View file

@ -11,7 +11,7 @@ All of these benchmarks run on Simple System. A verilator simulation suitable
for running them can be built with:
```
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system --RV32E=0 --RV32M=ibex_pkg::RV32MFast
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:cve2:cve2_simple_system --RV32E=0 --RV32M=cve2_pkg::RV32MFast
```
See examples/simple_system/README.md for full details.
@ -35,13 +35,13 @@ make -C ./examples/sw/benchmarks/coremark/
To run CoreMark (after building a suitable simulator binary, see above):
```
build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system --meminit=ram,examples/sw/benchmarks/coremark/coremark.elf
build/lowrisc_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system --meminit=ram,examples/sw/benchmarks/coremark/coremark.elf
```
The simulator outputs the performance counter values observed for the benchmark
(the counts do not include anything from pre or post benchmark loops).
CoreMark should output (to `ibex_simple_system.log`) something like the
CoreMark should output (to `cve2_simple_system.log`) something like the
following:
```

0
examples/sw/benchmarks/coremark/ibex/core_portme.c → examples/sw/benchmarks/coremark/cve2/core_portme.c
View file

0
examples/sw/benchmarks/coremark/ibex/core_portme.h → examples/sw/benchmarks/coremark/cve2/core_portme.h
View file

0
examples/sw/benchmarks/coremark/ibex/core_portme.mak → examples/sw/benchmarks/coremark/cve2/core_portme.mak
View file

0
examples/sw/benchmarks/coremark/ibex/ee_printf.c → examples/sw/benchmarks/coremark/cve2/ee_printf.c
View file

8
examples/sw/led/led.c
View file

@ -8,7 +8,7 @@
/**
* Delay loop executing within 8 cycles on ibex
*/
static void delay_loop_ibex(unsigned long loops) {
static void delay_loop_cve2(unsigned long loops) {
int out; /* only to notify compiler of modifications to |loops| */
asm volatile(
"1: nop \n" // 1 cycle
@ -22,16 +22,16 @@ static void delay_loop_ibex(unsigned long loops) {
);
}
static int usleep_ibex(unsigned long usec) {
static int usleep_cve2(unsigned long usec) {
unsigned long usec_cycles;
usec_cycles = CLK_FIXED_FREQ_HZ * usec / 1000 / 1000 / 8;
delay_loop_ibex(usec_cycles);
delay_loop_cve2(usec_cycles);
return 0;
}
static int usleep(unsigned long usec) {
return usleep_ibex(usec);
return usleep_cve2(usec);
}
int main(int argc, char **argv) {

2
formal/data_ind_timing/Makefile
View file

@ -4,7 +4,7 @@
# A simple wrapper around fusesoc to make it a bit easier to run the formal flow
core-name := lowrisc:fpv:ibex_data_ind_timing
core-name := lowrisc:fpv:cve2_data_ind_timing
vlnv := $(subst :,_,$(core-name))
build-root := $(abspath ../../build/$(vlnv))

10
formal/data_ind_timing/ibex_data_ind_timing.core → formal/data_ind_timing/cve2_data_ind_timing.core
View file

@ -3,14 +3,14 @@ CAPI=2:
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:fpv:ibex_data_ind_timing:0.1"
name: "lowrisc:fpv:cve2_data_ind_timing:0.1"
description: "Formal test for data independent timing"
filesets:
testbench:
depend:
- lowrisc:ibex:ibex_pkg
- lowrisc:ibex:ibex_multdiv
- lowrisc:cve2:cve2_pkg
- lowrisc:cve2:cve2_multdiv
- lowrisc:util:sv2v
files:
- run.sby.j2 : {file_type: sbyConfigTemplate}
@ -76,7 +76,7 @@ targets:
slow: &slow
filesets:
- testbench
toplevel: ibex_multdiv_slow
toplevel: cve2_multdiv_slow
default_tool: symbiyosys
tools:
symbiyosys:
@ -113,7 +113,7 @@ targets:
fast: &fast
<<: *slow
toplevel: ibex_multdiv_fast
toplevel: cve2_multdiv_fast
tools:
symbiyosys:
tasknames:

4
formal/data_ind_timing/formal_tb.sv
View file

@ -14,7 +14,7 @@ module formal_tb (
input logic div_en_i, // dynamic enable signal, for FSM control
input logic mult_sel_i, // static decoder input, for data muxes
input logic div_sel_i, // static decoder input, for data muxes
input ibex_pkg::md_op_e operator_i,
input cve2_pkg::md_op_e operator_i,
input logic [1:0] signed_mode_i,
input logic [31:0] op_a_i,
input logic [31:0] op_b_i,
@ -37,7 +37,7 @@ module formal_tb (
input logic valid_o
);
import ibex_pkg::*;
import cve2_pkg::*;
logic [2:0] f_startup_count = 3'd0;
always_ff @(posedge clk_i) begin : reset_assertion

2
formal/data_ind_timing/operation_div.svh
View file

@ -13,7 +13,7 @@ always_comb begin
// Enable signal must be asserted in order for the state machine to advance
assume (div_en_i);
assume (div_sel_i);
assume (operator_i == ibex_pkg::MD_OP_DIV);
assume (operator_i == cve2_pkg::MD_OP_DIV);
end else begin
assume (~div_en_i);
assume (~div_sel_i);

2
formal/data_ind_timing/operation_mulh.svh
View file

@ -13,7 +13,7 @@ always_comb begin
// Enable signal must be asserted in order for the state machine to advance
assume (mult_en_i);
assume (mult_sel_i);
assume (operator_i == ibex_pkg::MD_OP_MULH);
assume (operator_i == cve2_pkg::MD_OP_MULH);
end else begin
assume (~mult_en_i);
assume (~mult_sel_i);

2
formal/data_ind_timing/operation_mull.svh
View file

@ -13,7 +13,7 @@ always_comb begin
// Enable signal must be asserted in order for the state machine to advance
assume (mult_en_i);
assume (mult_sel_i);
assume (operator_i == ibex_pkg::MD_OP_MULL);
assume (operator_i == cve2_pkg::MD_OP_MULL);
end else begin
assume (~mult_en_i);
assume (~mult_sel_i);

2
formal/data_ind_timing/operation_rem.svh
View file

@ -13,7 +13,7 @@ always_comb begin
// Enable signal must be asserted in order for the state machine to advance
assume (div_en_i);
assume (div_sel_i);
assume (operator_i == ibex_pkg::MD_OP_REM);
assume (operator_i == cve2_pkg::MD_OP_REM);
end else begin
assume (~div_en_i);
assume (~div_sel_i);

2
formal/icache/Makefile
View file

@ -7,7 +7,7 @@
# Whether to use ECC (0 for disabled; 1 for enabled)
ECC := 0
core-name := lowrisc:fpv:ibex_icache_fpv
core-name := lowrisc:fpv:cve2_icache_fpv
vlnv := $(subst :,_,$(core-name))
build-root := $(abspath ../../build/$(vlnv))

6
formal/icache/ibex_icache_fpv.core → formal/icache/cve2_icache_fpv.core
View file

@ -3,13 +3,13 @@ CAPI=2:
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:fpv:ibex_icache_fpv:0.1"
name: "lowrisc:fpv:cve2_icache_fpv:0.1"
description: "Formal properties for Ibex ICache"
filesets:
all:
depend:
- lowrisc:ibex:ibex_icache
- lowrisc:cve2:cve2_icache
- lowrisc:prim:assert
- lowrisc:util:sv2v
files:
@ -30,7 +30,7 @@ targets:
- ICacheECC
filesets:
- all
toplevel: ibex_icache
toplevel: cve2_icache
default_tool: symbiyosys
tools:
symbiyosys:

2
formal/icache/formal_tb.sv
View file

@ -16,7 +16,7 @@
`ASSUME(name``_zero_in_reset, `IMPLIES(!rst_ni, ~|(name)), clk_i, 1'b0)
module formal_tb
import ibex_pkg::*;
import cve2_pkg::*;
#(
// DUT parameters
parameter bit BranchPredictor = 1'b0,

50
formal/riscv-formal/Makefile
View file

@ -5,7 +5,7 @@
# Provide a convenient way to create a Verilog source of Ibex.
# This is used by riscv-formal. See README.md for more details.
IBEX_ENABLE_WB ?= 0
CVE2_ENABLE_WB ?= 0
# Name of the output file
IBEX_OUT := ibex.v
@ -28,29 +28,29 @@ INC_DIRS := \
# SystemVerilog sources of Ibex
SRCS_SV ?= \
$(SRC_DIR)/ibex_alu.sv \
$(SRC_DIR)/ibex_compressed_decoder.sv \
$(SRC_DIR)/ibex_controller.sv \
$(SRC_DIR)/ibex_counter.sv \
$(SRC_DIR)/ibex_csr.sv \
$(SRC_DIR)/ibex_cs_registers.sv \
$(SRC_DIR)/ibex_decoder.sv \
$(SRC_DIR)/ibex_ex_block.sv \
$(SRC_DIR)/ibex_fetch_fifo.sv \
$(SRC_DIR)/ibex_id_stage.sv \
$(SRC_DIR)/ibex_if_stage.sv \
$(SRC_DIR)/ibex_load_store_unit.sv \
$(SRC_DIR)/ibex_multdiv_fast.sv \
$(SRC_DIR)/ibex_multdiv_slow.sv \
$(SRC_DIR)/ibex_prefetch_buffer.sv \
$(SRC_DIR)/ibex_pmp.sv \
$(SRC_DIR)/ibex_register_file_ff.sv \
$(SRC_DIR)/ibex_wb_stage.sv \
$(SRC_DIR)/ibex_core.sv \
$(SRC_DIR)/ibex_top.sv
$(SRC_DIR)/cve2_alu.sv \
$(SRC_DIR)/cve2_compressed_decoder.sv \
$(SRC_DIR)/cve2_controller.sv \
$(SRC_DIR)/cve2_counter.sv \
$(SRC_DIR)/cve2_csr.sv \
$(SRC_DIR)/cve2_cs_registers.sv \
$(SRC_DIR)/cve2_decoder.sv \
$(SRC_DIR)/cve2_ex_block.sv \
$(SRC_DIR)/cve2_fetch_fifo.sv \
$(SRC_DIR)/cve2_id_stage.sv \
$(SRC_DIR)/cve2_if_stage.sv \
$(SRC_DIR)/cve2_load_store_unit.sv \
$(SRC_DIR)/cve2_multdiv_fast.sv \
$(SRC_DIR)/cve2_multdiv_slow.sv \
$(SRC_DIR)/cve2_prefetch_buffer.sv \
$(SRC_DIR)/cve2_pmp.sv \
$(SRC_DIR)/cve2_register_file_ff.sv \
$(SRC_DIR)/cve2_wb_stage.sv \
$(SRC_DIR)/cve2_core.sv \
$(SRC_DIR)/cve2_top.sv
PKGS ?= \
$(SRC_DIR)/ibex_pkg.sv \
$(SRC_DIR)/cve2_pkg.sv \
$(LOWRISC_IP)/ip/prim/rtl/prim_ram_1p_pkg.sv
PRIM_CLOCK ?= $(SYN_DIR)/rtl/prim_clock_gating.v
@ -73,9 +73,9 @@ $(GEN_V): $(OUTDIR)%.v: $(SRC_DIR)%.sv $(PKGS) | $(OUTDIR)
# Disable "M" extension
$(IBEX_OUT): $(GEN_V) $(PRIM_CLOCK)
yosys -p "read_verilog $(PRIM_CLOCK) $(GEN_V)" \
-p "chparam -set RV32M 0 ibex_top" \
-p "chparam -set WritebackStage $(IBEX_ENABLE_WB) ibex_top" \
-p "synth -top ibex_top" \
-p "chparam -set RV32M 0 cve2_top" \
-p "chparam -set WritebackStage $(CVE2_ENABLE_WB) cve2_top" \
-p "synth -top cve2_top" \
-p "write_verilog $(IBEX_OUT)"
.PHONY: clean

26
lint/verilator_waiver.vlt
View file

@ -12,7 +12,7 @@
`verilator_config
lint_off -rule PINCONNECTEMPTY
// We have some boolean top-level parameters in e.g. ibex_core_tracing.sv.
// We have some boolean top-level parameters in e.g. cve2_core_tracing.sv.
// When building with fusesoc, these get set with defines like
// -GRV32M=1 (rather than -GRV32M=1'b1), leading to warnings like:
//
@ -23,13 +23,13 @@ lint_off -rule PINCONNECTEMPTY
// matches when you set a 1-bit value to a literal 1, so it won't hide
// silly mistakes like setting it to 2.
//
lint_off -rule WIDTH -file "*/rtl/ibex_top_tracing.sv"
lint_off -rule WIDTH -file "*/rtl/cve2_top_tracing.sv"
-match "*expects 1 bits*Initial value's CONST '32'h1'*"
// Operator expects 1 bit on initial value but initial value's CONST generates
// 32 bits, need a specific RV32B waiver as it uses enums so the above catch-all
// waiver doesn't work.
lint_off -rule WIDTH -file "*/rtl/ibex_top_tracing.sv" -match "*'RV32B'*"
lint_off -rule WIDTH -file "*/rtl/cve2_top_tracing.sv" -match "*'RV32B'*"
// Bits of signal are not used: be_i[3:1]
// Bits of signal are not used: addr_i[31:10,1:0]
@ -52,21 +52,21 @@ lint_off -rule UNUSED -file "*/rtl/timer.sv" -match "*'timer_addr_i'[31:10]*"
// Signal is not used: clk_i
// leaving clk and reset connected in-case we want to add assertions
lint_off -rule UNUSED -file "*/rtl/ibex_pmp.sv" -match "*clk_i*"
lint_off -rule UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -match "*clk_i*"
lint_off -rule UNUSED -file "*/rtl/ibex_decoder.sv" -match "*clk_i*"
lint_off -rule UNUSED -file "*/rtl/ibex_branch_predict.sv" -match "*clk_i*"
lint_off -rule UNUSED -file "*/rtl/cve2_pmp.sv" -match "*clk_i*"
lint_off -rule UNUSED -file "*/rtl/cve2_compressed_decoder.sv" -match "*clk_i*"
lint_off -rule UNUSED -file "*/rtl/cve2_decoder.sv" -match "*clk_i*"
lint_off -rule UNUSED -file "*/rtl/cve2_branch_predict.sv" -match "*clk_i*"
// Signal is not used: rst_ni
// leaving clk and reset connected in-case we want to add assertions
lint_off -rule UNUSED -file "*/rtl/ibex_pmp.sv" -match "*rst_ni*"
lint_off -rule UNUSED -file "*/rtl/ibex_compressed_decoder.sv" -match "*rst_ni*"
lint_off -rule UNUSED -file "*/rtl/ibex_decoder.sv" -match "*rst_ni*"
lint_off -rule UNUSED -file "*/rtl/ibex_branch_predict.sv" -match "*rst_ni*"
lint_off -rule UNUSED -file "*/rtl/cve2_pmp.sv" -match "*rst_ni*"
lint_off -rule UNUSED -file "*/rtl/cve2_compressed_decoder.sv" -match "*rst_ni*"
lint_off -rule UNUSED -file "*/rtl/cve2_decoder.sv" -match "*rst_ni*"
lint_off -rule UNUSED -file "*/rtl/cve2_branch_predict.sv" -match "*rst_ni*"
// Temporary waivers until OpenTitan primitives are lint-clean
// https://github.com/lowRISC/opentitan/issues/2313
lint_off -file "*/lowrisc_prim_*/rtl/*.sv"
lint_off -rule UNUSED -file "*/rtl/ibex_top_tracing.sv" -match "*RndCnstLfsrSeed*"
lint_off -rule UNUSED -file "*/rtl/ibex_top_tracing.sv" -match "*RndCnstLfsrPerm*"
lint_off -rule UNUSED -file "*/rtl/cve2_top_tracing.sv" -match "*RndCnstLfsrSeed*"
lint_off -rule UNUSED -file "*/rtl/cve2_top_tracing.sv" -match "*RndCnstLfsrPerm*"

8
rtl/ibex_alu.sv → rtl/cve2_alu.sv
View file

@ -6,10 +6,10 @@
/**
* Arithmetic logic unit
*/
module ibex_alu #(
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone
module cve2_alu #(
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone
) (
input ibex_pkg::alu_op_e operator_i,
input cve2_pkg::alu_op_e operator_i,
input logic [31:0] operand_a_i,
input logic [31:0] operand_b_i,
@ -31,7 +31,7 @@ module ibex_alu #(
output logic comparison_result_o,
output logic is_equal_result_o
);
import ibex_pkg::*;
import cve2_pkg::*;
logic [31:0] operand_a_rev;
logic [32:0] operand_b_neg;

4
rtl/ibex_branch_predict.sv → rtl/cve2_branch_predict.sv
View file

@ -17,7 +17,7 @@
`include "prim_assert.sv"
module ibex_branch_predict (
module cve2_branch_predict (
input logic clk_i,
input logic rst_ni,
@ -30,7 +30,7 @@ module ibex_branch_predict (
output logic predict_branch_taken_o,
output logic [31:0] predict_branch_pc_o
);
import ibex_pkg::*;
import cve2_pkg::*;
logic [31:0] imm_j_type;
logic [31:0] imm_b_type;

4
rtl/ibex_compressed_decoder.sv → rtl/cve2_compressed_decoder.sv
View file

@ -13,7 +13,7 @@
`include "prim_assert.sv"
module ibex_compressed_decoder (
module cve2_compressed_decoder (
input logic clk_i,
input logic rst_ni,
input logic valid_i,
@ -22,7 +22,7 @@ module ibex_compressed_decoder (
output logic is_compressed_o,
output logic illegal_instr_o
);
import ibex_pkg::*;
import cve2_pkg::*;
// valid_i indicates if instr_i is valid and is used for assertions only.
// The following signal is used to avoid possible lint errors.

24
rtl/ibex_controller.sv → rtl/cve2_controller.sv
View file

@ -10,7 +10,7 @@
`include "prim_assert.sv"
`include "dv_fcov_macros.svh"
module ibex_controller #(
module cve2_controller #(
parameter bit WritebackStage = 0,
parameter bit BranchPredictor = 0
) (
@ -47,12 +47,12 @@ module ibex_controller #(
// to prefetcher
output logic instr_req_o, // start fetching instructions
output logic pc_set_o, // jump to address set by pc_mux
output ibex_pkg::pc_sel_e pc_mux_o, // IF stage fetch address selector
output cve2_pkg::pc_sel_e pc_mux_o, // IF stage fetch address selector
// (boot, normal, exception...)
output logic nt_branch_mispredict_o, // Not-taken branch in ID/EX was
// mispredicted (predicted taken)
output ibex_pkg::exc_pc_sel_e exc_pc_mux_o, // IF stage selector for exception PC
output ibex_pkg::exc_cause_e exc_cause_o, // for IF stage, CSRs
output cve2_pkg::exc_pc_sel_e exc_pc_mux_o, // IF stage selector for exception PC
output cve2_pkg::exc_cause_e exc_cause_o, // for IF stage, CSRs
// LSU
input logic [31:0] lsu_addr_last_i, // for mtval
@ -70,14 +70,14 @@ module ibex_controller #(
// interrupt signals
input logic csr_mstatus_mie_i, // M-mode interrupt enable bit
input logic irq_pending_i, // interrupt request pending
input ibex_pkg::irqs_t irqs_i, // interrupt requests qualified with
input cve2_pkg::irqs_t irqs_i, // interrupt requests qualified with
// mie CSR
input logic irq_nm_i, // non-maskeable interrupt
output logic nmi_mode_o, // core executing NMI handler
// debug signals
input logic debug_req_i,
output ibex_pkg::dbg_cause_e debug_cause_o,
output cve2_pkg::dbg_cause_e debug_cause_o,
output logic debug_csr_save_o,
output logic debug_mode_o,
input logic debug_single_step_i,
@ -92,7 +92,7 @@ module ibex_controller #(
output logic csr_restore_dret_id_o,
output logic csr_save_cause_o,
output logic [31:0] csr_mtval_o,
input ibex_pkg::priv_lvl_e priv_mode_i,
input cve2_pkg::priv_lvl_e priv_mode_i,
input logic csr_mstatus_tw_i,
// stall & flush signals
@ -107,7 +107,7 @@ module ibex_controller #(
output logic perf_tbranch_o // we are executing a taken branch
// instruction
);
import ibex_pkg::*;
import cve2_pkg::*;
// FSM state encoding
typedef enum logic [3:0] {
@ -170,8 +170,8 @@ module ibex_controller #(
always_ff @(negedge clk_i) begin
// print warning in case of decoding errors
if ((ctrl_fsm_cs == DECODE) && instr_valid_i && !instr_fetch_err_i && illegal_insn_d) begin
$display("%t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, ibex_core.hart_id_i,
ibex_id_stage.pc_id_i, ibex_id_stage.instr_rdata_i);
$display("%t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, cve2_core.hart_id_i,
cve2_id_stage.pc_id_i, cve2_id_stage.instr_rdata_i);
end
end
// synopsys translate_on
@ -203,7 +203,7 @@ module ibex_controller #(
(mret_insn | (csr_mstatus_tw_i & wfi_insn));
// This is recorded in the illegal_insn_q flop to help timing. Specifically
// it is needed to break the path from ibex_cs_registers/illegal_csr_insn_o
// it is needed to break the path from cve2_cs_registers/illegal_csr_insn_o
// to pc_set_o. Clear when controller is in FLUSH so it won't remain set
// once illegal instruction is handled.
// All terms in this expression are qualified by instr_valid_i
@ -916,7 +916,7 @@ module ibex_controller #(
`ifdef RVFI
// Workaround for internal verilator error when using hierarchical refers to calcuate this
// directly in ibex_core
// directly in cve2_core
logic rvfi_flush_next;
assign rvfi_flush_next = ctrl_fsm_ns == FLUSH;

17
rtl/cve2_core.f Normal file
View file

@ -0,0 +1,17 @@
cve2_pkg.sv
cve2_alu.sv
cve2_compressed_decoder.sv
cve2_controller.sv
cve2_counter.sv
cve2_cs_registers.sv
cve2_decoder.sv
cve2_ex_block.sv
cve2_id_stage.sv
cve2_if_stage.sv
cve2_load_store_unit.sv
cve2_multdiv_slow.sv
cve2_multdiv_fast.sv
cve2_prefetch_buffer.sv
cve2_fetch_fifo.sv
cve2_register_file_ff.sv
cve2_core.sv

20
rtl/ibex_core.sv → rtl/cve2_core.sv
View file

@ -12,7 +12,7 @@
/**
* Top level module of the ibex RISC-V core
*/
module ibex_core import ibex_pkg::*; #(
module cve2_core import cve2_pkg::*; #(
parameter bit PMPEnable = 1'b0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
@ -362,7 +362,7 @@ module ibex_core import ibex_pkg::*; #(
// IF stage //
//////////////
ibex_if_stage #(
cve2_if_stage #(
.DmHaltAddr (DmHaltAddr),
.DmExceptionAddr (DmExceptionAddr),
.DummyInstructions(DummyInstructions),
@ -481,7 +481,7 @@ module ibex_core import ibex_pkg::*; #(
// ID stage //
//////////////
ibex_id_stage #(
cve2_id_stage #(
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B),
@ -640,7 +640,7 @@ module ibex_core import ibex_pkg::*; #(
// for RVFI only
assign unused_illegal_insn_id = illegal_insn_id;
ibex_ex_block #(
cve2_ex_block #(
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU(BranchTargetALU)
@ -692,7 +692,7 @@ module ibex_core import ibex_pkg::*; #(
assign data_req_o = data_req_out & ~pmp_req_err[PMP_D];
assign lsu_resp_err = lsu_load_err | lsu_store_err;
ibex_load_store_unit load_store_unit_i (
cve2_load_store_unit load_store_unit_i (
.clk_i (clk_i),
.rst_ni(rst_ni),
@ -738,7 +738,7 @@ module ibex_core import ibex_pkg::*; #(
.perf_store_o(perf_store)
);
ibex_wb_stage #(
cve2_wb_stage #(
.ResetAll ( ResetAll ),
.WritebackStage(WritebackStage)
) wb_stage_i (
@ -912,7 +912,7 @@ module ibex_core import ibex_pkg::*; #(
assign csr_wdata = alu_operand_a_ex;
assign csr_addr = csr_num_e'(csr_access ? alu_operand_b_ex[11:0] : 12'b0);
ibex_cs_registers #(
cve2_cs_registers #(
.DbgTriggerEn (DbgTriggerEn),
.DbgHwBreakNum (DbgHwBreakNum),
.DataIndTiming (DataIndTiming),
@ -1040,7 +1040,7 @@ module ibex_core import ibex_pkg::*; #(
assign pmp_req_type[PMP_D] = data_we_o ? PMP_ACC_WRITE : PMP_ACC_READ;
assign pmp_priv_lvl[PMP_D] = priv_mode_lsu;
ibex_pmp #(
cve2_pmp #(
.PMPGranularity(PMPGranularity),
.PMPNumChan (PMP_NUM_CHAN),
.PMPNumRegions (PMPNumRegions)
@ -1146,14 +1146,14 @@ module ibex_core import ibex_pkg::*; #(
logic new_debug_req;
logic new_nmi;
logic new_irq;
ibex_pkg::irqs_t captured_mip;
cve2_pkg::irqs_t captured_mip;
logic captured_nmi;
logic captured_debug_req;
logic captured_valid;
// RVFI extension for co-simulation support
// debug_req and MIP captured at IF -> ID transition so one extra stage
ibex_pkg::irqs_t rvfi_ext_stage_mip [RVFI_STAGES+1];
cve2_pkg::irqs_t rvfi_ext_stage_mip [RVFI_STAGES+1];
logic rvfi_ext_stage_nmi [RVFI_STAGES+1];
logic rvfi_ext_stage_debug_req [RVFI_STAGES+1];
logic [63:0] rvfi_ext_stage_mcycle [RVFI_STAGES];

2
rtl/ibex_counter.sv → rtl/cve2_counter.sv
View file

@ -1,4 +1,4 @@
module ibex_counter #(
module cve2_counter #(
parameter int CounterWidth = 32,
// When set `counter_val_upd_o` provides an incremented version of the counter value, otherwise
// the output is hard-wired to 0. This is required to allow Xilinx DSP inference to work

82
rtl/ibex_cs_registers.sv → rtl/cve2_cs_registers.sv
View file

@ -12,7 +12,7 @@
`include "prim_assert.sv"
module ibex_cs_registers #(
module cve2_cs_registers #(
parameter bit DbgTriggerEn = 0,
parameter int unsigned DbgHwBreakNum = 1,
parameter bit DataIndTiming = 1'b0,
@ -25,8 +25,8 @@ module ibex_cs_registers #(
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
parameter bit RV32E = 0,
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone
) (
// Clock and Reset
input logic clk_i,
@ -36,8 +36,8 @@ module ibex_cs_registers #(
input logic [31:0] hart_id_i,
// Privilege mode
output ibex_pkg::priv_lvl_e priv_mode_id_o,
output ibex_pkg::priv_lvl_e priv_mode_lsu_o,
output cve2_pkg::priv_lvl_e priv_mode_id_o,
output cve2_pkg::priv_lvl_e priv_mode_lsu_o,
output logic csr_mstatus_tw_o,
// mtvec
@ -47,9 +47,9 @@ module ibex_cs_registers #(
// Interface to registers (SRAM like)
input logic csr_access_i,
input ibex_pkg::csr_num_e csr_addr_i,
input cve2_pkg::csr_num_e csr_addr_i,
input logic [31:0] csr_wdata_i,
input ibex_pkg::csr_op_e csr_op_i,
input cve2_pkg::csr_op_e csr_op_i,
input csr_op_en_i,
output logic [31:0] csr_rdata_o,
@ -60,18 +60,18 @@ module ibex_cs_registers #(
input logic [14:0] irq_fast_i,
input logic nmi_mode_i,
output logic irq_pending_o, // interrupt request pending
output ibex_pkg::irqs_t irqs_o, // interrupt requests qualified with mie
output cve2_pkg::irqs_t irqs_o, // interrupt requests qualified with mie
output logic csr_mstatus_mie_o,
output logic [31:0] csr_mepc_o,
// PMP
output ibex_pkg::pmp_cfg_t csr_pmp_cfg_o [PMPNumRegions],
output cve2_pkg::pmp_cfg_t csr_pmp_cfg_o [PMPNumRegions],
output logic [33:0] csr_pmp_addr_o [PMPNumRegions],
output ibex_pkg::pmp_mseccfg_t csr_pmp_mseccfg_o,
output cve2_pkg::pmp_mseccfg_t csr_pmp_mseccfg_o,
// debug
input logic debug_mode_i,
input ibex_pkg::dbg_cause_e debug_cause_i,
input cve2_pkg::dbg_cause_e debug_cause_i,
input logic debug_csr_save_i,
output logic [31:0] csr_depc_o,
output logic debug_single_step_o,
@ -99,7 +99,7 @@ module ibex_cs_registers #(
input logic csr_restore_mret_i,
input logic csr_restore_dret_i,
input logic csr_save_cause_i,
input ibex_pkg::exc_cause_e csr_mcause_i,
input cve2_pkg::exc_cause_e csr_mcause_i,
input logic [31:0] csr_mtval_i,
output logic illegal_csr_insn_o, // access to non-existent CSR,
// with wrong priviledge level, or
@ -121,7 +121,7 @@ module ibex_cs_registers #(
input logic div_wait_i // core waiting for divide
);
import ibex_pkg::*;
import cve2_pkg::*;
localparam int unsigned RV32BEnabled = (RV32B == RV32BNone) ? 0 : 1;
localparam int unsigned RV32MEnabled = (RV32M == RV32MNone) ? 0 : 1;
@ -801,7 +801,7 @@ module ibex_cs_registers #(
mpp: PRIV_LVL_U,
mprv: 1'b0,
tw: 1'b0};
ibex_csr #(
cve2_csr #(
.Width ($bits(status_t)),
.ShadowCopy(ShadowCSR),
.ResetValue({MSTATUS_RST_VAL})
@ -815,7 +815,7 @@ module ibex_cs_registers #(
);
// MEPC
ibex_csr #(
cve2_csr #(
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
@ -833,7 +833,7 @@ module ibex_cs_registers #(
assign mie_d.irq_timer = csr_wdata_int[CSR_MTIX_BIT];
assign mie_d.irq_external = csr_wdata_int[CSR_MEIX_BIT];
assign mie_d.irq_fast = csr_wdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW];
ibex_csr #(
cve2_csr #(
.Width ($bits(irqs_t)),
.ShadowCopy(1'b0),
.ResetValue('0)
@ -847,7 +847,7 @@ module ibex_cs_registers #(
);
// MSCRATCH
ibex_csr #(
cve2_csr #(
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
@ -861,7 +861,7 @@ module ibex_cs_registers #(
);
// MCAUSE
ibex_csr #(
cve2_csr #(
.Width (6),
.ShadowCopy(1'b0),
.ResetValue('0)
@ -875,7 +875,7 @@ module ibex_cs_registers #(
);
// MTVAL
ibex_csr #(
cve2_csr #(
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
@ -889,7 +889,7 @@ module ibex_cs_registers #(
);
// MTVEC
ibex_csr #(
cve2_csr #(
.Width (32),
.ShadowCopy(ShadowCSR),
.ResetValue(32'd1)
@ -909,7 +909,7 @@ module ibex_cs_registers #(
prv: PRIV_LVL_M,
default: '0
};
ibex_csr #(
cve2_csr #(
.Width ($bits(dcsr_t)),
.ShadowCopy(1'b0),
.ResetValue({DCSR_RESET_VAL})
@ -923,7 +923,7 @@ module ibex_cs_registers #(
);
// DEPC
ibex_csr #(
cve2_csr #(
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
@ -937,7 +937,7 @@ module ibex_cs_registers #(
);
// DSCRATCH0
ibex_csr #(
cve2_csr #(
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
@ -951,7 +951,7 @@ module ibex_cs_registers #(
);
// DSCRATCH1
ibex_csr #(
cve2_csr #(
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
@ -966,7 +966,7 @@ module ibex_cs_registers #(
// MSTACK
localparam status_stk_t MSTACK_RESET_VAL = '{mpie: 1'b1, mpp: PRIV_LVL_U};
ibex_csr #(
cve2_csr #(
.Width ($bits(status_stk_t)),
.ShadowCopy(1'b0),
.ResetValue({MSTACK_RESET_VAL})
@ -980,7 +980,7 @@ module ibex_cs_registers #(
);
// MSTACK_EPC
ibex_csr #(
cve2_csr #(
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
@ -994,7 +994,7 @@ module ibex_cs_registers #(
);
// MSTACK_CAUSE
ibex_csr #(
cve2_csr #(
.Width (6),
.ShadowCopy(1'b0),
.ResetValue('0)
@ -1013,10 +1013,10 @@ module ibex_cs_registers #(
if (PMPEnable) begin : g_pmp_registers
// PMP reset values
`ifdef IBEX_CUSTOM_PMP_RESET_VALUES
`include "ibex_pmp_reset.svh"
`ifdef CVE2_CUSTOM_PMP_RESET_VALUES
`include "cve2_pmp_reset.svh"
`else
`include "ibex_pmp_reset_default.svh"
`include "cve2_pmp_reset_default.svh"
`endif
pmp_mseccfg_t pmp_mseccfg_q, pmp_mseccfg_d;
@ -1102,7 +1102,7 @@ module ibex_cs_registers #(
&csr_wdata_int[(i%4)*PMP_CFG_W+:2];
assign pmp_cfg_wdata[i].read = csr_wdata_int[(i%4)*PMP_CFG_W];
ibex_csr #(
cve2_csr #(
.Width ($bits(pmp_cfg_t)),
.ShadowCopy(ShadowCSR),
.ResetValue(pmp_cfg_rst[i])
@ -1131,7 +1131,7 @@ module ibex_cs_registers #(
(csr_addr == (CSR_OFF_PMP_ADDR + i[11:0]));
end
ibex_csr #(
cve2_csr #(
.Width (PMPAddrWidth),
.ShadowCopy(ShadowCSR),
.ResetValue(pmp_addr_rst[i][33-:PMPAddrWidth])
@ -1164,7 +1164,7 @@ module ibex_cs_registers #(
// MSECCFG.RLB cannot be set again
assign pmp_mseccfg_d.rlb = any_pmp_entry_locked ? 1'b0 : csr_wdata_int[CSR_MSECCFG_RLB_BIT];
ibex_csr #(
cve2_csr #(
.Width ($bits(pmp_mseccfg_t)),
.ShadowCopy(ShadowCSR),
.ResetValue(pmp_mseccfg_rst)
@ -1219,7 +1219,7 @@ module ibex_cs_registers #(
end
// When adding or altering performance counter meanings and default
// mappings please update dv/verilator/pcount/cpp/ibex_pcounts.cc
// mappings please update dv/verilator/pcount/cpp/cve2_pcounts.cc
// appropriately.
//
// active counters
@ -1255,7 +1255,7 @@ module ibex_cs_registers #(
end
// mcycle
ibex_counter #(
cve2_counter #(
.CounterWidth(64)
) mcycle_counter_i (
.clk_i(clk_i),
@ -1270,7 +1270,7 @@ module ibex_cs_registers #(
// minstret
ibex_counter #(
cve2_counter #(
.CounterWidth(64),
.ProvideValUpd(1)
) minstret_counter_i (
@ -1306,7 +1306,7 @@ module ibex_cs_registers #(
if (i < MHPMCounterNum) begin : gen_imp
logic [63:0] mhpmcounter_raw, mhpmcounter_next;
ibex_counter #(
cve2_counter #(
.CounterWidth(MHPMCounterWidth),
.ProvideValUpd(Cnt == 10)
) mcounters_variable_i (
@ -1407,7 +1407,7 @@ module ibex_cs_registers #(
assign tmatch_value_d = csr_wdata_int[31:0];
// Registers
ibex_csr #(
cve2_csr #(
.Width (DbgHwNumLen),
.ShadowCopy(1'b0),
.ResetValue('0)
@ -1421,7 +1421,7 @@ module ibex_cs_registers #(
);
for (genvar i = 0; i < DbgHwBreakNum; i++) begin : g_dbg_tmatch_reg
ibex_csr #(
cve2_csr #(
.Width (1),
.ShadowCopy(1'b0),
.ResetValue('0)
@ -1434,7 +1434,7 @@ module ibex_cs_registers #(
.rd_error_o()
);
ibex_csr #(
cve2_csr #(
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
@ -1564,7 +1564,7 @@ module ibex_cs_registers #(
assign icache_enable_o = cpuctrl_q.icache_enable;
ibex_csr #(
cve2_csr #(
.Width ($bits(cpu_ctrl_t)),
.ShadowCopy(ShadowCSR),
.ResetValue('0)

2
rtl/ibex_csr.sv → rtl/cve2_csr.sv
View file

@ -8,7 +8,7 @@
`include "prim_assert.sv"
module ibex_csr #(
module cve2_csr #(
parameter int unsigned Width = 32,
parameter bit ShadowCopy = 1'b0,
parameter bit [Width-1:0] ResetValue = '0

28
rtl/ibex_decoder.sv → rtl/cve2_decoder.sv
View file

@ -13,10 +13,10 @@
`include "prim_assert.sv"
module ibex_decoder #(
module cve2_decoder #(
parameter bit RV32E = 0,
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone,
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone,
parameter bit BranchTargetALU = 0
) (
input logic clk_i,
@ -43,10 +43,10 @@ module ibex_decoder #(
input logic illegal_c_insn_i, // compressed instruction decode failed
// immediates
output ibex_pkg::imm_a_sel_e imm_a_mux_sel_o, // immediate selection for operand a
output ibex_pkg::imm_b_sel_e imm_b_mux_sel_o, // immediate selection for operand b
output ibex_pkg::op_a_sel_e bt_a_mux_sel_o, // branch target selection operand a
output ibex_pkg::imm_b_sel_e bt_b_mux_sel_o, // branch target selection operand b
output cve2_pkg::imm_a_sel_e imm_a_mux_sel_o, // immediate selection for operand a
output cve2_pkg::imm_b_sel_e imm_b_mux_sel_o, // immediate selection for operand b
output cve2_pkg::op_a_sel_e bt_a_mux_sel_o, // branch target selection operand a
output cve2_pkg::imm_b_sel_e bt_b_mux_sel_o, // branch target selection operand b
output logic [31:0] imm_i_type_o,
output logic [31:0] imm_s_type_o,
output logic [31:0] imm_b_type_o,
@ -55,7 +55,7 @@ module ibex_decoder #(
output logic [31:0] zimm_rs1_type_o,
// register file
output ibex_pkg::rf_wd_sel_e rf_wdata_sel_o, // RF write data selection
output cve2_pkg::rf_wd_sel_e rf_wdata_sel_o, // RF write data selection
output logic rf_we_o, // write enable for regfile
output logic [4:0] rf_raddr_a_o,
output logic [4:0] rf_raddr_b_o,
@ -64,10 +64,10 @@ module ibex_decoder #(
output logic rf_ren_b_o, // Instruction reads from RF addr B
// ALU
output ibex_pkg::alu_op_e alu_operator_o, // ALU operation selection
output ibex_pkg::op_a_sel_e alu_op_a_mux_sel_o, // operand a selection: reg value, PC,
output cve2_pkg::alu_op_e alu_operator_o, // ALU operation selection
output cve2_pkg::op_a_sel_e alu_op_a_mux_sel_o, // operand a selection: reg value, PC,
// immediate or zero
output ibex_pkg::op_b_sel_e alu_op_b_mux_sel_o, // operand b selection: reg value or
output cve2_pkg::op_b_sel_e alu_op_b_mux_sel_o, // operand b selection: reg value or
// immediate
output logic alu_multicycle_o, // ternary bitmanip instruction
@ -77,12 +77,12 @@ module ibex_decoder #(
output logic mult_sel_o, // as above but static, for data muxes
output logic div_sel_o, // as above but static, for data muxes
output ibex_pkg::md_op_e multdiv_operator_o,
output cve2_pkg::md_op_e multdiv_operator_o,
output logic [1:0] multdiv_signed_mode_o,
// CSRs
output logic csr_access_o, // access to CSR
output ibex_pkg::csr_op_e csr_op_o, // operation to perform on CSR
output cve2_pkg::csr_op_e csr_op_o, // operation to perform on CSR
// LSU
output logic data_req_o, // start transaction to data memory
@ -97,7 +97,7 @@ module ibex_decoder #(
output logic branch_in_dec_o
);
import ibex_pkg::*;
import cve2_pkg::*;
logic illegal_insn;
logic illegal_reg_rv32e;

2
rtl/ibex_dummy_instr.sv → rtl/cve2_dummy_instr.sv
View file

@ -9,7 +9,7 @@
*/
// SEC_CM: CTRL_FLOW.UNPREDICTABLE
module ibex_dummy_instr import ibex_pkg::*; #(
module cve2_dummy_instr import cve2_pkg::*; #(
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault
) (

18
rtl/ibex_ex_block.sv → rtl/cve2_ex_block.sv
View file

@ -8,16 +8,16 @@
*
* Execution block: Hosts ALU and MUL/DIV unit
*/
module ibex_ex_block #(
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone,
module cve2_ex_block #(
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone,
parameter bit BranchTargetALU = 0
) (
input logic clk_i,
input logic rst_ni,
// ALU
input ibex_pkg::alu_op_e alu_operator_i,
input cve2_pkg::alu_op_e alu_operator_i,
input logic [31:0] alu_operand_a_i,
input logic [31:0] alu_operand_b_i,
input logic alu_instr_first_cycle_i,
@ -28,7 +28,7 @@ module ibex_ex_block #(
input logic [31:0] bt_b_operand_i,
// Multiplier/Divider
input ibex_pkg::md_op_e multdiv_operator_i,
input cve2_pkg::md_op_e multdiv_operator_i,
input logic mult_en_i, // dynamic enable signal, for FSM control
input logic div_en_i, // dynamic enable signal, for FSM control
input logic mult_sel_i, // static decoder output, for data muxes
@ -53,7 +53,7 @@ module ibex_ex_block #(
output logic ex_valid_o // EX has valid output
);
import ibex_pkg::*;
import cve2_pkg::*;
logic [31:0] alu_result, multdiv_result;
@ -113,7 +113,7 @@ module ibex_ex_block #(
// ALU //
/////////
ibex_alu #(
cve2_alu #(
.RV32B(RV32B)
) alu_i (
.operator_i (alu_operator_i),
@ -138,7 +138,7 @@ module ibex_ex_block #(
////////////////
if (RV32M == RV32MSlow) begin : gen_multdiv_slow
ibex_multdiv_slow multdiv_i (
cve2_multdiv_slow multdiv_i (
.clk_i (clk_i),
.rst_ni (rst_ni),
.mult_en_i (mult_en_i),
@ -163,7 +163,7 @@ module ibex_ex_block #(
.multdiv_result_o (multdiv_result)
);
end else if (RV32M == RV32MFast || RV32M == RV32MSingleCycle) begin : gen_multdiv_fast
ibex_multdiv_fast #(
cve2_multdiv_fast #(
.RV32M(RV32M)
) multdiv_i (
.clk_i (clk_i),

2
rtl/ibex_fetch_fifo.sv → rtl/cve2_fetch_fifo.sv
View file

@ -12,7 +12,7 @@
`include "prim_assert.sv"
module ibex_fetch_fifo #(
module cve2_fetch_fifo #(
parameter int unsigned NUM_REQS = 2,
parameter bit ResetAll = 1'b0
) (

2
rtl/ibex_icache.sv → rtl/cve2_icache.sv
View file

@ -10,7 +10,7 @@
`include "prim_assert.sv"
module ibex_icache import ibex_pkg::*; #(
module cve2_icache import cve2_pkg::*; #(
parameter bit ICacheECC = 1'b0,
parameter bit ResetAll = 1'b0,
parameter int unsigned BusSizeECC = BUS_SIZE,

32
rtl/ibex_id_stage.sv → rtl/cve2_id_stage.sv
View file

@ -17,10 +17,10 @@
`include "prim_assert.sv"
`include "dv_fcov_macros.svh"
module ibex_id_stage #(
module cve2_id_stage #(
parameter bit RV32E = 0,
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone,
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone,
parameter bit DataIndTiming = 1'b0,
parameter bit BranchTargetALU = 0,
parameter bit WritebackStage = 0,
@ -50,11 +50,11 @@ module ibex_id_stage #(
// IF and ID stage signals
output logic pc_set_o,
output ibex_pkg::pc_sel_e pc_mux_o,
output cve2_pkg::pc_sel_e pc_mux_o,
output logic nt_branch_mispredict_o,
output logic [31:0] nt_branch_addr_o,
output ibex_pkg::exc_pc_sel_e exc_pc_mux_o,
output ibex_pkg::exc_cause_e exc_cause_o,
output cve2_pkg::exc_pc_sel_e exc_pc_mux_o,
output cve2_pkg::exc_cause_e exc_cause_o,
input logic illegal_c_insn_i,
input logic instr_fetch_err_i,
@ -66,7 +66,7 @@ module ibex_id_stage #(
input logic ex_valid_i, // EX stage has valid output
input logic lsu_resp_valid_i, // LSU has valid output, or is done
// ALU
output ibex_pkg::alu_op_e alu_operator_ex_o,
output cve2_pkg::alu_op_e alu_operator_ex_o,
output logic [31:0] alu_operand_a_ex_o,
output logic [31:0] alu_operand_b_ex_o,
@ -84,7 +84,7 @@ module ibex_id_stage #(
output logic div_en_ex_o,
output logic mult_sel_ex_o,
output logic div_sel_ex_o,
output ibex_pkg::md_op_e multdiv_operator_ex_o,
output cve2_pkg::md_op_e multdiv_operator_ex_o,
output logic [1:0] multdiv_signed_mode_ex_o,
output logic [31:0] multdiv_operand_a_ex_o,
output logic [31:0] multdiv_operand_b_ex_o,
@ -92,7 +92,7 @@ module ibex_id_stage #(
// CSR
output logic csr_access_o,
output ibex_pkg::csr_op_e csr_op_o,
output cve2_pkg::csr_op_e csr_op_o,
output logic csr_op_en_o,
output logic csr_save_if_o,
output logic csr_save_id_o,
@ -101,7 +101,7 @@ module ibex_id_stage #(
output logic csr_restore_dret_id_o,
output logic csr_save_cause_o,
output logic [31:0] csr_mtval_o,
input ibex_pkg::priv_lvl_e priv_mode_i,
input cve2_pkg::priv_lvl_e priv_mode_i,
input logic csr_mstatus_tw_i,
input logic illegal_csr_insn_i,
input logic data_ind_timing_i,
@ -124,7 +124,7 @@ module ibex_id_stage #(
// Interrupt signals
input logic csr_mstatus_mie_i,
input logic irq_pending_i,
input ibex_pkg::irqs_t irqs_i,
input cve2_pkg::irqs_t irqs_i,
input logic irq_nm_i,
output logic nmi_mode_o,
@ -133,7 +133,7 @@ module ibex_id_stage #(
// Debug Signal
output logic debug_mode_o,
output ibex_pkg::dbg_cause_e debug_cause_o,
output cve2_pkg::dbg_cause_e debug_cause_o,
output logic debug_csr_save_o,
input logic debug_req_i,
input logic debug_single_step_i,
@ -166,7 +166,7 @@ module ibex_id_stage #(
input logic rf_write_wb_i,
output logic en_wb_o,
output ibex_pkg::wb_instr_type_e instr_type_wb_o,
output cve2_pkg::wb_instr_type_e instr_type_wb_o,
output logic instr_perf_count_id_o,
input logic ready_wb_i,
input logic outstanding_load_wb_i,
@ -183,7 +183,7 @@ module ibex_id_stage #(
output logic instr_id_done_o
);
import ibex_pkg::*;
import cve2_pkg::*;
// Decoder/Controller, ID stage internal signals
logic illegal_insn_dec;
@ -419,7 +419,7 @@ module ibex_id_stage #(
// Decoder //
/////////////
ibex_decoder #(
cve2_decoder #(
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B),
@ -529,7 +529,7 @@ module ibex_id_stage #(
assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i);
ibex_controller #(
cve2_controller #(
.WritebackStage (WritebackStage),
.BranchPredictor(BranchPredictor)
) controller_i (

14
rtl/ibex_if_stage.sv → rtl/cve2_if_stage.sv
View file

@ -12,7 +12,7 @@
`include "prim_assert.sv"
module ibex_if_stage import ibex_pkg::*; #(
module cve2_if_stage import cve2_pkg::*; #(
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808,
parameter bit DummyInstructions = 1'b0,
@ -159,7 +159,7 @@ module ibex_if_stage import ibex_pkg::*; #(
logic predict_branch_taken;
logic [31:0] predict_branch_pc;
ibex_pkg::pc_sel_e pc_mux_internal;
cve2_pkg::pc_sel_e pc_mux_internal;
logic [7:0] unused_boot_addr;
logic [7:0] unused_csr_mtvec;
@ -207,7 +207,7 @@ module ibex_if_stage import ibex_pkg::*; #(
if (ICache) begin : gen_icache
// Full I-Cache option
ibex_icache #(
cve2_icache #(
.ICacheECC (ICacheECC),
.ResetAll (ResetAll),
.BusSizeECC (BusSizeECC),
@ -257,7 +257,7 @@ module ibex_if_stage import ibex_pkg::*; #(
);
end else begin : gen_prefetch_buffer
// prefetch buffer, caches a fixed number of instructions
ibex_prefetch_buffer #(
cve2_prefetch_buffer #(
.ResetAll (ResetAll)
) prefetch_buffer_i (
.clk_i ( clk_i ),
@ -347,7 +347,7 @@ module ibex_if_stage import ibex_pkg::*; #(
//
// since it does not matter where we decompress instructions, we do it here
// to ease timing closure
ibex_compressed_decoder compressed_decoder_i (
cve2_compressed_decoder compressed_decoder_i (
.clk_i (clk_i),
.rst_ni (rst_ni),
.valid_i (fetch_valid & ~fetch_err),
@ -363,7 +363,7 @@ module ibex_if_stage import ibex_pkg::*; #(
logic insert_dummy_instr;
logic [31:0] dummy_instr_data;
ibex_dummy_instr #(
cve2_dummy_instr #(
.RndCnstLfsrSeed (RndCnstLfsrSeed),
.RndCnstLfsrPerm (RndCnstLfsrPerm)
) dummy_instr_i (
@ -584,7 +584,7 @@ module ibex_if_stage import ibex_pkg::*; #(
end
end
ibex_branch_predict branch_predict_i (
cve2_branch_predict branch_predict_i (
.clk_i (clk_i),
.rst_ni (rst_ni),
.fetch_rdata_i(fetch_rdata),

2
rtl/ibex_load_store_unit.sv → rtl/cve2_load_store_unit.sv
View file

@ -14,7 +14,7 @@
`include "prim_assert.sv"
`include "dv_fcov_macros.svh"
module ibex_load_store_unit
module cve2_load_store_unit
(
input logic clk_i,
input logic rst_ni,

4
rtl/ibex_lockstep.sv → rtl/cve2_lockstep.sv
View file

@ -8,7 +8,7 @@
// LockstepOffset cycles.
// SEC_CM: LOGIC.SHADOW
module ibex_lockstep import ibex_pkg::*; #(
module cve2_lockstep import cve2_pkg::*; #(
parameter int unsigned LockstepOffset = 2,
parameter bit PMPEnable = 1'b0,
parameter int unsigned PMPGranularity = 0,
@ -351,7 +351,7 @@ module ibex_lockstep import ibex_pkg::*; #(
logic shadow_alert_minor, shadow_alert_major;
ibex_core #(
cve2_core #(
.PMPEnable ( PMPEnable ),
.PMPGranularity ( PMPGranularity ),
.PMPNumRegions ( PMPNumRegions ),

10
rtl/ibex_multdiv_fast.sv → rtl/cve2_multdiv_fast.sv
View file

@ -14,8 +14,8 @@
`include "prim_assert.sv"
module ibex_multdiv_fast #(
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast
module cve2_multdiv_fast #(
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast
) (
input logic clk_i,
input logic rst_ni,
@ -23,7 +23,7 @@ module ibex_multdiv_fast #(
input logic div_en_i, // dynamic enable signal, for FSM control
input logic mult_sel_i, // static decoder output, for data muxes
input logic div_sel_i, // static decoder output, for data muxes
input ibex_pkg::md_op_e operator_i,
input cve2_pkg::md_op_e operator_i,
input logic [1:0] signed_mode_i,
input logic [31:0] op_a_i,
input logic [31:0] op_b_i,
@ -45,7 +45,7 @@ module ibex_multdiv_fast #(
output logic valid_o
);
import ibex_pkg::*;
import cve2_pkg::*;
// Both multiplier variants
logic signed [34:0] mac_res_signed;
@ -530,4 +530,4 @@ module ibex_multdiv_fast #(
`endif
`endif
endmodule // ibex_mult
endmodule // cve2_mult

6
rtl/ibex_multdiv_slow.sv → rtl/cve2_multdiv_slow.sv
View file

@ -11,7 +11,7 @@
`include "prim_assert.sv"
module ibex_multdiv_slow
module cve2_multdiv_slow
(
input logic clk_i,
input logic rst_ni,
@ -19,7 +19,7 @@ module ibex_multdiv_slow
input logic div_en_i, // dynamic enable signal, for FSM control
input logic mult_sel_i, // static decoder output, for data muxes
input logic div_sel_i, // static decoder output, for data muxes
input ibex_pkg::md_op_e operator_i,
input cve2_pkg::md_op_e operator_i,
input logic [1:0] signed_mode_i,
input logic [31:0] op_a_i,
input logic [31:0] op_b_i,
@ -42,7 +42,7 @@ module ibex_multdiv_slow
output logic valid_o
);
import ibex_pkg::*;
import cve2_pkg::*;
typedef enum logic [2:0] {
MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH

4
rtl/ibex_pkg.sv → rtl/cve2_pkg.sv
View file

@ -6,7 +6,7 @@
/**
* Package with constants used by Ibex
*/
package ibex_pkg;
package cve2_pkg;
////////////////
// IO Structs //
@ -614,7 +614,7 @@ package ibex_pkg;
// Note that if adjusting these parameters it is assumed the bottom bit is set for On and unset
// for Off. This allows the use of FetchEnableOn/FetchEnableOff to work for both secure and
// non-secure Ibex. If this assumption is broken the RTL that uses the fetch_enable signal within
// `ibex_core` may need adjusting.
// `cve2_core` may need adjusting.
parameter fetch_enable_t FetchEnableOn = 4'b1001;
parameter fetch_enable_t FetchEnableOff = 4'b0110;
endpackage

14
rtl/ibex_pmp.sv → rtl/cve2_pmp.sv
View file

@ -2,7 +2,7 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
module ibex_pmp #(
module cve2_pmp #(
// Granularity of NAPOT access,
// 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.
parameter int unsigned PMPGranularity = 0,
@ -16,19 +16,19 @@ module ibex_pmp #(
input logic rst_ni,
// Interface to CSRs
input ibex_pkg::pmp_cfg_t csr_pmp_cfg_i [PMPNumRegions],
input cve2_pkg::pmp_cfg_t csr_pmp_cfg_i [PMPNumRegions],
input logic [33:0] csr_pmp_addr_i [PMPNumRegions],
input ibex_pkg::pmp_mseccfg_t csr_pmp_mseccfg_i,
input cve2_pkg::pmp_mseccfg_t csr_pmp_mseccfg_i,
input ibex_pkg::priv_lvl_e priv_mode_i [PMPNumChan],
input cve2_pkg::priv_lvl_e priv_mode_i [PMPNumChan],
// Access checking channels
input logic [33:0] pmp_req_addr_i [PMPNumChan],
input ibex_pkg::pmp_req_e pmp_req_type_i [PMPNumChan],
input cve2_pkg::pmp_req_e pmp_req_type_i [PMPNumChan],
output logic pmp_req_err_o [PMPNumChan]
);
import ibex_pkg::*;
import cve2_pkg::*;
// Access Checking Signals
logic [33:0] region_start_addr [PMPNumRegions];
@ -177,7 +177,7 @@ module ibex_pmp #(
assign pmp_req_err_o[c] = access_fault[c];
end
// RLB, rule locking bypass, is only relevant to ibex_cs_registers which controls writes to the
// RLB, rule locking bypass, is only relevant to cve2_cs_registers which controls writes to the
// PMP CSRs. Tie to unused signal here to prevent lint warnings.
logic unused_csr_pmp_mseccfg_rlb;
assign unused_csr_pmp_mseccfg_rlb = csr_pmp_mseccfg_i.rlb;

0
rtl/ibex_pmp_reset_default.svh → rtl/cve2_pmp_reset_default.svh
View file

4
rtl/ibex_prefetch_buffer.sv → rtl/cve2_prefetch_buffer.sv
View file

@ -9,7 +9,7 @@
* Prefetch Buffer that caches instructions. This cuts overly long critical
* paths to the instruction cache.
*/
module ibex_prefetch_buffer #(
module cve2_prefetch_buffer #(
parameter bit ResetAll = 1'b0
) (
input logic clk_i,
@ -94,7 +94,7 @@ module ibex_prefetch_buffer #(
// Overlay the fifo fill state with the outstanding requests to see if there is space.
assign fifo_ready = ~&(fifo_busy | rdata_outstanding_rev);
ibex_fetch_fifo #(
cve2_fetch_fifo #(
.NUM_REQS (NUM_REQS),
.ResetAll (ResetAll)
) fifo_i (

2
rtl/ibex_register_file_ff.sv → rtl/cve2_register_file_ff.sv
View file

@ -10,7 +10,7 @@
* This register file is based on flip flops. Use this register file when
* targeting FPGA synthesis or Verilator simulation.
*/
module ibex_register_file_ff #(
module cve2_register_file_ff #(
parameter bit RV32E = 0,
parameter int unsigned DataWidth = 32,
parameter bit DummyInstructions = 0,

2
rtl/ibex_register_file_fpga.sv → rtl/cve2_register_file_fpga.sv
View file

@ -11,7 +11,7 @@
* This register file is designed to make FPGA synthesis tools infer RAM primitives. For Xilinx
* FPGA architectures, it will produce RAM32M primitives. Other vendors have not yet been tested.
*/
module ibex_register_file_fpga #(
module cve2_register_file_fpga #(
parameter bit RV32E = 0,
parameter int unsigned DataWidth = 32,
parameter bit DummyInstructions = 0,

2
rtl/ibex_register_file_latch.sv → rtl/cve2_register_file_latch.sv
View file

@ -11,7 +11,7 @@
* based RF. It requires a target technology-specific clock gating cell. Use this
* register file when targeting ASIC synthesis or event-based simulators.
*/
module ibex_register_file_latch #(
module cve2_register_file_latch #(
parameter bit RV32E = 0,
parameter int unsigned DataWidth = 32,
parameter bit DummyInstructions = 0,

16
rtl/ibex_top.sv → rtl/cve2_top.sv
View file

@ -12,7 +12,7 @@
/**
* Top level module of the ibex RISC-V core
*/
module ibex_top import ibex_pkg::*; #(
module cve2_top import cve2_pkg::*; #(
parameter bit PMPEnable = 1'b0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
@ -226,7 +226,7 @@ module ibex_top import ibex_pkg::*; #(
.out_o(rf_rdata_b_ecc_buf)
);
ibex_core #(
cve2_core #(
.PMPEnable (PMPEnable),
.PMPGranularity (PMPGranularity),
.PMPNumRegions (PMPNumRegions),
@ -254,7 +254,7 @@ module ibex_top import ibex_pkg::*; #(
.RegFileDataWidth (RegFileDataWidth),
.DmHaltAddr (DmHaltAddr),
.DmExceptionAddr (DmExceptionAddr)
) u_ibex_core (
) u_cve2_core (
.clk_i(clk),
.rst_ni,
@ -352,7 +352,7 @@ module ibex_top import ibex_pkg::*; #(
/////////////////////////////////
if (RegFile == RegFileFF) begin : gen_regfile_ff
ibex_register_file_ff #(
cve2_register_file_ff #(
.RV32E (RV32E),
.DataWidth (RegFileDataWidth),
.DummyInstructions(DummyInstructions),
@ -373,7 +373,7 @@ module ibex_top import ibex_pkg::*; #(
.we_a_i (rf_we_wb)
);
end else if (RegFile == RegFileFPGA) begin : gen_regfile_fpga
ibex_register_file_fpga #(
cve2_register_file_fpga #(
.RV32E (RV32E),
.DataWidth (RegFileDataWidth),
.DummyInstructions(DummyInstructions),
@ -394,7 +394,7 @@ module ibex_top import ibex_pkg::*; #(
.we_a_i (rf_we_wb)
);
end else if (RegFile == RegFileLatch) begin : gen_regfile_latch
ibex_register_file_latch #(
cve2_register_file_latch #(
.RV32E (RV32E),
.DataWidth (RegFileDataWidth),
.DummyInstructions(DummyInstructions),
@ -806,7 +806,7 @@ module ibex_top import ibex_pkg::*; #(
logic lockstep_alert_minor_local, lockstep_alert_major_internal_local;
logic lockstep_alert_major_bus_local;
ibex_lockstep #(
cve2_lockstep #(
.PMPEnable (PMPEnable),
.PMPGranularity (PMPGranularity),
.PMPNumRegions (PMPNumRegions),
@ -834,7 +834,7 @@ module ibex_top import ibex_pkg::*; #(
.RegFileDataWidth (RegFileDataWidth),
.DmHaltAddr (DmHaltAddr),
.DmExceptionAddr (DmExceptionAddr)
) u_ibex_lockstep (
) u_cve2_lockstep (
.clk_i (clk),
.rst_ni (rst_ni),

12
rtl/ibex_top_tracing.sv → rtl/cve2_top_tracing.sv
View file

@ -6,7 +6,7 @@
* Top level module of the ibex RISC-V core with tracing enabled
*/
module ibex_top_tracing import ibex_pkg::*; #(
module cve2_top_tracing import cve2_pkg::*; #(
parameter bit PMPEnable = 1'b0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
@ -91,7 +91,7 @@ module ibex_top_tracing import ibex_pkg::*; #(
);
// ibex_tracer relies on the signals from the RISC-V Formal Interface
// cve2_tracer relies on the signals from the RISC-V Formal Interface
`ifndef RVFI
$fatal("Fatal error: RVFI needs to be defined globally.");
`endif
@ -136,7 +136,7 @@ module ibex_top_tracing import ibex_pkg::*; #(
assign unused_rvfi_ext_debug_req = rvfi_ext_debug_req;
assign unused_rvfi_ext_mcycle = rvfi_ext_mcycle;
ibex_top #(
cve2_top #(
.PMPEnable ( PMPEnable ),
.PMPGranularity ( PMPGranularity ),
.PMPNumRegions ( PMPNumRegions ),
@ -159,7 +159,7 @@ module ibex_top_tracing import ibex_pkg::*; #(
.RndCnstLfsrPerm ( RndCnstLfsrPerm ),
.DmHaltAddr ( DmHaltAddr ),
.DmExceptionAddr ( DmExceptionAddr )
) u_ibex_top (
) u_cve2_top (
.clk_i,
.rst_ni,
@ -240,8 +240,8 @@ module ibex_top_tracing import ibex_pkg::*; #(
.core_sleep_o
);
ibex_tracer
u_ibex_tracer (
cve2_tracer
u_cve2_tracer (
.clk_i,
.rst_ni,

14
rtl/ibex_tracer.sv → rtl/cve2_tracer.sv
View file

@ -12,12 +12,12 @@
* All traced instructions are written to a log file. By default, the log file is named
* trace_core_<HARTID>.log, with <HARTID> being the 8 digit hart ID of the core being traced.
*
* The file name base, defaulting to "trace_core" can be set using the "ibex_tracer_file_base"
* plusarg passed to the simulation, e.g. "+ibex_tracer_file_base=ibex_my_trace". The exact syntax
* The file name base, defaulting to "trace_core" can be set using the "cve2_tracer_file_base"
* plusarg passed to the simulation, e.g. "+cve2_tracer_file_base=cve2_my_trace". The exact syntax
* of passing plusargs to a simulation depends on the simulator.
*
* The creation of the instruction trace is enabled by default but can be disabled for a simulation.
* This behaviour is controlled by the plusarg "ibex_tracer_enable". Use "ibex_tracer_enable=0" to
* This behaviour is controlled by the plusarg "cve2_tracer_enable". Use "cve2_tracer_enable=0" to
* disable the tracer.
*
* The trace contains six columns, separated by tabs:
@ -34,7 +34,7 @@
* to the one produced by objdump. This simplifies the correlation between the static program
* information from the objdump-generated disassembly, and the runtime information from this tracer.
*/
module ibex_tracer (
module cve2_tracer (
input logic clk_i,
input logic rst_ni,
@ -79,7 +79,7 @@ module ibex_tracer (
logic [ 1:0] unused_rvfi_mode = rvfi_mode;
logic [ 1:0] unused_rvfi_ixl = rvfi_ixl;
import ibex_tracer_pkg::*;
import cve2_tracer_pkg::*;
int file_handle;
string file_name;
@ -98,7 +98,7 @@ module ibex_tracer (
logic trace_log_enable;
initial begin
if ($value$plusargs("ibex_tracer_enable=%b", trace_log_enable)) begin
if ($value$plusargs("cve2_tracer_enable=%b", trace_log_enable)) begin
if (trace_log_enable == 1'b0) begin
$display("%m: Instruction trace disabled.");
end
@ -112,7 +112,7 @@ module ibex_tracer (
if (file_handle == 32'h0) begin
string file_name_base = "trace_core";
void'($value$plusargs("ibex_tracer_file_base=%s", file_name_base));
void'($value$plusargs("cve2_tracer_file_base=%s", file_name_base));
$sformat(file_name, "%s_%h.log", file_name_base, hart_id_i);
$display("%m: Writing execution trace to %s", file_name);

4
rtl/ibex_tracer_pkg.sv → rtl/cve2_tracer_pkg.sv
View file

@ -3,8 +3,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
package ibex_tracer_pkg;
import ibex_pkg::*;
package cve2_tracer_pkg;
import cve2_pkg::*;
parameter logic [1:0] OPCODE_C0 = 2'b00;
parameter logic [1:0] OPCODE_C1 = 2'b01;

6
rtl/ibex_wb_stage.sv → rtl/cve2_wb_stage.sv
View file

@ -14,7 +14,7 @@
`include "prim_assert.sv"
`include "dv_fcov_macros.svh"
module ibex_wb_stage #(
module cve2_wb_stage #(
parameter bit ResetAll = 1'b0,
parameter bit WritebackStage = 1'b0
) (
@ -22,7 +22,7 @@ module ibex_wb_stage #(
input logic rst_ni,
input logic en_wb_i,
input ibex_pkg::wb_instr_type_e instr_type_wb_i,
input cve2_pkg::wb_instr_type_e instr_type_wb_i,
input logic [31:0] pc_id_i,
input logic instr_is_compressed_id_i,
input logic instr_perf_count_id_i,
@ -56,7 +56,7 @@ module ibex_wb_stage #(
output logic instr_done_wb_o
);
import ibex_pkg::*;
import cve2_pkg::*;
// 0 == RF write from ID
// 1 == RF write from LSU

17
rtl/ibex_core.f
View file

@ -1,17 +0,0 @@
ibex_pkg.sv
ibex_alu.sv
ibex_compressed_decoder.sv
ibex_controller.sv
ibex_counter.sv
ibex_cs_registers.sv
ibex_decoder.sv
ibex_ex_block.sv
ibex_id_stage.sv
ibex_if_stage.sv
ibex_load_store_unit.sv
ibex_multdiv_slow.sv
ibex_multdiv_fast.sv
ibex_prefetch_buffer.sv
ibex_fetch_fifo.sv
ibex_register_file_ff.sv
ibex_core.sv

2
shared/fpga_xilinx.core
View file

@ -2,7 +2,7 @@ CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:fpga_xilinx_shared"
name: "lowrisc:cve2:fpga_xilinx_shared"
description: "Collection of useful RTL for Xilinx based examples"
filesets:
files_sv:

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