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Fix deadlock

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This commit is contained in:
Markus Wegmann 2017-01-12 19:16:27 +01:00
parent 8cee19ae74
commit 946c31ab9a
2 changed files with 11 additions and 12 deletions
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2
id_stage.sv
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@ -1796,7 +1796,7 @@ module riscv_id_stage
`ifdef ONLY_ALIGNED
assign id_ready_o = ((~jr_stall) & (~load_stall) & ex_ready_i);
`else
assign id_ready_o = ((~misaligned_stall & first_cycle_misaligned_i) & (~jr_stall) & (~load_stall) & ex_ready_i);
assign id_ready_o = ((~first_cycle_misaligned_i) & (~jr_stall) & (~load_stall) & ex_ready_i);
`endif // ONLY_ALIGNED
`else
`ifdef ONLY_ALIGNED

21
include/riscv_config.sv
View file

@ -58,6 +58,14 @@
// will enable bit manipulation and counting support.
//`define BIT_SUPPORT
// CONFIG: MATH_SPECIAL_SUPPORT
// will enable clip, min and max operations support.
//`define MATH_SPECIAL_SUPPORT
// CONFIG: JUMP_IN_ID
// will enable direct jump in ID. Might increase critical path of jump target.
`define JUMP_IN_ID
// CONFIG: LSU_ADDER_SUPPORT
// will enable an additional adder in the LSU for better timings.
//`define LSU_ADDER_SUPPORT
@ -70,14 +78,6 @@
`endif // LSU_ADDER_SUPPORT
// CONFIG: MATH_SPECIAL_SUPPORT
// will enable clip, min and max operations support.
//`define MATH_SPECIAL_SUPPORT
// CONFIG: JUMP_IN_ID
// will enable direct jump in ID. Might increase critical path of jump target
`define JUMP_IN_ID
// Dependent definitions
@ -103,17 +103,16 @@
// CONFIG: RV32E
// will reduce the register file to 16 words
`define RV32E
//`define RV32E
// CONFIG: ONLY_ALIGNED
// will only allow aligned memory accesses and therefore overlapping mustn't occur
`define ONLY_ALIGNED
//`define ONLY_ALIGNED
// CONFIG: SPLITTED_ADDER
// will split ALU Adder in half and use two cycles to add operands
//`define SPLITTED_ADDER
`ifndef SPLITTED_ADDER
`ifdef JUMP_IN_ID
// CONFIG: MERGE_ID_EX