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Update google_riscv-dv to google/riscv-dv@d341944 (#353)
Update code from upstream repository https://github.com/google/riscv- dv to revision d3419444ca2fdb499a204587b2d36c6f5c1e0c44 * Update README (Udi) * Add knob to enable full CSR randomization, fix mstatus.spp (Udi)
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2
vendor/google_riscv-dv.lock.hjson
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vendor/google_riscv-dv.lock.hjson
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@ -9,6 +9,6 @@
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upstream:
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{
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url: https://github.com/google/riscv-dv
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rev: e3e1e308cfc3d718aeb94bb3463371979d9a31ae
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rev: d3419444ca2fdb499a204587b2d36c6f5c1e0c44
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}
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}
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19
vendor/google_riscv-dv/README.md
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vendor/google_riscv-dv/README.md
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@ -7,12 +7,16 @@ processor verification. It currently supports the following features:
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- Supported privileged mode: machine mode, supervisor mode, user mode
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- Page table randomization and exception
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- Privileged CSR setup randomization
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- Privileged CSR test suite
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- Trap/interrupt handling
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- Test suite to stress test MMU
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- Support sub-programs and random program calls
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- Support illegal instruction and HINT instruction
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- Random forward/backward branch instructions
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- Supports mixing directed instructions with random instruction stream
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- Debug mode support, with fully randomized debug ROM
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- Instruction generation coverage model
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- Communication of information to any integrated SV testbench
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- Supports co-simulation with multiple ISS : spike, riscv-ovpsim
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A CSR test generation script written in Python is also provided, to generate a
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@ -213,7 +217,7 @@ program. You can modify the link script to link each section to the target
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memory location. Please avoid setting a large memory range as it could takes a
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long time to randomly initializing the memory. You can break down a large memory
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region to a few representative small regions which covers all the boundary
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conditions for the load/store testing.
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conditions for the load/store testing.
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### Runtime options of the generator
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@ -224,8 +228,10 @@ conditions for the load/store testing.
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| num_of_sub_program | Number of sub-program in one test | 5 |
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| instr_cnt | Instruction count per test | 200 |
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| enable_page_table_exception | Enable page table exception | 0 |
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| enable_unaligned_load_store | Enable unaligned memory operations | 0 |
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| no_ebreak | Disable ebreak instruction | 1 |
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| no_wfi | Disable WFI instruction | 1 |
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| no_dret | Disable dret instruction | 1 |
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| no_branch_jump | Disable branch/jump instruction | 0 |
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| no_load_store | Disable load/store instruction | 0 |
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| no_csr_instr | Disable CSR instruction | 0 |
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@ -239,6 +245,9 @@ conditions for the load/store testing.
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| enable_interrupt | Enable MStatus.MIE, used in interrupt test | 0 |
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| gen_debug_section | Disables randomized debug_rom section | 0 |
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| num_debug_sub_program | Number of debug sub-programs in test | 0 |
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| enable_ebreak_in_debug_rom | Generate ebreak instructions inside debug ROM | 0 |
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| set_dcsr_ebreak | Randomly enable dcsr.ebreak(m/s/u) | 0 |
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| randomize_csr | Fully randomize main CSRs (xSTATUS, xIE) | 0 |
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### Setup Privileged CSR description
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@ -409,14 +418,6 @@ collaborative effort to build a strong open source RISC-V processor
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verification platform. Free feel to submit your pull request for review.
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Please refer to CONTRIBUTING.md for license related questions.
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## Future release plan
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We have some work in progress which will be part of future releases:
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- Privileged CSR test suite.
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- Coverage model.
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- Debug mode support
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## Disclaimer
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This is not an officially supported Google product.
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@ -147,6 +147,7 @@ class riscv_instr_gen_config extends uvm_object;
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// - Accessing non-existence CSR
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// - Accessing CSR with wrong privileged mode
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bit enable_illegal_csr_instruction;
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bit randomize_csr = 0;
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// sfence support
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bit allow_sfence_exception = 0;
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// Interrupt/Exception Delegation
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@ -368,6 +369,7 @@ class riscv_instr_gen_config extends uvm_object;
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get_bool_arg_value("+force_m_delegation=", force_m_delegation);
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get_bool_arg_value("+force_s_delegation=", force_s_delegation);
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get_bool_arg_value("+require_signature_addr=", require_signature_addr);
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get_bool_arg_value("+randomize_csr=", randomize_csr);
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if (this.require_signature_addr) begin
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get_hex_arg_value("+signature_addr=", signature_addr);
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end
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@ -55,8 +55,15 @@ class riscv_privileged_common_seq extends uvm_sequence;
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virtual function void setup_mmode_reg(privileged_mode_t mode, ref riscv_privil_reg regs[$]);
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mstatus = riscv_privil_reg::type_id::create("mstatus");
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mstatus.init_reg(MSTATUS);
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mstatus.set_val({cfg.mstatus[XLEN-1:XLEN-21], cfg.mstatus_tvm, cfg.mstatus_mxr,
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if (cfg.randomize_csr) begin
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mstatus.set_val({cfg.mstatus[XLEN-1:XLEN-21], cfg.mstatus_tvm, cfg.mstatus_mxr,
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cfg.mstatus_sum, cfg.mstatus_mprv, cfg.mstatus[16:0]});
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end else begin
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mstatus.set_field("MPRV", cfg.mstatus_mprv);
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mstatus.set_field("MXR", cfg.mstatus_mxr);
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mstatus.set_field("SUM", cfg.mstatus_sum);
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mstatus.set_field("TVM", cfg.mstatus_tvm);
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end
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if(XLEN==64) begin
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mstatus.set_field("UXL", 2'b10);
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mstatus.set_field("SXL", 2'b10);
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@ -67,10 +74,7 @@ class riscv_privileged_common_seq extends uvm_sequence;
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mstatus.set_field("UIE", 0);
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// Set the previous privileged mode as the target mode
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mstatus.set_field("MPP", mode);
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if(mode == USER_MODE)
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mstatus.set_field("SPP", 0);
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else
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mstatus.set_field("SPP", 1);
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mstatus.set_field("SPP", 0);
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// Enable interrupt
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mstatus.set_field("MPIE", cfg.enable_interrupt);
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mstatus.set_field("MIE", cfg.enable_interrupt);
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@ -84,7 +88,9 @@ class riscv_privileged_common_seq extends uvm_sequence;
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if (MIE inside {implemented_csr}) begin
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mie = riscv_privil_reg::type_id::create("mie");
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mie.init_reg(MIE);
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mie.set_val(cfg.mie);
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if (cfg.randomize_csr) begin
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mie.set_val(cfg.mie);
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end
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mie.set_field("UEIE", cfg.enable_interrupt);
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mie.set_field("SEIE", cfg.enable_interrupt);
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mie.set_field("MEIE", cfg.enable_interrupt);
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@ -105,7 +111,9 @@ class riscv_privileged_common_seq extends uvm_sequence;
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sstatus = riscv_privil_reg::type_id::create("sstatus");
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sstatus.init_reg(SSTATUS);
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`DV_CHECK_RANDOMIZE_FATAL(sstatus, "cannot randomize sstatus")
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sstatus.set_val(cfg.sstatus);
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if (cfg.randomize_csr) begin
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sstatus.set_val(cfg.sstatus);
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end
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sstatus.set_field("SPIE", cfg.enable_interrupt);
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sstatus.set_field("SIE", cfg.enable_interrupt);
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sstatus.set_field("UPIE", cfg.enable_interrupt);
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@ -117,16 +125,15 @@ class riscv_privileged_common_seq extends uvm_sequence;
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sstatus.set_field("FS", 0);
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sstatus.set_field("SD", 0);
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sstatus.set_field("UIE", 0);
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if(mode == USER_MODE)
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sstatus.set_field("SPP", 0);
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else
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sstatus.set_field("SPP", 1);
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sstatus.set_field("SPP", 0);
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regs.push_back(sstatus);
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// Enable external and timer interrupt
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if (SIE inside {implemented_csr}) begin
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sie = riscv_privil_reg::type_id::create("sie");
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sie.init_reg(SIE);
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sie.set_val(cfg.sie);
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if (cfg.randomize_csr) begin
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sie.set_val(cfg.sie);
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end
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sie.set_field("UEIE", cfg.enable_interrupt);
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sie.set_field("SEIE", cfg.enable_interrupt);
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sie.set_field("USIE", cfg.enable_interrupt);
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@ -141,14 +148,18 @@ class riscv_privileged_common_seq extends uvm_sequence;
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ustatus = riscv_privil_reg::type_id::create("ustatus");
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ustatus.init_reg(USTATUS);
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`DV_CHECK_RANDOMIZE_FATAL(ustatus, "cannot randomize ustatus")
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ustatus.set_val(cfg.ustatus);
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if (cfg.randomize_csr) begin
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ustatus.set_val(cfg.ustatus);
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end
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ustatus.set_field("UIE", cfg.enable_interrupt);
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ustatus.set_field("UPIE", cfg.enable_interrupt);
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regs.push_back(ustatus);
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if (UIE inside {implemented_csr}) begin
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uie = riscv_privil_reg::type_id::create("uie");
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uie.init_reg(UIE);
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uie.set_val(cfg.uie);
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if (cfg.randomize_csr) begin
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uie.set_val(cfg.uie);
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end
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uie.set_field("UEIE", cfg.enable_interrupt);
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uie.set_field("USIE", cfg.enable_interrupt);
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uie.set_field("UTIE", 1'b0);
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