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Trigger an invalid instruction if jalr op code bits 14:12 are not zero

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Robert Schilling 2016-06-13 14:37:19 +02:00
parent 3277a983c7
commit 99da96f66b
1 changed files with 1 additions and 1 deletions
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2
decoder.sv
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@ -221,7 +221,7 @@ module riscv_decoder
if (instr_rdata_i[14:12] != 3'b0) begin
jump_in_id = `BRANCH_NONE;
regfile_alu_we = 1'b0;
illegal_insn_o = 1'b0;
illegal_insn_o = 1'b1;
end
end