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move nmi to irq 32 (#139)

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* move nmi to irq 32

* fix exc cause

* update top tracing

* fix mcause read
This commit is contained in:
Davide Schiavone 2023-08-30 14:24:16 +02:00 • committed by GitHub
parent 4e5dc5bf8b
commit 9a79be864f
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GPG key ID: 4AEE18F83AFDEB23
7 changed files with 38 additions and 38 deletions
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11
rtl/cve2_controller.sv
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@ -303,7 +303,7 @@ module cve2_controller #(
always_comb begin : gen_mfip_id always_comb begin : gen_mfip_id
mfip_id = 4'd0; mfip_id = 4'd0;
for (int i = 14; i >= 0; i--) begin for (int i = 15; i >= 0; i--) begin
if (irqs_i.irq_fast[i]) begin if (irqs_i.irq_fast[i]) begin
mfip_id = i[3:0]; mfip_id = i[3:0];
end end
@ -499,12 +499,13 @@ module cve2_controller #(
if (irq_nm_i && !nmi_mode_q) begin if (irq_nm_i && !nmi_mode_q) begin
exc_cause_o = EXC_CAUSE_IRQ_NM; exc_cause_o = EXC_CAUSE_IRQ_NM;
nmi_mode_d = 1'b1; // enter NMI mode nmi_mode_d = 1'b1; // enter NMI mode
end else if (irqs_i.irq_fast != 15'b0) begin end else if (irqs_i.irq_fast != 16'b0) begin
// generate exception cause ID from fast interrupt ID: // generate exception cause ID from fast interrupt ID:
// - first bit distinguishes interrupts from exceptions, // - first bit distinguishes interrupts from exceptions,
// - second bit adds 16 to fast interrupt ID // - third bit adds 16 to fast interrupt ID so that the interrup 0 becomes 16 and the interrupt 15 becomes 31 (hence 5bits)
// for example EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16} // - second bit is always 0 as the FAST interrupts are represented in the first 5bits, the 6th is always 0 cause is used by the NMI (in that case is 1 as represented by the number 32)
exc_cause_o = exc_cause_e'({2'b11, mfip_id}); // for example EXC_CAUSE_IRQ_FAST_0 = {1'b1, 6'd16}
exc_cause_o = exc_cause_e'({3'b101, mfip_id});
end else if (irqs_i.irq_external) begin end else if (irqs_i.irq_external) begin
exc_cause_o = EXC_CAUSE_IRQ_EXTERNAL_M; exc_cause_o = EXC_CAUSE_IRQ_EXTERNAL_M;
end else if (irqs_i.irq_software) begin end else if (irqs_i.irq_software) begin

2
rtl/cve2_core.sv
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@ -58,7 +58,7 @@ module cve2_core import cve2_pkg::*; #(
input logic irq_software_i, input logic irq_software_i,
input logic irq_timer_i, input logic irq_timer_i,
input logic irq_external_i, input logic irq_external_i,
input logic [14:0] irq_fast_i, input logic [15:0] irq_fast_i,
input logic irq_nm_i, // non-maskeable interrupt input logic irq_nm_i, // non-maskeable interrupt
output logic irq_pending_o, output logic irq_pending_o,

14
rtl/cve2_cs_registers.sv
View file

@ -53,7 +53,7 @@ module cve2_cs_registers #(
input logic irq_software_i, input logic irq_software_i,
input logic irq_timer_i, input logic irq_timer_i,
input logic irq_external_i, input logic irq_external_i,
input logic [14:0] irq_fast_i, input logic [15:0] irq_fast_i,
input logic nmi_mode_i, input logic nmi_mode_i,
output logic irq_pending_o, // interrupt request pending output logic irq_pending_o, // interrupt request pending
output cve2_pkg::irqs_t irqs_o, // interrupt requests qualified with mie output cve2_pkg::irqs_t irqs_o, // interrupt requests qualified with mie
@ -169,7 +169,7 @@ module cve2_cs_registers #(
logic mscratch_en; logic mscratch_en;
logic [31:0] mepc_q, mepc_d; logic [31:0] mepc_q, mepc_d;
logic mepc_en; logic mepc_en;
logic [5:0] mcause_q, mcause_d; logic [6:0] mcause_q, mcause_d;
logic mcause_en; logic mcause_en;
logic [31:0] mtval_q, mtval_d; logic [31:0] mtval_q, mtval_d;
logic mtval_en; logic mtval_en;
@ -189,7 +189,7 @@ module cve2_cs_registers #(
status_stk_t mstack_q, mstack_d; status_stk_t mstack_q, mstack_d;
logic mstack_en; logic mstack_en;
logic [31:0] mstack_epc_q, mstack_epc_d; logic [31:0] mstack_epc_q, mstack_epc_d;
logic [5:0] mstack_cause_q, mstack_cause_d; logic [6:0] mstack_cause_q, mstack_cause_d;
// PMP Signals // PMP Signals
logic [31:0] pmp_addr_rdata [PMP_MAX_REGIONS]; logic [31:0] pmp_addr_rdata [PMP_MAX_REGIONS];
@ -318,7 +318,7 @@ module cve2_cs_registers #(
CSR_MEPC: csr_rdata_int = mepc_q; CSR_MEPC: csr_rdata_int = mepc_q;
// mcause: exception cause // mcause: exception cause
CSR_MCAUSE: csr_rdata_int = {mcause_q[5], 26'b0, mcause_q[4:0]}; CSR_MCAUSE: csr_rdata_int = {mcause_q[6], 25'b0, mcause_q[5:0]};
// mtval: trap value // mtval: trap value
CSR_MTVAL: csr_rdata_int = mtval_q; CSR_MTVAL: csr_rdata_int = mtval_q;
@ -482,7 +482,7 @@ module cve2_cs_registers #(
mepc_en = 1'b0; mepc_en = 1'b0;
mepc_d = {csr_wdata_int[31:1], 1'b0}; mepc_d = {csr_wdata_int[31:1], 1'b0};
mcause_en = 1'b0; mcause_en = 1'b0;
mcause_d = {csr_wdata_int[31], csr_wdata_int[4:0]}; mcause_d = {csr_wdata_int[31], csr_wdata_int[5:0]};
mtval_en = 1'b0; mtval_en = 1'b0;
mtval_d = csr_wdata_int; mtval_d = csr_wdata_int;
mtvec_en = csr_mtvec_init_i; mtvec_en = csr_mtvec_init_i;
@ -807,7 +807,7 @@ module cve2_cs_registers #(
// MCAUSE // MCAUSE
cve2_csr #( cve2_csr #(
.Width (6), .Width (7),
.ShadowCopy(1'b0), .ShadowCopy(1'b0),
.ResetValue('0) .ResetValue('0)
) u_mcause_csr ( ) u_mcause_csr (
@ -939,7 +939,7 @@ module cve2_cs_registers #(
// MSTACK_CAUSE // MSTACK_CAUSE
cve2_csr #( cve2_csr #(
.Width (6), .Width (7),
.ShadowCopy(1'b0), .ShadowCopy(1'b0),
.ResetValue('0) .ResetValue('0)
) u_mstack_cause_csr ( ) u_mstack_cause_csr (

10
rtl/cve2_if_stage.sv
View file

@ -101,7 +101,7 @@ module cve2_if_stage import cve2_pkg::*; #(
logic [31:0] exc_pc; logic [31:0] exc_pc;
logic [5:0] irq_id; logic [6:0] irq_id;
logic unused_irq_bit; logic unused_irq_bit;
logic if_id_pipe_reg_we; // IF-ID pipeline reg write enable logic if_id_pipe_reg_we; // IF-ID pipeline reg write enable
@ -116,16 +116,16 @@ module cve2_if_stage import cve2_pkg::*; #(
// extract interrupt ID from exception cause // extract interrupt ID from exception cause
assign irq_id = {exc_cause}; assign irq_id = {exc_cause};
assign unused_irq_bit = irq_id[5]; // MSB distinguishes interrupts from exceptions assign unused_irq_bit = irq_id[6]; // MSB distinguishes interrupts from exceptions
// exception PC selection mux // exception PC selection mux
always_comb begin : exc_pc_mux always_comb begin : exc_pc_mux
unique case (exc_pc_mux_i) unique case (exc_pc_mux_i)
EXC_PC_EXC: exc_pc = { csr_mtvec_i[31:8], 8'h00 }; EXC_PC_EXC: exc_pc = { csr_mtvec_i[31:8], 8'h00 };
EXC_PC_IRQ: exc_pc = { csr_mtvec_i[31:8], 1'b0, irq_id[4:0], 2'b00 }; EXC_PC_IRQ: exc_pc = { csr_mtvec_i[31:8], irq_id[5:0], 2'b00 };
EXC_PC_DBD: exc_pc = DmHaltAddr; EXC_PC_DBD: exc_pc = DmHaltAddr;
EXC_PC_DBG_EXC: exc_pc = DmExceptionAddr; EXC_PC_DBG_EXC: exc_pc = DmExceptionAddr;
default: exc_pc = { csr_mtvec_i[31:8], 8'h00 }; default: exc_pc = { csr_mtvec_i[31:8], 8'h00 };
endcase endcase
end end

35
rtl/cve2_pkg.sv
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@ -292,26 +292,25 @@ package cve2_pkg;
logic irq_software; logic irq_software;
logic irq_timer; logic irq_timer;
logic irq_external; logic irq_external;
logic [14:0] irq_fast; // 15 fast interrupts, logic [15:0] irq_fast; // 16 fast interrupts
// one interrupt is reserved for NMI (not visible through mip/mie)
} irqs_t; } irqs_t;
// Exception cause // Exception cause
typedef enum logic [5:0] { typedef enum logic [6:0] {
EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd03}, EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 6'd03},
EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd07}, EXC_CAUSE_IRQ_TIMER_M = {1'b1, 6'd07},
EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}, EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 6'd11},
// EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16}, // EXC_CAUSE_IRQ_FAST_0 = {1'b1, 6'd16},
// EXC_CAUSE_IRQ_FAST_14 = {1'b1, 5'd30}, // EXC_CAUSE_IRQ_FAST_15 = {1'b1, 6'd31},
EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}, // == EXC_CAUSE_IRQ_FAST_15 EXC_CAUSE_IRQ_NM = {1'b1, 6'd32},
EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd00}, EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 6'd00},
EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd01}, EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},
EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd02}, EXC_CAUSE_ILLEGAL_INSN = {1'b0, 6'd02},
EXC_CAUSE_BREAKPOINT = {1'b0, 5'd03}, EXC_CAUSE_BREAKPOINT = {1'b0, 6'd03},
EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd05}, EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 6'd05},
EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07}, EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},
EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd08}, EXC_CAUSE_ECALL_UMODE = {1'b0, 6'd08},
EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11} EXC_CAUSE_ECALL_MMODE = {1'b0, 6'd11}
} exc_cause_e; } exc_cause_e;
// Debug cause // Debug cause
@ -547,7 +546,7 @@ package cve2_pkg;
parameter int unsigned CSR_MTIX_BIT = 7; parameter int unsigned CSR_MTIX_BIT = 7;
parameter int unsigned CSR_MEIX_BIT = 11; parameter int unsigned CSR_MEIX_BIT = 11;
parameter int unsigned CSR_MFIX_BIT_LOW = 16; parameter int unsigned CSR_MFIX_BIT_LOW = 16;
parameter int unsigned CSR_MFIX_BIT_HIGH = 30; parameter int unsigned CSR_MFIX_BIT_HIGH = 31;
// CSR Machine Security Configuration bits // CSR Machine Security Configuration bits
parameter int unsigned CSR_MSECCFG_MML_BIT = 0; parameter int unsigned CSR_MSECCFG_MML_BIT = 0;

2
rtl/cve2_top.sv
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@ -53,7 +53,7 @@ module cve2_top import cve2_pkg::*; #(
input logic irq_software_i, input logic irq_software_i,
input logic irq_timer_i, input logic irq_timer_i,
input logic irq_external_i, input logic irq_external_i,
input logic [14:0] irq_fast_i, input logic [15:0] irq_fast_i,
input logic irq_nm_i, // non-maskeable interrupt input logic irq_nm_i, // non-maskeable interrupt
// Debug Interface // Debug Interface

2
rtl/cve2_top_tracing.sv
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@ -49,7 +49,7 @@ module cve2_top_tracing import cve2_pkg::*; #(
input logic irq_software_i, input logic irq_software_i,
input logic irq_timer_i, input logic irq_timer_i,
input logic irq_external_i, input logic irq_external_i,
input logic [14:0] irq_fast_i, input logic [15:0] irq_fast_i,
input logic irq_nm_i, // non-maskeable interrupt input logic irq_nm_i, // non-maskeable interrupt
// Debug Interface // Debug Interface