mirror of
https://github.com/openhwgroup/cve2.git
synced 2025-06-27 17:01:13 -04:00
fix verilator and add clk gating cell (#114)
* fix verilator * add clk gating cell * remove prim_generic_buf from manifest * fix comment
This commit is contained in:
Davide Schiavone
GitHub
parent
67def6f46e
commit
9abe653e1b
15 changed files with 189 additions and 213 deletions
2
Makefile
2
Makefile
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@ -51,6 +51,8 @@ run-simple-system: sw-simple-hello | $(Vcve2_simple_system)
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build/lowrisc_cve2_cve2_simple_system_0/sim-verilator/Vcve2_simple_system \
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--raminit=$(simple-system-program)
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compile_verilator:
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fusesoc --cores-root . run --no-export --target=lint --tool=verilator --setup --build lowrisc:cve2:cve2_top:0.1 2>&1 | tee buildsim.log
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# Arty A7 FPGA example
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# Use the following targets (depending on your hardware):
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30
bhv/cve2_sim_clock_gate.sv
Normal file
30
bhv/cve2_sim_clock_gate.sv
Normal file
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@ -0,0 +1,30 @@
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// Copyright 2017 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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// !!! cve2_sim_clock_gate file is meant for simulation only !!!
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// !!! It must not be used for ASIC synthesis !!!
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// !!! It must not be used for FPGA synthesis !!!
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module cve2_clock_gate (
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input logic clk_i,
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input logic en_i,
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input logic scan_cg_en_i,
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output logic clk_o
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);
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logic clk_en;
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always_latch begin
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if (clk_i == 1'b0) clk_en <= en_i | scan_cg_en_i;
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end
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assign clk_o = clk_i & clk_en;
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endmodule // cve2_clock_gate
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@ -61,5 +61,4 @@ ${DESIGN_RTL_DIR}/cve2_top.sv
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${DESIGN_RTL_DIR}/cve2_top_tracing.sv
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${DESIGN_RTL_DIR}/cve2_tracer.sv
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${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv
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${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv
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${DESIGN_RTL_DIR}/../bhv/cve2_sim_clock_gate.sv
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@ -12,7 +12,6 @@ filesets:
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- lowrisc:prim:clock_gating
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- lowrisc:prim:lfsr
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- lowrisc:cve2:cve2_pkg
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- lowrisc:cve2:cve2_icache
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- lowrisc:dv:dv_fcov_macros
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files:
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- rtl/cve2_alu.sv
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@ -33,7 +32,6 @@ filesets:
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- rtl/cve2_prefetch_buffer.sv
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- rtl/cve2_pmp.sv
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- rtl/cve2_wb_stage.sv
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- rtl/cve2_dummy_instr.sv
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- rtl/cve2_core.sv
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- rtl/cve2_pmp_reset_default.svh: {is_include_file: true}
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file_type: systemVerilogSource
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@ -142,6 +140,7 @@ targets:
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- tool_verilator ? (files_lint_verilator)
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- tool_veriblelint ? (files_lint_verible)
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- files_rtl
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- target_sim? (files_clk_gate)
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- files_check_tool_requirements
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toplevel: cve2_core
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parameters:
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@ -16,8 +16,6 @@ filesets:
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- lowrisc:prim:ram_1p_scr
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files:
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- rtl/cve2_register_file_ff.sv # generic FF-based
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- rtl/cve2_register_file_fpga.sv # FPGA
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- rtl/cve2_register_file_latch.sv # ASIC
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- rtl/cve2_top.sv
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file_type: systemVerilogSource
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@ -33,6 +31,11 @@ filesets:
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depend:
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- lowrisc:tool:check_tool_requirements
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files_clk_gate:
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files:
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- bhv/cve2_sim_clock_gate.sv
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file_type: systemVerilogSource
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parameters:
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RVFI:
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datatype: bool
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@ -131,6 +134,7 @@ targets:
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- tool_verilator ? (files_lint_verilator)
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- tool_veriblelint ? (files_lint_verible)
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- files_rtl
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- target_sim? (files_clk_gate)
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- files_check_tool_requirements
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toplevel: cve2_top
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parameters:
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@ -140,6 +144,8 @@ targets:
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parameters:
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- SYNTHESIS=true
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- RVFI=true
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filesets_append:
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- files_clk_gate
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default_tool: verilator
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tools:
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verilator:
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@ -149,6 +155,7 @@ targets:
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# RAM primitives wider than 64bit (required for ECC) fail to build in
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# Verilator without increasing the unroll count (see Verilator#1266)
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- "--unroll-count 72"
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format:
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filesets:
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- files_rtl
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@ -70,3 +70,5 @@ lint_off -file "*/lowrisc_prim_*/rtl/*.sv"
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lint_off -rule UNUSED -file "*/rtl/cve2_top_tracing.sv" -match "*RndCnstLfsrSeed*"
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lint_off -rule UNUSED -file "*/rtl/cve2_top_tracing.sv" -match "*RndCnstLfsrPerm*"
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lint_off -rule DECLFILENAME -file "*/bhv/cve2_sim_clock_gate.sv" -match "Filename 'cve2_sim_clock_gate' does not match MODULE name: 'cve2_clock_gate'"
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lint_off -rule UNOPTFLAT -file "*/rtl/cve2_core.sv" -match "Signal unoptimizable: Feedback to clock or circular logic: 'cve2_top.u_cve2_core.irqs'"
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@ -32,6 +32,8 @@ module cve2_core import cve2_pkg::*; #(
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input logic clk_i,
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input logic rst_ni,
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input logic test_en_i,
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input logic [31:0] hart_id_i,
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input logic [31:0] boot_addr_i,
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@ -102,9 +104,6 @@ module cve2_core import cve2_pkg::*; #(
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`endif
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// CPU Control Signals
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// SEC_CM: FETCH.CTRL.LC_GATED
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output logic alert_minor_o,
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output logic alert_major_o,
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output logic core_busy_o
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);
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@ -175,8 +174,6 @@ module cve2_core import cve2_pkg::*; #(
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logic [4:0] rf_waddr_id;
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logic [31:0] rf_wdata_id;
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logic rf_we_id;
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logic rf_rd_a_wb_match;
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logic rf_rd_b_wb_match;
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// ALU Control
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alu_op_e alu_operator_ex;
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@ -367,10 +364,8 @@ module cve2_core import cve2_pkg::*; #(
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// available
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assign perf_iside_wait = id_in_ready & ~instr_valid_id;
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begin : g_instr_req_gated_non_secure
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// For non secure Ibex only the bottom bit of fetch enable is considered
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assign instr_req_gated = instr_req_int;
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end
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// For non secure Ibex only the bottom bit of fetch enable is considered
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assign instr_req_gated = instr_req_int;
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//////////////
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// ID stage //
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@ -500,8 +495,8 @@ module cve2_core import cve2_pkg::*; #(
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.rf_waddr_id_o (rf_waddr_id),
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.rf_wdata_id_o (rf_wdata_id),
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.rf_we_id_o (rf_we_id),
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.rf_rd_a_wb_match_o(rf_rd_a_wb_match),
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.rf_rd_b_wb_match_o(rf_rd_b_wb_match),
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.rf_rd_a_wb_match_o(),
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.rf_rd_b_wb_match_o(),
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.rf_waddr_wb_i (rf_waddr_wb),
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.rf_wdata_fwd_wb_i(rf_wdata_fwd_wb),
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@ -659,15 +654,6 @@ module cve2_core import cve2_pkg::*; #(
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.instr_done_wb_o(instr_done_wb)
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);
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/////////////////////////////
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// Register file interface //
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/////////////////////////////
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assign rf_raddr_a_o = rf_raddr_a;
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assign rf_waddr_wb_o = rf_waddr_wb;
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assign rf_we_wb_o = rf_we_wb;
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assign rf_raddr_b_o = rf_raddr_b;
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///////////////////////
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// Crash dump output //
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///////////////////////
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@ -677,12 +663,6 @@ module cve2_core import cve2_pkg::*; #(
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assign crash_dump_o.last_data_addr = lsu_addr_last;
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assign crash_dump_o.exception_addr = csr_mepc;
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///////////////////
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// Alert outputs //
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///////////////////
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// Minor alert - core is in a recoverable state
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assign alert_minor_o = 1'b0;
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// Explict INC_ASSERT block to avoid unused signal lint warnings were asserts are not included
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`ifdef INC_ASSERT
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@ -726,26 +706,24 @@ module cve2_core import cve2_pkg::*; #(
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////////////////////////
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// RF (Register File) //
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////////////////////////
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begin : gen_regfile_ff
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cve2_register_file_ff #(
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.RV32E (RV32E),
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.DataWidth (32),
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.WordZeroVal (32'(prim_secded_pkg::SecdedInv3932ZeroWord))
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) register_file_i (
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.clk_i (clk_i),
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.rst_ni(rst_ni),
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cve2_register_file_ff #(
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.RV32E (RV32E),
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.DataWidth (32),
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.WordZeroVal (32'(prim_secded_pkg::SecdedInv3932ZeroWord))
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) register_file_i (
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.clk_i (clk_i),
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.rst_ni(rst_ni),
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.test_en_i (test_en_i),
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.test_en_i(test_en_i),
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.raddr_a_i(rf_raddr_a),
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.rdata_a_o(rf_rdata_a),
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.raddr_b_i(rf_raddr_b),
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.rdata_b_o(rf_rdata_b),
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.waddr_a_i(rf_waddr_wb),
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.wdata_a_i(rf_wdata_wb),
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.we_a_i (rf_we_wb)
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);
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end
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.raddr_a_i(rf_raddr_a),
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.rdata_a_o(rf_rdata_a),
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.raddr_b_i(rf_raddr_b),
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.rdata_b_o(rf_rdata_b),
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.waddr_a_i(rf_waddr_wb),
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.wdata_a_i(rf_wdata_wb),
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.we_a_i (rf_we_wb)
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);
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/////////////////////////////////////////
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@ -166,7 +166,6 @@ module cve2_cs_registers #(
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// CSRs
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priv_lvl_e priv_lvl_q, priv_lvl_d;
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status_t mstatus_q, mstatus_d;
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logic mstatus_err;
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logic mstatus_en;
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irqs_t mie_q, mie_d;
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logic mie_en;
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@ -179,7 +178,6 @@ module cve2_cs_registers #(
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logic [31:0] mtval_q, mtval_d;
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logic mtval_en;
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logic [31:0] mtvec_q, mtvec_d;
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logic mtvec_err;
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logic mtvec_en;
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irqs_t mip;
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dcsr_t dcsr_q, dcsr_d;
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@ -200,7 +198,6 @@ module cve2_cs_registers #(
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// PMP Signals
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logic [31:0] pmp_addr_rdata [PMP_MAX_REGIONS];
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logic [PMP_CFG_W-1:0] pmp_cfg_rdata [PMP_MAX_REGIONS];
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logic pmp_csr_err;
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pmp_mseccfg_t pmp_mseccfg;
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// Hardware performance monitor signals
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@ -766,7 +763,7 @@ module cve2_cs_registers #(
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.wr_data_i ({mstatus_d}),
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.wr_en_i (mstatus_en),
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.rd_data_o (mstatus_q),
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.rd_error_o(mstatus_err)
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.rd_error_o()
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);
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// MEPC
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@ -853,7 +850,7 @@ module cve2_cs_registers #(
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.wr_data_i (mtvec_d),
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.wr_en_i (mtvec_en),
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.rd_data_o (mtvec_q),
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.rd_error_o(mtvec_err)
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.rd_error_o()
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);
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// DCSR
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@ -1128,7 +1125,6 @@ module cve2_cs_registers #(
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.rd_error_o(pmp_mseccfg_err)
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);
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assign pmp_csr_err = (|pmp_cfg_err) | (|pmp_addr_err) | pmp_mseccfg_err;
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assign pmp_mseccfg = pmp_mseccfg_q;
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end else begin : g_no_pmp_tieoffs
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@ -1141,7 +1137,6 @@ module cve2_cs_registers #(
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assign csr_pmp_cfg_o[i] = pmp_cfg_t'(1'b0);
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assign csr_pmp_addr_o[i] = '0;
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end
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assign pmp_csr_err = 1'b0;
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assign pmp_mseccfg = '0;
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end
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@ -84,12 +84,10 @@ module cve2_ex_block #(
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// branch handling
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assign branch_decision_o = alu_cmp_result;
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begin : g_no_branch_target_alu
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// Unused bt_operand signals cause lint errors, this avoids them
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//logic [31:0] unused_bt_a_operand, unused_bt_b_operand;
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// Unused bt_operand signals cause lint errors, this avoids them
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//logic [31:0] unused_bt_a_operand, unused_bt_b_operand;
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assign branch_target_o = alu_adder_result_ex_o;
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end
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assign branch_target_o = alu_adder_result_ex_o;
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/////////
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// ALU //
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@ -148,13 +148,11 @@ module cve2_fetch_fifo #(
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assign instr_addr_d = clear_i ? in_addr_i[31:1] :
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instr_addr_next;
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begin : g_instr_addr
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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instr_addr_q <= '0;
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end else if (instr_addr_en) begin
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instr_addr_q <= instr_addr_d;
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end
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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instr_addr_q <= '0;
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end else if (instr_addr_en) begin
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instr_addr_q <= instr_addr_d;
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end
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end
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@ -298,32 +298,30 @@ module cve2_id_stage #(
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endcase
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end
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begin : g_nobtalu
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op_a_sel_e unused_a_mux_sel;
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imm_b_sel_e unused_b_mux_sel;
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op_a_sel_e unused_a_mux_sel;
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imm_b_sel_e unused_b_mux_sel;
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// Full main ALU immediate MUX for Operand B
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always_comb begin : immediate_b_mux
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unique case (imm_b_mux_sel)
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IMM_B_I: imm_b = imm_i_type;
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IMM_B_S: imm_b = imm_s_type;
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IMM_B_B: imm_b = imm_b_type;
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IMM_B_U: imm_b = imm_u_type;
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IMM_B_J: imm_b = imm_j_type;
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IMM_B_INCR_PC: imm_b = instr_is_compressed_i ? 32'h2 : 32'h4;
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IMM_B_INCR_ADDR: imm_b = 32'h4;
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default: imm_b = 32'h4;
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endcase
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end
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`ASSERT(IbexImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside {
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IMM_B_I,
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IMM_B_S,
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IMM_B_B,
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IMM_B_U,
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IMM_B_J,
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IMM_B_INCR_PC,
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IMM_B_INCR_ADDR})
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// Full main ALU immediate MUX for Operand B
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always_comb begin : immediate_b_mux
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unique case (imm_b_mux_sel)
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IMM_B_I: imm_b = imm_i_type;
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IMM_B_S: imm_b = imm_s_type;
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IMM_B_B: imm_b = imm_b_type;
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IMM_B_U: imm_b = imm_u_type;
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IMM_B_J: imm_b = imm_j_type;
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IMM_B_INCR_PC: imm_b = instr_is_compressed_i ? 32'h2 : 32'h4;
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IMM_B_INCR_ADDR: imm_b = 32'h4;
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default: imm_b = 32'h4;
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endcase
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end
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`ASSERT(IbexImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside {
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||||
IMM_B_I,
|
||||
IMM_B_S,
|
||||
IMM_B_B,
|
||||
IMM_B_U,
|
||||
IMM_B_J,
|
||||
IMM_B_INCR_PC,
|
||||
IMM_B_INCR_ADDR})
|
||||
|
||||
// ALU MUX for Operand B
|
||||
assign alu_operand_b = (alu_op_b_mux_sel == OP_B_IMM) ? imm_b : rf_rdata_b_fwd;
|
||||
|
|
@ -598,27 +596,25 @@ module cve2_id_stage #(
|
|||
// Branch set control //
|
||||
////////////////////////
|
||||
|
||||
begin : g_branch_set_flop
|
||||
// SEC_CM: CORE.DATA_REG_SW.SCA
|
||||
// Branch set flopped without branch target ALU, or in fixed time execution mode
|
||||
// (condition pass/fail used next cycle where branch target is calculated)
|
||||
logic branch_set_raw_q;
|
||||
// SEC_CM: CORE.DATA_REG_SW.SCA
|
||||
// Branch set flopped without branch target ALU, or in fixed time execution mode
|
||||
// (condition pass/fail used next cycle where branch target is calculated)
|
||||
logic branch_set_raw_q;
|
||||
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
branch_set_raw_q <= 1'b0;
|
||||
end else begin
|
||||
branch_set_raw_q <= branch_set_raw_d;
|
||||
end
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
branch_set_raw_q <= 1'b0;
|
||||
end else begin
|
||||
branch_set_raw_q <= branch_set_raw_d;
|
||||
end
|
||||
|
||||
// Branches always take two cycles in fixed time execution mode, with or without the branch
|
||||
// target ALU (to avoid a path from the branch decision into the branch target ALU operand
|
||||
// muxing).
|
||||
assign branch_set_raw = branch_set_raw_q;
|
||||
|
||||
end
|
||||
|
||||
// Branches always take two cycles in fixed time execution mode, with or without the branch
|
||||
// target ALU (to avoid a path from the branch decision into the branch target ALU operand
|
||||
// muxing).
|
||||
assign branch_set_raw = branch_set_raw_q;
|
||||
|
||||
|
||||
// Track whether the current instruction in ID/EX has done a branch or jump set.
|
||||
assign branch_jump_set_done_d = (branch_set_raw | jump_set_raw | branch_jump_set_done_q) &
|
||||
~instr_valid_clear_o;
|
||||
|
|
|
|||
|
|
@ -165,37 +165,35 @@ module cve2_if_stage import cve2_pkg::*; #(
|
|||
// tell CS register file to initialize mtvec on boot
|
||||
assign csr_mtvec_init_o = (pc_mux_i == PC_BOOT) & pc_set_i;
|
||||
|
||||
begin : gen_prefetch_buffer
|
||||
// prefetch buffer, caches a fixed number of instructions
|
||||
cve2_prefetch_buffer #(
|
||||
) prefetch_buffer_i (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( rst_ni ),
|
||||
// prefetch buffer, caches a fixed number of instructions
|
||||
cve2_prefetch_buffer #(
|
||||
) prefetch_buffer_i (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( rst_ni ),
|
||||
|
||||
.req_i ( req_i ),
|
||||
.req_i ( req_i ),
|
||||
|
||||
.branch_i ( branch_req ),
|
||||
.branch_mispredict_i ( nt_branch_mispredict_i ),
|
||||
.mispredict_addr_i ( nt_branch_addr_i ),
|
||||
.addr_i ( {fetch_addr_n[31:1], 1'b0} ),
|
||||
.branch_i ( branch_req ),
|
||||
.branch_mispredict_i ( nt_branch_mispredict_i ),
|
||||
.mispredict_addr_i ( nt_branch_addr_i ),
|
||||
.addr_i ( {fetch_addr_n[31:1], 1'b0} ),
|
||||
|
||||
.ready_i ( fetch_ready ),
|
||||
.valid_o ( fetch_valid ),
|
||||
.rdata_o ( fetch_rdata ),
|
||||
.addr_o ( fetch_addr ),
|
||||
.err_o ( fetch_err ),
|
||||
.err_plus2_o ( fetch_err_plus2 ),
|
||||
.ready_i ( fetch_ready ),
|
||||
.valid_o ( fetch_valid ),
|
||||
.rdata_o ( fetch_rdata ),
|
||||
.addr_o ( fetch_addr ),
|
||||
.err_o ( fetch_err ),
|
||||
.err_plus2_o ( fetch_err_plus2 ),
|
||||
|
||||
.instr_req_o ( instr_req_o ),
|
||||
.instr_addr_o ( instr_addr_o ),
|
||||
.instr_gnt_i ( instr_gnt_i ),
|
||||
.instr_rvalid_i ( instr_rvalid_i ),
|
||||
.instr_rdata_i ( instr_rdata_i ),
|
||||
.instr_err_i ( instr_err_i ),
|
||||
.instr_req_o ( instr_req_o ),
|
||||
.instr_addr_o ( instr_addr_o ),
|
||||
.instr_gnt_i ( instr_gnt_i ),
|
||||
.instr_rvalid_i ( instr_rvalid_i ),
|
||||
.instr_rdata_i ( instr_rdata_i ),
|
||||
.instr_err_i ( instr_err_i ),
|
||||
|
||||
.busy_o ( prefetch_busy )
|
||||
);
|
||||
end
|
||||
.busy_o ( prefetch_busy )
|
||||
);
|
||||
|
||||
assign unused_fetch_addr_n0 = fetch_addr_n[0];
|
||||
|
||||
|
|
@ -256,28 +254,26 @@ module cve2_if_stage import cve2_pkg::*; #(
|
|||
// IF-ID pipeline registers, frozen when the ID stage is stalled
|
||||
assign if_id_pipe_reg_we = instr_new_id_d;
|
||||
|
||||
begin : g_instr_rdata
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
instr_rdata_id_o <= '0;
|
||||
instr_rdata_alu_id_o <= '0;
|
||||
instr_fetch_err_o <= '0;
|
||||
instr_fetch_err_plus2_o <= '0;
|
||||
instr_rdata_c_id_o <= '0;
|
||||
instr_is_compressed_id_o <= '0;
|
||||
illegal_c_insn_id_o <= '0;
|
||||
pc_id_o <= '0;
|
||||
end else if (if_id_pipe_reg_we) begin
|
||||
instr_rdata_id_o <= instr_decompressed;
|
||||
// To reduce fan-out and help timing from the instr_rdata_id flops they are replicated.
|
||||
instr_rdata_alu_id_o <= instr_decompressed;
|
||||
instr_fetch_err_o <= if_instr_err;
|
||||
instr_fetch_err_plus2_o <= if_instr_err_plus2;
|
||||
instr_rdata_c_id_o <= if_instr_rdata[15:0];
|
||||
instr_is_compressed_id_o <= instr_is_compressed;
|
||||
illegal_c_insn_id_o <= illegal_c_insn;
|
||||
pc_id_o <= pc_if_o;
|
||||
end
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
instr_rdata_id_o <= '0;
|
||||
instr_rdata_alu_id_o <= '0;
|
||||
instr_fetch_err_o <= '0;
|
||||
instr_fetch_err_plus2_o <= '0;
|
||||
instr_rdata_c_id_o <= '0;
|
||||
instr_is_compressed_id_o <= '0;
|
||||
illegal_c_insn_id_o <= '0;
|
||||
pc_id_o <= '0;
|
||||
end else if (if_id_pipe_reg_we) begin
|
||||
instr_rdata_id_o <= instr_decompressed;
|
||||
// To reduce fan-out and help timing from the instr_rdata_id flops they are replicated.
|
||||
instr_rdata_alu_id_o <= instr_decompressed;
|
||||
instr_fetch_err_o <= if_instr_err;
|
||||
instr_fetch_err_plus2_o <= if_instr_err_plus2;
|
||||
instr_rdata_c_id_o <= if_instr_rdata[15:0];
|
||||
instr_is_compressed_id_o <= instr_is_compressed;
|
||||
illegal_c_insn_id_o <= illegal_c_insn;
|
||||
pc_id_o <= pc_if_o;
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -323,17 +319,15 @@ module cve2_if_stage import cve2_pkg::*; #(
|
|||
end
|
||||
end
|
||||
|
||||
begin : g_instr_skid
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
instr_skid_bp_taken_q <= '0;
|
||||
instr_skid_data_q <= '0;
|
||||
instr_skid_addr_q <= '0;
|
||||
end else if (instr_skid_en) begin
|
||||
instr_skid_bp_taken_q <= predict_branch_taken;
|
||||
instr_skid_data_q <= fetch_rdata;
|
||||
instr_skid_addr_q <= fetch_addr;
|
||||
end
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
instr_skid_bp_taken_q <= '0;
|
||||
instr_skid_data_q <= '0;
|
||||
instr_skid_addr_q <= '0;
|
||||
end else if (instr_skid_en) begin
|
||||
instr_skid_bp_taken_q <= predict_branch_taken;
|
||||
instr_skid_data_q <= fetch_rdata;
|
||||
instr_skid_addr_q <= fetch_addr;
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -154,13 +154,11 @@ module cve2_prefetch_buffer #(
|
|||
assign stored_addr_d = instr_addr;
|
||||
|
||||
// CPU resets with a branch, so no need to reset these addresses
|
||||
begin : g_stored_addr
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
stored_addr_q <= '0;
|
||||
end else if (stored_addr_en) begin
|
||||
stored_addr_q <= stored_addr_d;
|
||||
end
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
stored_addr_q <= '0;
|
||||
end else if (stored_addr_en) begin
|
||||
stored_addr_q <= stored_addr_d;
|
||||
end
|
||||
end
|
||||
// 2. fetch_addr_q
|
||||
|
|
@ -174,13 +172,11 @@ module cve2_prefetch_buffer #(
|
|||
// Current address + 4
|
||||
{{29{1'b0}},(valid_new_req & ~valid_req_q),2'b00};
|
||||
|
||||
begin : g_fetch_addr
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
fetch_addr_q <= '0;
|
||||
end else if (fetch_addr_en) begin
|
||||
fetch_addr_q <= fetch_addr_d;
|
||||
end
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
fetch_addr_q <= '0;
|
||||
end else if (fetch_addr_en) begin
|
||||
fetch_addr_q <= fetch_addr_d;
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -61,10 +61,8 @@ module cve2_register_file_ff #(
|
|||
end
|
||||
end
|
||||
|
||||
begin : g_normal_r0
|
||||
// R0 is nil
|
||||
assign rf_reg[0] = WordZeroVal;
|
||||
end
|
||||
// R0 is nil
|
||||
assign rf_reg[0] = WordZeroVal;
|
||||
|
||||
assign rf_reg[NUM_WORDS-1:1] = rf_reg_q[NUM_WORDS-1:1];
|
||||
|
||||
|
|
|
|||
|
|
@ -38,7 +38,6 @@ module cve2_top import cve2_pkg::*; #(
|
|||
input logic instr_rvalid_i,
|
||||
output logic [31:0] instr_addr_o,
|
||||
input logic [31:0] instr_rdata_i,
|
||||
input logic [6:0] instr_rdata_intg_i,
|
||||
input logic instr_err_i,
|
||||
|
||||
// Data memory interface
|
||||
|
|
@ -49,9 +48,7 @@ module cve2_top import cve2_pkg::*; #(
|
|||
output logic [3:0] data_be_o,
|
||||
output logic [31:0] data_addr_o,
|
||||
output logic [31:0] data_wdata_o,
|
||||
output logic [6:0] data_wdata_intg_o,
|
||||
input logic [31:0] data_rdata_i,
|
||||
input logic [6:0] data_rdata_intg_i,
|
||||
input logic data_err_i,
|
||||
|
||||
// Interrupt inputs
|
||||
|
|
@ -99,18 +96,11 @@ module cve2_top import cve2_pkg::*; #(
|
|||
`endif
|
||||
|
||||
// CPU Control Signals
|
||||
output logic alert_minor_o,
|
||||
output logic alert_major_internal_o,
|
||||
output logic alert_major_bus_o,
|
||||
output logic core_sleep_o,
|
||||
|
||||
// DFT bypass controls
|
||||
input logic scan_rst_ni
|
||||
output logic core_sleep_o
|
||||
);
|
||||
|
||||
// Scrambling Parameter
|
||||
localparam int unsigned NumAddrScrRounds = 0;
|
||||
localparam int unsigned NumDiffRounds = NumAddrScrRounds;
|
||||
|
||||
// Physical Memory Protection
|
||||
localparam bit PMPEnable = 1'b0;
|
||||
|
|
@ -129,8 +119,6 @@ module cve2_top import cve2_pkg::*; #(
|
|||
logic core_busy_d, core_busy_q;
|
||||
logic clock_en;
|
||||
logic irq_pending;
|
||||
// Alert signals
|
||||
logic core_alert_major, core_alert_minor;
|
||||
|
||||
/////////////////////
|
||||
// Main clock gate //
|
||||
|
|
@ -147,10 +135,10 @@ module cve2_top import cve2_pkg::*; #(
|
|||
assign clock_en = core_busy_q | debug_req_i | irq_pending | irq_nm_i;
|
||||
assign core_sleep_o = ~clock_en;
|
||||
|
||||
prim_clock_gating core_clock_gate_i (
|
||||
cve2_clock_gate core_clock_gate_i (
|
||||
.clk_i (clk_i),
|
||||
.en_i (clock_en),
|
||||
.test_en_i(test_en_i),
|
||||
.scan_cg_en_i(test_en_i),
|
||||
.clk_o (clk)
|
||||
);
|
||||
|
||||
|
|
@ -176,6 +164,7 @@ module cve2_top import cve2_pkg::*; #(
|
|||
) u_cve2_core (
|
||||
.clk_i(clk),
|
||||
.rst_ni,
|
||||
.test_en_i,
|
||||
|
||||
.hart_id_i,
|
||||
.boot_addr_i,
|
||||
|
|
@ -237,8 +226,6 @@ module cve2_top import cve2_pkg::*; #(
|
|||
.rvfi_ext_mcycle,
|
||||
`endif
|
||||
|
||||
.alert_minor_o (core_alert_minor),
|
||||
.alert_major_o (core_alert_major),
|
||||
.core_busy_o (core_busy_d)
|
||||
);
|
||||
|
||||
|
|
@ -246,15 +233,12 @@ module cve2_top import cve2_pkg::*; #(
|
|||
// Rams Instantiation //
|
||||
////////////////////////
|
||||
|
||||
begin : gen_norams
|
||||
prim_ram_1p_pkg::ram_1p_cfg_t unused_ram_cfg;
|
||||
logic unused_ram_inputs;
|
||||
|
||||
prim_ram_1p_pkg::ram_1p_cfg_t unused_ram_cfg;
|
||||
logic unused_ram_inputs;
|
||||
assign unused_ram_cfg = ram_cfg_i;
|
||||
assign unused_ram_inputs = (|NumAddrScrRounds);
|
||||
|
||||
assign unused_ram_cfg = ram_cfg_i;
|
||||
assign unused_ram_inputs = (|NumAddrScrRounds);
|
||||
|
||||
end
|
||||
|
||||
// X checks for top-level outputs
|
||||
`ASSERT_KNOWN(IbexInstrReqX, instr_req_o)
|
||||
|
|
@ -278,11 +262,11 @@ module cve2_top import cve2_pkg::*; #(
|
|||
`ASSERT_KNOWN(IbexInstrGntX, instr_gnt_i)
|
||||
`ASSERT_KNOWN(IbexInstrRValidX, instr_rvalid_i)
|
||||
`ASSERT_KNOWN_IF(IbexInstrRPayloadX,
|
||||
{instr_rdata_i, instr_rdata_intg_i, instr_err_i}, instr_rvalid_i)
|
||||
{instr_rdata_i, instr_err_i}, instr_rvalid_i)
|
||||
|
||||
`ASSERT_KNOWN(IbexDataGntX, data_gnt_i)
|
||||
`ASSERT_KNOWN(IbexDataRValidX, data_rvalid_i)
|
||||
`ASSERT_KNOWN_IF(IbexDataRPayloadX, {data_rdata_i, data_rdata_intg_i, data_err_i}, data_rvalid_i)
|
||||
`ASSERT_KNOWN_IF(IbexDataRPayloadX, {data_rdata_i, data_err_i}, data_rvalid_i)
|
||||
|
||||
`ASSERT_KNOWN(IbexIrqX, {irq_software_i, irq_timer_i, irq_external_i, irq_fast_i, irq_nm_i})
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue