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Merge branch 'master' of iis-git.ee.ethz.ch:pulp-project/riscv
This commit is contained in:
Francesco Conti
commit
9ecd6d9868
16 changed files with 1249 additions and 116 deletions
22
README.md
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22
README.md
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@ -0,0 +1,22 @@
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# RI5CY: RISC-V Core
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RI5CY is a small 4-stage RISC-V core. It starte its life as a
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fork of the OR10N cpu core that is based on the OpenRISC ISA.
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RI5CY fully implements the RV32I instruction set, the multiply instruction from
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RV32M and many custom instruction set extensions that improve its performance
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for signal processing applications.
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The core was developed as part of the [PULP platform](http://pulp.ethz.ch/) for
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energy-efficient computing and is currently used as the processing core for
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PULP and PULPino.
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## Documentation
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A datasheet that explains the most important features of the core can be found
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in `docs/datasheet/`.
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It is written using LaTeX and can be generated as follows
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make all
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@ -71,7 +71,8 @@ module riscv_controller
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input logic trap_hit_i, // a trap was hit, so we have to flush EX and WB
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output logic save_pc_id_o,
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output logic exc_save_id_o,
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output logic exc_restore_id_o,
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// Debug Unit Signals
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input logic dbg_stall_i, // Pipeline stall is requested
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@ -158,23 +159,24 @@ module riscv_controller
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always_comb
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begin
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// Default values
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instr_req_o = 1'b1;
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instr_req_o = 1'b1;
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exc_ack_o = 1'b0;
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save_pc_id_o = 1'b0;
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exc_ack_o = 1'b0;
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exc_save_id_o = 1'b0;
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exc_restore_id_o = 1'b0;
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pc_mux_o = `PC_BOOT;
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pc_set_o = 1'b0;
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jump_done = jump_done_q;
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pc_mux_o = `PC_BOOT;
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pc_set_o = 1'b0;
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jump_done = jump_done_q;
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ctrl_fsm_ns = ctrl_fsm_cs;
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ctrl_fsm_ns = ctrl_fsm_cs;
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core_busy_o = 1'b1;
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is_decoding_o = 1'b0;
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core_busy_o = 1'b1;
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is_decoding_o = 1'b0;
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halt_if_o = 1'b0;
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halt_id_o = 1'b0;
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dbg_trap_o = 1'b0;
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halt_if_o = 1'b0;
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halt_id_o = 1'b0;
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dbg_trap_o = 1'b0;
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unique case (ctrl_fsm_cs)
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// We were just reset, wait for fetch_enable
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@ -227,7 +229,7 @@ module riscv_controller
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// TODO: This assumes that the pipeline is always flushed before
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// going to sleep.
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save_pc_id_o = 1'b1;
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exc_save_id_o = 1'b1;
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end
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end
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@ -266,7 +268,7 @@ module riscv_controller
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exc_ack_o = 1'b1;
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halt_id_o = 1'b1; // we don't want to propagate this instruction to EX
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save_pc_id_o = 1'b1;
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exc_save_id_o = 1'b1;
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// we don't have to change our current state here as the prefetch
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// buffer is automatically invalidated, thus the next instruction
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@ -276,8 +278,9 @@ module riscv_controller
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end
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if (eret_insn_i) begin
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pc_mux_o = `PC_ERET;
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pc_set_o = 1'b1;
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pc_mux_o = `PC_ERET;
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pc_set_o = 1'b1;
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exc_restore_id_o = 1'b1;
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end
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// handle WFI instruction, flush pipeline and (potentially) go to
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@ -55,10 +55,11 @@ module riscv_cs_registers
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// Interrupts
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output logic irq_enable_o,
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output logic [31:0] epcr_o,
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output logic [31:0] mepc_o,
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input logic [31:0] curr_pc_id_i,
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input logic save_pc_id_i,
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input logic exc_save_i,
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input logic exc_restore_i,
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input logic [5:0] exc_cause_i,
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input logic save_exc_cause_i,
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@ -115,17 +116,16 @@ module riscv_cs_registers
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logic is_pcer;
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logic is_pcmr;
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// Generic CSRs
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logic [31:0] mepc_q, mepc_n;
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// CSR update logic
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logic [31:0] csr_wdata_int;
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logic [31:0] csr_rdata_int;
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logic csr_we_int;
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// Interrupt control signals
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logic irq_enable, irq_enable_n;
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logic [5:0] exc_cause, exc_cause_n;
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logic [31:0] mepc_q, mepc_n;
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logic [ 0:0] mestatus_q, mestatus_n;
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logic [ 0:0] mstatus_q, mstatus_n;
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logic [ 5:0] exc_cause, exc_cause_n;
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////////////////////////////////////////////
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@ -144,7 +144,7 @@ module riscv_cs_registers
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case (csr_addr_i)
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// mstatus: always M-mode, contains IE bit
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12'h300: csr_rdata_int = {29'b0, 2'b11, irq_enable};
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12'h300: csr_rdata_int = {29'b0, 2'b11, mstatus_q};
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// mepc: exception program counter
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12'h341: csr_rdata_int = mepc_q;
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@ -165,6 +165,8 @@ module riscv_cs_registers
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12'h7B4: csr_rdata_int = hwlp_start_i[1];
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12'h7B5: csr_rdata_int = hwlp_end_i[1];
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12'h7B6: csr_rdata_int = hwlp_cnt_i[1];
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12'h7C0: csr_rdata_int = {29'b0, 2'b11, mestatus_q};
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endcase
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end
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@ -173,14 +175,15 @@ module riscv_cs_registers
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always_comb
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begin
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mepc_n = mepc_q;
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irq_enable_n = irq_enable;
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mestatus_n = mestatus_q;
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mstatus_n = mstatus_q;
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exc_cause_n = exc_cause;
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hwlp_we_o = '0;
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hwlp_regid_o = '0;
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case (csr_addr_i)
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// mstatus: IE bit
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12'h300: if (csr_we_int) irq_enable_n = csr_wdata_int[0];
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12'h300: if (csr_we_int) mstatus_n = csr_wdata_int[0];
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// mepc: exception program counter
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12'h341: if (csr_we_int) mepc_n = csr_wdata_int;
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@ -194,7 +197,24 @@ module riscv_cs_registers
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12'h7B4: if (csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b1; end
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12'h7B5: if (csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b1; end
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12'h7B6: if (csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b1; end
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// mestatus: machine exception status
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12'h7C0: if (csr_we_int) mestatus_n = csr_wdata_int[0];
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endcase
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// exception controller gets priority over other writes
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if (exc_save_i) begin
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mepc_n = curr_pc_id_i;
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mestatus_n = mstatus_q;
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mstatus_n = 1'b0;
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end
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if (save_exc_cause_i)
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exc_cause_n = exc_cause_i;
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if (exc_restore_i) begin
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mstatus_n = mestatus_q;
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end
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end
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assign hwlp_data_o = csr_wdata_int;
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@ -231,8 +251,8 @@ module riscv_cs_registers
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// directly output some registers
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assign irq_enable_o = irq_enable;
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assign epcr_o = mepc_q;
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assign irq_enable_o = mstatus_q[0];
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assign mepc_o = mepc_q;
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// actual registers
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@ -240,25 +260,20 @@ module riscv_cs_registers
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begin
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if (rst_n == 1'b0)
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begin
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irq_enable <= 1'b0;
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mstatus_q <= '0;
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mepc_q <= '0;
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mestatus_q <= '0;
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exc_cause <= '0;
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end
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else
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begin
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// update CSRs
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irq_enable <= irq_enable_n;
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mstatus_q <= mstatus_n;
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// exception controller gets priority over other writes
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if (save_pc_id_i == 1'b1)
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mepc_q <= curr_pc_id_i;
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else
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mepc_q <= mepc_n;
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mepc_q <= mepc_n;
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mestatus_q <= mestatus_n;
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if (save_exc_cause_i)
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exc_cause <= exc_cause_i;
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else
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exc_cause <= exc_cause_n;
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exc_cause <= exc_cause_n;
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end
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end
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@ -18,9 +18,10 @@ as possible and avoid any overhead that we do not explicitely need.
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00 & 11 & 01 & 000001 & 0x341 & MEPC & R/W & Machine exception program counter \\ \hline
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00 & 11 & 01 & 000010 & 0x342 & MCAUSE & R/W & Machine trap cause \\ \hline
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01 & 11 & 00 & 0XXXXX & 0x780 - 0x79F & PCCRs & R/W & Performance Counter Counter Registers \\ \hline
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01 & 11 & 10 & 200000 & 0x7A0 & PCER & R/W & Performance Counter Enable Register \\ \hline
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01 & 11 & 10 & 100000 & 0x7A0 & PCER & R/W & Performance Counter Enable Register \\ \hline
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01 & 11 & 10 & 100001 & 0x7A1 & PCMR & R/W & Performance Counter Mode Register \\ \hline
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01 & 11 & 10 & 110XXX & 0x7B0 - 0x7B6 & HWLP & R/W & Hardware Loop Registers \\ \hline
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01 & 11 & 10 & 111000 & 0x7C0 & MESTATUS & R/W & Machine exception Status Register \\ \hline
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11 & 11 & 00 & 000000 & 0xF00 & MCPUID & R & CPU description \\ \hline
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11 & 11 & 00 & 000001 & 0xF01 & MIMPID & R & Vendor ID and version number \\ \hline
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11 & 11 & 00 & 010000 & 0xF10 & MHARTID & R & Hardware Thread ID \\ \bottomrule
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@ -41,6 +42,28 @@ as possible and avoid any overhead that we do not explicitely need.
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}
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Note that \signal{PRV[1:0]} is statically \signal{2'b11} and cannot be altered (read-only).
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When en exception is encountered, \signal{Interrupt Enable} will be set to
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\signal{1'b0}. When the \signal{eret} instruction is executed, the original
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value of \signal{Interrupt Enable} will be restored, as \signal{MESTATUS} will
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replace \signal{MSTATUS}.
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If you want to enable interrupt handling in your exception hanlder, set the
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\signal{Interrupt Enable} to \signal{1'b1} inside your handler code.
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\subsection{MESTATUS}
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\csrDesc{0x7C0}{0x0000\_0006}{MESTATUS}{
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\begin{bytefield}[endianness=big,bitheight=60pt]{32}
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\bitheader{31,2,1,0} \\
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\bitbox{29}{ Unused }
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\bitbox{2}{\rotatebox{90}{\tiny PRV[1:0] }}
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\bitbox{1}{\rotatebox{90}{\tiny Interrupt Enable }}
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\end{bytefield}
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}
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Note that \signal{PRV[1:0]} is statically \signal{2'b11} and cannot be altered (read-only).
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When an exception is encountered, the current value of \signal{MSTATUS} is saved
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in \signal{MESTATUS}. When an \instr{eret} instruction is executed, the value
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from \signal{MESTATUS} replaces the \signal{MSTATUS} register.
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\subsection{MEPC}
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@ -52,9 +75,9 @@ Note that \signal{PRV[1:0]} is statically \signal{2'b11} and cannot be altered (
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}
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When an exception is encountered, the current program counter is saved in
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\signal{mepc} and the core jumps to the exception address.
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When an \instr{eret} instruction is executed, the value from \signal{mepc}
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replaces the current program counter.
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\signal{MEPC}, and the core jumps to the exception address. When an \instr{eret}
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instruction is executed, the value from \signal{MEPC} replaces the current
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program counter.
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\subsection{MCAUSE}
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\csrDesc{0x341}{0x0000\_0000}{MCAUSE}{
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|
|
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@ -29,7 +29,15 @@ exception/interrupt.
|
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interrupt lines. Interrupts can only be enabled/disabled on a global basis and
|
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not individually. It is assumed that there is an event/interrupt controller
|
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outside of the core that performs masking and buffering of the interrupt lines.
|
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The global interrupt enable is done via the CSR register \signal{mstatus}.
|
||||
The global interrupt enable is done via the CSR register \signal{MSTATUS}.
|
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|
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If multiple interrupts arrive in the same cycle, the interrupt with the lowest
|
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number will be executed first. As soon as IRQs are re-enabled, either after an
|
||||
\signal{eret} or an explicit enable, the interrupt with lowest number will be
|
||||
executed.
|
||||
This means that it is important to clear the interrupt line before re-enabling
|
||||
interrupts, as otherwise the same interrupt handler could be called over and
|
||||
over again.
|
||||
|
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\section{Exceptions}
|
||||
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||||
|
|
@ -38,16 +46,21 @@ exceptions and ecall instruction exceptions can not be disabled and are always
|
|||
active.
|
||||
|
||||
The illegal instruction exception and the load and store invalid memory access
|
||||
exceptions are precise exceptions, i.e. the value of \signal{mepc} will be the
|
||||
exceptions are precise exceptions, i.e. the value of \signal{MEPC} will be the
|
||||
instruction address that caused it.
|
||||
|
||||
\section{Handling}
|
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|
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\rvcore does not support nested interrupt/exception handling. Exceptions inside
|
||||
interrupt/exception handlers are ignored and thus a user must ensure that such
|
||||
a situation does not happen, as otherwise the behaviour is undefined.
|
||||
\rvcore does support nested interrupt/exception handling. Exceptions inside
|
||||
interrupt/exception handlers cause another exception, thus exceptions during the
|
||||
critical part of your exception handlers, i.e. before having saved the
|
||||
\signal{MEPC} and \signal{MESTATUS} registers, will cause those register to be
|
||||
overwritten.
|
||||
Interrupts during interrupt/exception handlers are disabled by default, but can
|
||||
be explicitely enabled if desired.
|
||||
|
||||
Upon executing an \instr{eret} instruction, the core jumps to the program
|
||||
counter saved in the CSR register \signal{mepc}. When entering an
|
||||
interrupt/exception handler, the core sets \signal{mepc} to the current program
|
||||
counter.
|
||||
counter saved in the CSR register \signal{MEPC} and restores the value of
|
||||
register \signal{MESTATUS} to \signal{MSTATUS}. When entering an
|
||||
interrupt/exception handler, the core sets \signal{MEPC} to the current program
|
||||
counter and saves the current value of \signal{MSTATUS} in \signal{MESTATUS}.
|
||||
|
|
|
|||
|
|
@ -13,6 +13,9 @@ the loop body is executed. RI5CY contains two hardware loop register sets, each
|
|||
of them can store these three values.
|
||||
If the end address of the two hardware loops is identical, loop 0 has higher
|
||||
priority and only the loop counter for hardware loop 0 is decremented.
|
||||
As soon as the counter of loop 0 reaches 1 at an end address, meaning it is
|
||||
decremented to 0 now, loop 1 gets active too. In this case, both counters will
|
||||
be decremented and the core jumps to the start of loop 1.
|
||||
|
||||
The instructions described below are used to setup the hardware loop registers.
|
||||
Note that the minimum loop size is two instructions.
|
||||
|
|
|
|||
44
docs/datasheet/content/pipeline.tex
Normal file
44
docs/datasheet/content/pipeline.tex
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
\chapter{Pipeline}
|
||||
\label{chap:pipeline}
|
||||
|
||||
\rvcore has a fully independent pipeline, meaning that whenever possible data
|
||||
will propagate through the pipeline and therefor does not suffer from any
|
||||
unneeded stalls.
|
||||
|
||||
The pipeline design is easily extendable to incorporate out-of-order
|
||||
completion. E.g. it would be possible to complete an instruction that only
|
||||
needs the EX stage before the WB stage, that is currently blocked waiting for
|
||||
an rvalid, is ready.
|
||||
Currently this is not done in \rvcore, but might be added in the future.
|
||||
|
||||
Figure~\ref{fig:pipeline} shows the control signals relevant for the pipeline
|
||||
operation. Running from right to left are the main control signals, the
|
||||
\signal{ready} signals of each pipeline stage.
|
||||
Each pipeline stage has two control inputs: an enable and a clear. The enable
|
||||
activates the pipeline stage and the core moves forward by one instruction. The
|
||||
clear removes the instruction from the pipeline stage as it is completed.
|
||||
At every pipeline stage, when the \signal{ready} coming from the stage to the
|
||||
right is high, but the valid signal of the stage is low, the stage is cleared.
|
||||
If the valid signal is high, it is enabled.
|
||||
|
||||
Going from right to left every stage is independent, no stage depends on the
|
||||
stage on its left. Going from left to right every stage depends on its right
|
||||
neighbor and can only continue when it is ready.
|
||||
This means that in addition that a single stage has to be ready, also the stage
|
||||
on its right has to be ready to move on.
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[width=0.9\textwidth]{./figures/pipeline}
|
||||
\caption{\rvcore Pipeline.}
|
||||
\label{fig:pipeline}
|
||||
\end{figure}
|
||||
|
||||
|
||||
|
||||
\begin{boxnote}
|
||||
In contrast to \orion there is no global stall controller any more, instead
|
||||
every stage manages its own dependencies. The main controller of \rvcore is now
|
||||
only responsible for control flow operations, i.e. flushing the pipe, branches,
|
||||
jumps and exceptions.
|
||||
\end{boxnote}
|
||||
|
|
@ -37,6 +37,7 @@
|
|||
\input{./content/mac.tex}
|
||||
\input{./content/aluext.tex}
|
||||
\input{./content/hwloop.tex}
|
||||
\input{./content/pipeline.tex}
|
||||
\input{./content/rf.tex}
|
||||
\input{./content/csr.tex}
|
||||
\input{./content/perfcounters.tex}
|
||||
|
|
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oval('#A8322D','',832,492,840,500,0,2,1,288653,0,0,0,0,0,'2',0,[
|
||||
]).
|
||||
group([
|
||||
arc('#A8322D','',0,2,1,0,840,472,856,488,856,472,856,504,1,32,32,5760,-11520,288656,0,0,10,4,0,0,0,'2','10','4',0,[
|
||||
]),
|
||||
poly('#A8322D','',4,[
|
||||
856,472,840,472,840,504,856,504],0,2,1,288655,0,0,0,0,0,0,0,'2',0,0,
|
||||
"0","",[
|
||||
0,10,4,0,'10','4','0'],[0,10,4,0,'10','4','0'],[
|
||||
])
|
||||
],
|
||||
288654,0,0,[
|
||||
]).
|
||||
poly('#A8322D','',3,[
|
||||
808,576,808,480,840,480],0,2,1,288657,0,0,0,0,0,0,0,'2',0,0,
|
||||
"0","",[
|
||||
0,10,4,0,'10','4','0'],[0,10,4,0,'10','4','0'],[
|
||||
]).
|
||||
poly('#A8322D','',2,[
|
||||
872,488,888,488],0,2,1,288658,0,0,0,0,0,0,0,'2',0,0,
|
||||
"0","",[
|
||||
0,10,4,0,'10','4','0'],[0,10,4,0,'10','4','0'],[
|
||||
]).
|
||||
poly('#3C5A0F','',4,[
|
||||
864,520,824,520,824,496,832,496],0,2,1,288668,0,0,0,0,0,0,0,'2',0,0,
|
||||
"0","",[
|
||||
0,10,4,0,'10','4','0'],[0,10,4,0,'10','4','0'],[
|
||||
]).
|
||||
oval('#A8322D','',232,492,240,500,0,2,1,288675,0,0,0,0,0,'2',0,[
|
||||
]).
|
||||
group([
|
||||
arc('#A8322D','',0,2,1,0,240,472,256,488,256,472,256,504,1,32,32,5760,-11520,288678,0,0,10,4,0,0,0,'2','10','4',0,[
|
||||
]),
|
||||
poly('#A8322D','',4,[
|
||||
256,472,240,472,240,504,256,504],0,2,1,288677,0,0,0,0,0,0,0,'2',0,0,
|
||||
"0","",[
|
||||
0,10,4,0,'10','4','0'],[0,10,4,0,'10','4','0'],[
|
||||
])
|
||||
],
|
||||
288676,0,0,[
|
||||
]).
|
||||
poly('#A8322D','',3,[
|
||||
208,576,208,480,240,480],0,2,1,288679,0,0,0,0,0,0,0,'2',0,0,
|
||||
"0","",[
|
||||
0,10,4,0,'10','4','0'],[0,10,4,0,'10','4','0'],[
|
||||
]).
|
||||
poly('#A8322D','',2,[
|
||||
272,488,288,488],0,2,1,288680,0,0,0,0,0,0,0,'2',0,0,
|
||||
"0","",[
|
||||
0,10,4,0,'10','4','0'],[0,10,4,0,'10','4','0'],[
|
||||
]).
|
||||
poly('#3C5A0F','',4,[
|
||||
256,520,224,520,224,496,232,496],0,2,1,288682,0,0,0,0,0,0,0,'2',0,0,
|
||||
"0","",[
|
||||
0,10,4,0,'10','4','0'],[0,10,4,0,'10','4','0'],[
|
||||
]).
|
||||
text('black',296,476,1,1,1,12,20,288685,16,4,0,0,0,0,-65534,12,20,0,0,"",0,0,0,0,492,'',[
|
||||
minilines(12,20,0,0,1,0,0,[
|
||||
mini_line(12,16,4,0,0,0,[
|
||||
str_block(0,12,16,4,0,-1,0,0,0,[
|
||||
str_seg('black','Helvetica-Bold',1,97920,12,16,4,0,-1,0,0,0,0,0,
|
||||
"C")])
|
||||
])
|
||||
])]).
|
||||
text('black',896,476,1,1,1,12,20,288687,16,4,0,0,0,0,-65534,12,20,0,0,"",0,0,0,0,492,'',[
|
||||
minilines(12,20,0,0,1,0,0,[
|
||||
mini_line(12,16,4,0,0,0,[
|
||||
str_block(0,12,16,4,0,-1,0,0,0,[
|
||||
str_seg('black','Helvetica-Bold',1,97920,12,16,4,0,-1,0,0,0,0,0,
|
||||
"C")])
|
||||
])
|
||||
])]).
|
||||
|
|
@ -55,6 +55,8 @@
|
|||
|
||||
\usepackage{enumitem}
|
||||
|
||||
\usepackage{tcolorbox}
|
||||
|
||||
\usepackage{pdflscape}
|
||||
|
||||
|
||||
|
|
@ -115,3 +117,10 @@
|
|||
\textbf{Operation:} \texttt{#2}%
|
||||
}
|
||||
|
||||
\newenvironment{boxnote}%
|
||||
{%
|
||||
\begin{tcolorbox}[colback=red!5!white,colframe=red!75!black,title=Note]%
|
||||
}%
|
||||
{%
|
||||
\end{tcolorbox}%
|
||||
}%
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ module riscv_exc_controller
|
|||
);
|
||||
|
||||
|
||||
enum logic [1:0] { IDLE, WAIT_CONTROLLER, IN_ISR } exc_ctrl_cs, exc_ctrl_ns;
|
||||
enum logic [0:0] { IDLE, WAIT_CONTROLLER } exc_ctrl_cs, exc_ctrl_ns;
|
||||
|
||||
logic req_int;
|
||||
logic [1:0] pc_mux_int, pc_mux_int_q;
|
||||
|
|
@ -173,7 +173,7 @@ module riscv_exc_controller
|
|||
|
||||
if (ack_i) begin
|
||||
save_cause_o = 1'b1;
|
||||
exc_ctrl_ns = IN_ISR;
|
||||
exc_ctrl_ns = IDLE;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -184,16 +184,10 @@ module riscv_exc_controller
|
|||
|
||||
if (ack_i) begin
|
||||
save_cause_o = 1'b1;
|
||||
exc_ctrl_ns = IN_ISR;
|
||||
exc_ctrl_ns = IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
IN_ISR:
|
||||
begin
|
||||
if (eret_insn_i)
|
||||
exc_ctrl_ns = IDLE;
|
||||
end
|
||||
|
||||
default:
|
||||
begin
|
||||
exc_ctrl_ns = IDLE;
|
||||
|
|
|
|||
|
|
@ -140,7 +140,8 @@ module riscv_id_stage
|
|||
output logic [5:0] exc_cause_o,
|
||||
output logic save_exc_cause_o,
|
||||
|
||||
output logic save_pc_id_o,
|
||||
output logic exc_save_id_o,
|
||||
output logic exc_restore_id_o,
|
||||
|
||||
input logic lsu_load_err_i,
|
||||
input logic lsu_store_err_i,
|
||||
|
|
@ -714,7 +715,8 @@ module riscv_id_stage
|
|||
.exc_ack_o ( exc_ack ),
|
||||
.trap_hit_i ( trap_hit ),
|
||||
|
||||
.save_pc_id_o ( save_pc_id_o ),
|
||||
.exc_save_id_o ( exc_save_id_o ),
|
||||
.exc_restore_id_o ( exc_restore_id_o ),
|
||||
|
||||
// Debug Unit Signals
|
||||
.dbg_stall_i ( dbg_stall_i ),
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
// no traces for synthesis, they are not synthesizable
|
||||
`ifndef SYNTHESIS
|
||||
`define TRACE_EXECUTION
|
||||
//`define SIMCHECKER
|
||||
`endif
|
||||
|
||||
|
||||
|
|
|
|||
132
riscv_core.sv
132
riscv_core.sv
|
|
@ -190,11 +190,12 @@ module riscv_core
|
|||
|
||||
// Interrupts
|
||||
logic irq_enable;
|
||||
logic [31:0] epcr;
|
||||
logic [31:0] mepc;
|
||||
|
||||
logic [5:0] exc_cause;
|
||||
logic save_exc_cause;
|
||||
logic save_pc_id;
|
||||
logic exc_save_id;
|
||||
logic exc_restore_id;
|
||||
|
||||
|
||||
// Hardware loop controller signals
|
||||
|
|
@ -280,7 +281,7 @@ module riscv_core
|
|||
// control signals
|
||||
.clear_instr_valid_i ( clear_instr_valid ),
|
||||
.pc_set_i ( pc_set ),
|
||||
.exception_pc_reg_i ( epcr ), // exception return address
|
||||
.exception_pc_reg_i ( mepc ), // exception return address
|
||||
.pc_mux_i ( pc_mux_id ), // sel for pc multiplexer
|
||||
.exc_pc_mux_i ( exc_pc_mux_id ),
|
||||
.exc_vec_pc_mux_i ( exc_vec_pc_mux_id ),
|
||||
|
|
@ -425,7 +426,8 @@ module riscv_core
|
|||
.irq_enable_i ( irq_enable ), // global interrupt enable
|
||||
.exc_cause_o ( exc_cause ),
|
||||
.save_exc_cause_o ( save_exc_cause ),
|
||||
.save_pc_id_o ( save_pc_id ), // control signal to save pc
|
||||
.exc_save_id_o ( exc_save_id ), // control signal to save pc
|
||||
.exc_restore_id_o ( exc_restore_id ), // control signal to restore pc
|
||||
.lsu_load_err_i ( lsu_load_err ),
|
||||
.lsu_store_err_i ( lsu_store_err ),
|
||||
|
||||
|
|
@ -611,10 +613,11 @@ module riscv_core
|
|||
|
||||
// Interrupt related control signals
|
||||
.irq_enable_o ( irq_enable ),
|
||||
.epcr_o ( epcr ),
|
||||
.mepc_o ( mepc ),
|
||||
|
||||
.curr_pc_id_i ( current_pc_id ), // from IF stage
|
||||
.save_pc_id_i ( save_pc_id ),
|
||||
.exc_save_i ( exc_save_id ),
|
||||
.exc_restore_i ( exc_restore_id ),
|
||||
|
||||
.exc_cause_i ( exc_cause ),
|
||||
.save_exc_cause_i ( save_exc_cause ),
|
||||
|
|
@ -715,47 +718,98 @@ module riscv_core
|
|||
`ifdef TRACE_EXECUTION
|
||||
riscv_tracer riscv_tracer_i
|
||||
(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
|
||||
.core_id ( core_id_i ),
|
||||
.cluster_id ( cluster_id_i ),
|
||||
.fetch_enable ( fetch_enable_i ),
|
||||
.core_id ( core_id_i ),
|
||||
.cluster_id ( cluster_id_i ),
|
||||
|
||||
.pc ( id_stage_i.current_pc_id_i ),
|
||||
.instr ( id_stage_i.instr ),
|
||||
.compressed ( id_stage_i.is_compressed_i ),
|
||||
.id_valid ( id_stage_i.id_valid_o ),
|
||||
.is_decoding ( id_stage_i.is_decoding_o ),
|
||||
.pipe_flush ( id_stage_i.controller_i.pipe_flush_i ),
|
||||
.pc ( id_stage_i.current_pc_id_i ),
|
||||
.instr ( id_stage_i.instr ),
|
||||
.compressed ( id_stage_i.is_compressed_i ),
|
||||
.id_valid ( id_stage_i.id_valid_o ),
|
||||
.is_decoding ( id_stage_i.is_decoding_o ),
|
||||
.pipe_flush ( id_stage_i.controller_i.pipe_flush_i ),
|
||||
|
||||
.rs1_value ( id_stage_i.operand_a_fw_id ),
|
||||
.rs2_value ( id_stage_i.operand_b_fw_id ),
|
||||
.rs3_value ( id_stage_i.alu_operand_c ),
|
||||
.rs1_value ( id_stage_i.operand_a_fw_id ),
|
||||
.rs2_value ( id_stage_i.operand_b_fw_id ),
|
||||
.rs3_value ( id_stage_i.alu_operand_c ),
|
||||
|
||||
.ex_valid ( ex_valid ),
|
||||
.ex_reg_addr ( regfile_alu_waddr_fw ),
|
||||
.ex_reg_we ( regfile_alu_we_fw ),
|
||||
.ex_reg_wdata ( regfile_alu_wdata_fw ),
|
||||
.ex_valid ( ex_valid ),
|
||||
.ex_reg_addr ( regfile_alu_waddr_fw ),
|
||||
.ex_reg_we ( regfile_alu_we_fw ),
|
||||
.ex_reg_wdata ( regfile_alu_wdata_fw ),
|
||||
|
||||
.ex_data_addr ( data_addr_o ),
|
||||
.ex_data_req ( data_req_o ),
|
||||
.ex_data_gnt ( data_gnt_i ),
|
||||
.ex_data_we ( data_we_o ),
|
||||
.ex_data_wdata ( data_wdata_o ),
|
||||
.ex_data_addr ( data_addr_o ),
|
||||
.ex_data_req ( data_req_o ),
|
||||
.ex_data_gnt ( data_gnt_i ),
|
||||
.ex_data_we ( data_we_o ),
|
||||
.ex_data_wdata ( data_wdata_o ),
|
||||
|
||||
.wb_valid ( wb_valid ),
|
||||
.wb_reg_addr ( regfile_waddr_fw_wb_o ),
|
||||
.wb_reg_we ( regfile_we_wb ),
|
||||
.wb_reg_wdata ( regfile_wdata ),
|
||||
.wb_valid ( wb_valid ),
|
||||
.wb_reg_addr ( regfile_waddr_fw_wb_o ),
|
||||
.wb_reg_we ( regfile_we_wb ),
|
||||
.wb_reg_wdata ( regfile_wdata ),
|
||||
|
||||
.imm_u_type ( id_stage_i.imm_u_type ),
|
||||
.imm_uj_type ( id_stage_i.imm_uj_type ),
|
||||
.imm_i_type ( id_stage_i.imm_i_type ),
|
||||
.imm_iz_type ( id_stage_i.imm_iz_type[11:0] ),
|
||||
.imm_z_type ( id_stage_i.imm_z_type ),
|
||||
.imm_s_type ( id_stage_i.imm_s_type ),
|
||||
.imm_sb_type ( id_stage_i.imm_sb_type )
|
||||
.imm_u_type ( id_stage_i.imm_u_type ),
|
||||
.imm_uj_type ( id_stage_i.imm_uj_type ),
|
||||
.imm_i_type ( id_stage_i.imm_i_type ),
|
||||
.imm_iz_type ( id_stage_i.imm_iz_type[11:0] ),
|
||||
.imm_z_type ( id_stage_i.imm_z_type ),
|
||||
.imm_s_type ( id_stage_i.imm_s_type ),
|
||||
.imm_sb_type ( id_stage_i.imm_sb_type )
|
||||
);
|
||||
`endif
|
||||
|
||||
`ifdef SIMCHECKER
|
||||
logic is_interrupt;
|
||||
assign is_interrupt = (pc_mux_id == `PC_EXCEPTION) && (exc_pc_mux_id == `EXC_PC_IRQ);
|
||||
|
||||
riscv_simchecker riscv_simchecker_i
|
||||
(
|
||||
.clk ( clk ),
|
||||
.rst_n ( rst_n ),
|
||||
|
||||
.fetch_enable ( fetch_enable_i ),
|
||||
.boot_addr ( boot_addr_i ),
|
||||
.core_id ( core_id_i ),
|
||||
.cluster_id ( cluster_id_i ),
|
||||
|
||||
.instr_compressed ( if_stage_i.fetch_rdata[15:0] ),
|
||||
.pc_set ( pc_set ),
|
||||
.if_valid ( if_valid ),
|
||||
|
||||
.pc ( id_stage_i.current_pc_id_i ),
|
||||
.instr ( id_stage_i.instr ),
|
||||
.is_compressed ( is_compressed_id ),
|
||||
.id_valid ( id_stage_i.id_valid_o ),
|
||||
.is_decoding ( id_stage_i.is_decoding_o ),
|
||||
.is_illegal ( id_stage_i.illegal_insn_dec ),
|
||||
.is_interrupt ( is_interrupt ),
|
||||
.irq_no ( exc_vec_pc_mux_id ),
|
||||
.pipe_flush ( id_stage_i.controller_i.pipe_flush_i ),
|
||||
|
||||
.ex_valid ( ex_valid ),
|
||||
.ex_reg_addr ( id_stage_i.registers_i.waddr_b_i ),
|
||||
.ex_reg_we ( id_stage_i.registers_i.we_b_i ),
|
||||
.ex_reg_wdata ( id_stage_i.registers_i.wdata_b_i ),
|
||||
|
||||
.ex_data_addr ( data_addr_o ),
|
||||
.ex_data_req ( data_req_o ),
|
||||
.ex_data_gnt ( data_gnt_i ),
|
||||
.ex_data_we ( data_we_o ),
|
||||
.ex_data_wdata ( data_wdata_o ),
|
||||
|
||||
.lsu_misaligned ( data_misaligned ),
|
||||
|
||||
.wb_valid ( wb_valid ),
|
||||
.wb_reg_addr ( id_stage_i.registers_i.waddr_a_i ),
|
||||
.wb_reg_we ( id_stage_i.registers_i.we_a_i ),
|
||||
.wb_reg_wdata ( id_stage_i.registers_i.wdata_a_i ),
|
||||
|
||||
.wb_data_rvalid ( data_rvalid_i ),
|
||||
.wb_data_rdata ( data_rdata_i )
|
||||
);
|
||||
`endif
|
||||
|
||||
|
|
|
|||
309
riscv_simchecker.sv
Normal file
309
riscv_simchecker.sv
Normal file
|
|
@ -0,0 +1,309 @@
|
|||
// Copyright 2015 ETH Zurich and University of Bologna.
|
||||
// Copyright and related rights are licensed under the Solderpad Hardware
|
||||
// License, Version 0.51 (the “License”); you may not use this file except in
|
||||
// compliance with the License. You may obtain a copy of the License at
|
||||
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
|
||||
// or agreed to in writing, software, hardware and materials distributed under
|
||||
// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
|
||||
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
|
||||
// specific language governing permissions and limitations under the License.
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Engineer: Andreas Traber - atraber@iis.ee.ethz.ch //
|
||||
// //
|
||||
// Additional contributions by: //
|
||||
// //
|
||||
// Design Name: RISC-V Tracer //
|
||||
// Project Name: RI5CY //
|
||||
// Language: SystemVerilog //
|
||||
// //
|
||||
// Description: Compares the executed instructions with a golden model //
|
||||
// //
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
import "DPI-C" function chandle riscv_checker_init(input int boot_addr, input int core_id, input int cluster_id);
|
||||
import "DPI-C" function int riscv_checker_step(input chandle cpu, input longint simtime, input int cycle, input logic [31:0] pc, input logic [31:0] instr);
|
||||
import "DPI-C" function void riscv_checker_irq(input chandle cpu, input int irq, input int irq_no);
|
||||
import "DPI-C" function void riscv_checker_mem_access(input chandle cpu, input int we, input logic [31:0] addr, input logic [31:0] data);
|
||||
import "DPI-C" function void riscv_checker_reg_access(input chandle cpu, input logic [31:0] addr, input logic [31:0] data);
|
||||
|
||||
module riscv_simchecker
|
||||
(
|
||||
// Clock and Reset
|
||||
input logic clk,
|
||||
input logic rst_n,
|
||||
|
||||
input logic fetch_enable,
|
||||
input logic [31:0] boot_addr,
|
||||
input logic [4:0] core_id,
|
||||
input logic [4:0] cluster_id,
|
||||
|
||||
input logic [15:0] instr_compressed,
|
||||
input logic if_valid,
|
||||
input logic pc_set,
|
||||
|
||||
input logic [31:0] pc,
|
||||
input logic [31:0] instr,
|
||||
input logic is_compressed,
|
||||
input logic id_valid,
|
||||
input logic is_decoding,
|
||||
input logic is_illegal,
|
||||
input logic is_interrupt,
|
||||
input logic [4:0] irq_no,
|
||||
input logic pipe_flush,
|
||||
|
||||
input logic ex_valid,
|
||||
input logic [ 4:0] ex_reg_addr,
|
||||
input logic ex_reg_we,
|
||||
input logic [31:0] ex_reg_wdata,
|
||||
|
||||
input logic ex_data_req,
|
||||
input logic ex_data_gnt,
|
||||
input logic ex_data_we,
|
||||
input logic [31:0] ex_data_addr,
|
||||
input logic [31:0] ex_data_wdata,
|
||||
|
||||
input logic lsu_misaligned,
|
||||
|
||||
input logic wb_valid,
|
||||
input logic [ 4:0] wb_reg_addr,
|
||||
input logic wb_reg_we,
|
||||
input logic [31:0] wb_reg_wdata,
|
||||
|
||||
input logic wb_data_rvalid,
|
||||
input logic [31:0] wb_data_rdata
|
||||
);
|
||||
|
||||
// DPI stuff
|
||||
chandle dpi_simdata;
|
||||
|
||||
// SV-only stuff
|
||||
typedef struct {
|
||||
logic [ 4:0] addr;
|
||||
logic [31:0] value;
|
||||
} reg_t;
|
||||
|
||||
typedef struct {
|
||||
logic [31:0] addr;
|
||||
logic we;
|
||||
logic [ 3:0] be;
|
||||
logic [31:0] wdata;
|
||||
logic [31:0] rdata;
|
||||
} mem_acc_t;
|
||||
|
||||
class instr_trace_t;
|
||||
time simtime;
|
||||
int cycles;
|
||||
logic [31:0] pc;
|
||||
logic [31:0] instr;
|
||||
logic irq;
|
||||
logic [ 4:0] irq_no;
|
||||
reg_t regs_write[$];
|
||||
mem_acc_t mem_access[$];
|
||||
|
||||
function new ();
|
||||
irq = 1'b0;
|
||||
regs_write = {};
|
||||
mem_access = {};
|
||||
endfunction
|
||||
endclass
|
||||
|
||||
mailbox rdata_stack = new (4);
|
||||
integer rdata_writes = 0;
|
||||
|
||||
integer cycles;
|
||||
|
||||
logic [15:0] instr_compressed_id;
|
||||
logic is_irq_if, is_irq_id;
|
||||
logic [ 4:0] irq_no_id, irq_no_if;
|
||||
|
||||
mailbox instr_ex = new (2);
|
||||
mailbox instr_wb = new (2);
|
||||
|
||||
// simchecker initialization
|
||||
initial
|
||||
begin
|
||||
wait(rst_n == 1'b1);
|
||||
wait(fetch_enable == 1'b1);
|
||||
|
||||
dpi_simdata = riscv_checker_init(boot_addr, core_id, cluster_id);
|
||||
end
|
||||
|
||||
// virtual ID/EX pipeline
|
||||
initial
|
||||
begin
|
||||
instr_trace_t trace;
|
||||
mem_acc_t mem_acc;
|
||||
reg_t reg_write;
|
||||
|
||||
while(1) begin
|
||||
instr_ex.get(trace);
|
||||
|
||||
// wait until we are going to the next stage
|
||||
do begin
|
||||
@(negedge clk);
|
||||
|
||||
reg_write.addr = ex_reg_addr;
|
||||
reg_write.value = ex_reg_wdata;
|
||||
|
||||
if (ex_reg_we)
|
||||
trace.regs_write.push_back(reg_write);
|
||||
|
||||
// look for data accesses and log them
|
||||
if (ex_data_req && ex_data_gnt) begin
|
||||
mem_acc.addr = ex_data_addr;
|
||||
mem_acc.we = ex_data_we;
|
||||
|
||||
if (mem_acc.we)
|
||||
mem_acc.wdata = ex_data_wdata;
|
||||
else
|
||||
mem_acc.wdata = 'x;
|
||||
|
||||
trace.mem_access.push_back(mem_acc);
|
||||
end
|
||||
end while (!ex_valid || lsu_misaligned);
|
||||
|
||||
instr_wb.put(trace);
|
||||
end
|
||||
end
|
||||
|
||||
// virtual EX/WB pipeline
|
||||
initial
|
||||
begin
|
||||
instr_trace_t trace;
|
||||
reg_t reg_write;
|
||||
logic [31:0] tmp_discard;
|
||||
|
||||
while(1) begin
|
||||
instr_wb.get(trace);
|
||||
|
||||
// wait until we are going to the next stage
|
||||
do begin
|
||||
@(negedge clk);
|
||||
#1;
|
||||
|
||||
// pop rdata from stack when there were pending writes
|
||||
while(rdata_stack.num() > 0 && rdata_writes > 0) begin
|
||||
rdata_writes--;
|
||||
rdata_stack.get(tmp_discard);
|
||||
end
|
||||
|
||||
end while (!wb_valid);
|
||||
|
||||
reg_write.addr = wb_reg_addr;
|
||||
reg_write.value = wb_reg_wdata;
|
||||
|
||||
if (wb_reg_we)
|
||||
trace.regs_write.push_back(reg_write);
|
||||
|
||||
// keep care of rdata
|
||||
foreach(trace.mem_access[i]) begin
|
||||
if (trace.mem_access[i].we) begin
|
||||
// for writes we don't need to wait for the rdata, so if it has
|
||||
// not appeared yet, we count it and remove it later from out
|
||||
// stack
|
||||
rdata_writes++;
|
||||
|
||||
end else begin
|
||||
if (rdata_stack.num() == 0)
|
||||
$warning("rdata stack is empty, but we are waiting for a read");
|
||||
|
||||
rdata_stack.get(trace.mem_access[i].rdata);
|
||||
end
|
||||
end
|
||||
|
||||
// instruction is ready now, all data is inserted
|
||||
foreach(trace.mem_access[i]) begin
|
||||
if (trace.mem_access[i].we)
|
||||
riscv_checker_mem_access(dpi_simdata, trace.mem_access[i].we, trace.mem_access[i].addr, trace.mem_access[i].wdata);
|
||||
else
|
||||
riscv_checker_mem_access(dpi_simdata, trace.mem_access[i].we, trace.mem_access[i].addr, trace.mem_access[i].rdata);
|
||||
end
|
||||
|
||||
foreach(trace.regs_write[i]) begin
|
||||
riscv_checker_reg_access(dpi_simdata, trace.regs_write[i].addr, trace.regs_write[i].value);
|
||||
end
|
||||
|
||||
riscv_checker_irq(dpi_simdata, trace.irq, trace.irq_no);
|
||||
|
||||
if (riscv_checker_step(dpi_simdata, trace.simtime, trace.cycles, trace.pc, trace.instr))
|
||||
$display("%t: Cluster %d, Core %d: Mismatch between simulator and RTL detected", trace.simtime, cluster_id, core_id);
|
||||
end
|
||||
end
|
||||
|
||||
// cycle counter
|
||||
always_ff @(posedge clk, negedge rst_n)
|
||||
begin
|
||||
if (rst_n == 1'b0)
|
||||
cycles = 0;
|
||||
else
|
||||
cycles = cycles + 1;
|
||||
end
|
||||
|
||||
// create rdata stack
|
||||
initial
|
||||
begin
|
||||
while(1) begin
|
||||
@(negedge clk);
|
||||
|
||||
if (wb_data_rvalid) begin
|
||||
rdata_stack.put(wb_data_rdata);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk)
|
||||
begin
|
||||
if (pc_set) begin
|
||||
is_irq_if <= is_interrupt;
|
||||
irq_no_if <= irq_no;
|
||||
end else if (if_valid) begin
|
||||
is_irq_if <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk)
|
||||
begin
|
||||
if (if_valid) begin
|
||||
instr_compressed_id <= instr_compressed;
|
||||
is_irq_id <= is_irq_if;
|
||||
irq_no_id <= irq_no_if;
|
||||
end
|
||||
end
|
||||
|
||||
// log execution
|
||||
initial
|
||||
begin
|
||||
instr_trace_t trace;
|
||||
|
||||
while(1) begin
|
||||
@(negedge clk);
|
||||
|
||||
// - special case for WFI because we don't wait for unstalling there
|
||||
// - special case for illegal instructions, since they will not go through
|
||||
// the pipe
|
||||
if ((id_valid && is_decoding) || pipe_flush || (is_decoding && is_illegal))
|
||||
begin
|
||||
trace = new ();
|
||||
|
||||
trace.simtime = $time;
|
||||
trace.cycles = cycles;
|
||||
trace.pc = pc;
|
||||
|
||||
if (is_compressed)
|
||||
trace.instr = {instr_compressed_id, instr_compressed_id};
|
||||
else
|
||||
trace.instr = instr;
|
||||
|
||||
if (is_irq_id) begin
|
||||
trace.irq = 1'b1;
|
||||
trace.irq_no = irq_no_id;
|
||||
end
|
||||
|
||||
instr_ex.put(trace);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -30,6 +30,7 @@ module riscv_tracer
|
|||
input logic clk,
|
||||
input logic rst_n,
|
||||
|
||||
input logic fetch_enable,
|
||||
input logic [4:0] core_id,
|
||||
input logic [4:0] cluster_id,
|
||||
|
||||
|
|
@ -67,7 +68,6 @@ module riscv_tracer
|
|||
input logic [31:0] imm_z_type,
|
||||
input logic [31:0] imm_s_type,
|
||||
input logic [31:0] imm_sb_type
|
||||
|
||||
);
|
||||
|
||||
integer f;
|
||||
|
|
@ -187,7 +187,7 @@ module riscv_tracer
|
|||
function void printUInstr(input string mnemonic);
|
||||
begin
|
||||
regs_write.push_back({rd, 'x});
|
||||
str = $sformatf("%-16s x%0d, 0x%0h000", mnemonic, rd, imm_u_type[31:12]);
|
||||
str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, {imm_u_type[31:12], 12'h000});
|
||||
end
|
||||
endfunction // printUInstr
|
||||
|
||||
|
|
@ -375,11 +375,13 @@ module riscv_tracer
|
|||
// open/close output file for writing
|
||||
initial
|
||||
begin
|
||||
#1 // delay needed for valid core_id and cluster_id
|
||||
wait(rst_n == 1'b1);
|
||||
wait(fetch_enable == 1'b1);
|
||||
$sformat(fn, "trace_core_%h_%h.log", cluster_id, core_id);
|
||||
$display("[TRACER] Output filename is: %s", fn);
|
||||
f = $fopen(fn, "w");
|
||||
$fwrite(f, "%20s\t%6s\t%10s\t%10s\t \t%s\n", "Time", "Cycles", "PC", "Instr", "Mnemonic");
|
||||
$fwrite(f, " Time Cycles PC Instr Mnemonic\n");
|
||||
|
||||
end
|
||||
|
||||
final
|
||||
|
|
@ -403,7 +405,7 @@ module riscv_tracer
|
|||
|
||||
// wait until we are going to the next stage
|
||||
do begin
|
||||
@(posedge clk);
|
||||
@(negedge clk);
|
||||
|
||||
// replace register written back
|
||||
foreach(trace.regs_write[i])
|
||||
|
|
@ -438,7 +440,7 @@ module riscv_tracer
|
|||
|
||||
// wait until we are going to the next stage
|
||||
do begin
|
||||
@(posedge clk);
|
||||
@(negedge clk);
|
||||
|
||||
// replace register written back
|
||||
foreach(trace.regs_write[i])
|
||||
|
|
@ -451,7 +453,7 @@ module riscv_tracer
|
|||
end
|
||||
|
||||
// log execution
|
||||
always @(posedge clk)
|
||||
always @(negedge clk)
|
||||
begin
|
||||
instr_trace_t trace;
|
||||
|
||||
|
|
@ -502,10 +504,10 @@ module riscv_tracer
|
|||
`INSTR_SRA: trace.printRInstr("sra");
|
||||
`INSTR_OR: trace.printRInstr("or");
|
||||
`INSTR_AND: trace.printRInstr("and");
|
||||
`INSTR_EXTHS: trace.printRInstr("exths");
|
||||
`INSTR_EXTHZ: trace.printRInstr("exthz");
|
||||
`INSTR_EXTBS: trace.printRInstr("extbs");
|
||||
`INSTR_EXTBZ: trace.printRInstr("extbz");
|
||||
`INSTR_EXTHS: trace.printRInstr("p.exths");
|
||||
`INSTR_EXTHZ: trace.printRInstr("p.exthz");
|
||||
`INSTR_EXTBS: trace.printRInstr("p.extbs");
|
||||
`INSTR_EXTBZ: trace.printRInstr("p.extbz");
|
||||
`INSTR_PAVG: trace.printRInstr("p.avg");
|
||||
`INSTR_PAVGU: trace.printRInstr("p.avgu");
|
||||
`INSTR_PSLET: trace.printRInstr("p.slet");
|
||||
|
|
@ -545,7 +547,4 @@ module riscv_tracer
|
|||
end
|
||||
end // always @ (posedge clk)
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue