Fix a nasty L0 buffer bug that happens with hardware loops

This commit is contained in:
Andreas Traber 2016-03-24 17:54:55 +01:00
parent 1f2eef7606
commit aa28fac157

View file

@ -59,7 +59,7 @@ module riscv_prefetch_L0_buffer
logic busy_L0;
enum logic [3:0] { IDLE, BRANCHED,
HWLP_WAIT_GNT, HWLP_GRANTED, HWLP_FETCH_DONE,
HWLP_WAIT_GNT, HWLP_GRANTED, HWLP_GRANTED_WAIT, HWLP_FETCH_DONE,
NOT_VALID, NOT_VALID_GRANTED, NOT_VALID_CROSS, NOT_VALID_CROSS_GRANTED,
VALID, VALID_CROSS, VALID_GRANTED, VALID_FETCH_DONE } CS, NS;
@ -407,15 +407,18 @@ module riscv_prefetch_L0_buffer
use_hwlp = 1'b1;
if (ready_i) begin
addr_n = hwloop_target_i;
if (fetch_valid) begin
is_hwlp_n = 1'b1;
addr_n = hwloop_target_i;
if (hwlp_is_crossword) begin
NS = NOT_VALID_CROSS;
end else begin
NS = VALID;
end
end else begin
NS = HWLP_GRANTED_WAIT;
end
end else begin
if (fetch_valid)
@ -423,6 +426,20 @@ module riscv_prefetch_L0_buffer
end
end
HWLP_GRANTED_WAIT: begin
use_hwlp = 1'b1;
if (fetch_valid) begin
is_hwlp_n = 1'b1;
if (hwlp_is_crossword) begin
NS = NOT_VALID_CROSS;
end else begin
NS = VALID;
end
end
end
HWLP_FETCH_DONE: begin
valid = 1'b1;
use_hwlp = 1'b1;