Use control knobs rather than subclassing in ICache core sequences

This is a bit less verbose than what we had: we can just set the
control knobs in the virtual sequence rather than subclassing
everything.

dv/uvm/icache/dv/env/seq_lib/ibex_icache_passthru_vseq.sv

@@ -7,9 +7,8 @@ class ibex_icache_passthru_vseq extends ibex_icache_base_vseq;
   `uvm_object_utils(ibex_icache_passthru_vseq)
   `uvm_object_new
 
-  // A passthru sequence for the core agent and a basic slave sequence for the memory agent
-  ibex_icache_core_passthru_seq core_seq;
-  ibex_icache_mem_resp_seq      mem_seq;
+  ibex_icache_core_base_seq core_seq;
+  ibex_icache_mem_resp_seq  mem_seq;
 
   task body();
     // Start the core and memory sequences. We use fork/join_any so that we don't wait for the
@@ -17,11 +16,17 @@ class ibex_icache_passthru_vseq extends ibex_icache_base_vseq;
     fork
       begin
         `uvm_create_on(core_seq, p_sequencer.core_sequencer_h)
+
+        // Constrain branch targets and leave the cache disabled.
+        core_seq.constrain_branches = 1'b1;
+        core_seq.force_disable      = 1'b1;
+
         `DV_CHECK_RANDOMIZE_FATAL(core_seq)
         core_seq.start(p_sequencer.core_sequencer_h);
       end
       begin
         `uvm_create_on(mem_seq, p_sequencer.mem_sequencer_h)
+
         // Increase the frequency of seed updates
         mem_seq.gap_between_seeds = 49;
 

dv/uvm/icache/dv/env/seq_lib/ibex_icache_sanity_vseq.sv

@@ -9,9 +9,10 @@ class ibex_icache_sanity_vseq extends ibex_icache_base_vseq;
   `uvm_object_utils(ibex_icache_sanity_vseq)
   `uvm_object_new
 
-  // A sanity sequence for the core agent and a basic slave sequence for the memory agent
-  ibex_icache_core_sanity_seq core_seq;
-  ibex_icache_mem_resp_seq    mem_seq;
+  // An un-specialized base sequence for the core agent and a basic slave sequence for the memory
+  // agent
+  ibex_icache_core_base_seq core_seq;
+  ibex_icache_mem_resp_seq  mem_seq;
 
   task body();
     // Start the core and memory sequences. We use fork/join_any so that we don't wait for the

dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_agent.core

@@ -23,8 +23,6 @@ filesets:
       - ibex_icache_core_monitor.sv: {is_include_file: true}
       - ibex_icache_core_agent.sv: {is_include_file: true}
       - seq_lib/ibex_icache_core_base_seq.sv: {is_include_file: true}
-      - seq_lib/ibex_icache_core_sanity_seq.sv: {is_include_file: true}
-      - seq_lib/ibex_icache_core_passthru_seq.sv: {is_include_file: true}
       - seq_lib/ibex_icache_core_seq_list.sv: {is_include_file: true}
     file_type: systemVerilogSource
 

dv/uvm/icache/dv/ibex_icache_core_agent/seq_lib/ibex_icache_core_base_seq.sv

@@ -12,6 +12,14 @@ class ibex_icache_core_base_seq extends dv_base_seq #(
 
   `uvm_object_new
 
+  // If this is set, any branch target address should be within 64 bytes of base_addr and runs of
+  // instructions should have a maximum length of 100.
+  bit constrain_branches = 1'b0;
+
+  // If this bit is set, we will never enable the cache
+  bit force_disable = 1'b0;
+
+
   // Number of test items (note that a single test item may contain many instruction fetches)
   protected rand int count;
   constraint c_count { count inside {[800:1000]}; }
@@ -24,20 +32,13 @@ class ibex_icache_core_base_seq extends dv_base_seq #(
   // the cache where to fetch from in the first place.
   protected bit force_branch = 1'b1;
 
-  // If this is set, any branch target address should be within 64 bytes of base_addr and runs of
-  // instructions should have a maximum length of 100.
-  protected bit constrain_branches = 1'b0;
-
   // A count of the number of instructions fetched since the last branch. This is only important
   // when constrain_branches is true, in which case we want to ensure that we don't fetch too much
   // in a straight line between branches.
   protected int unsigned insns_since_branch = 0;
 
-  // If this bit is set, we will never enable the cache
-  protected bit force_disable = 1'b0;
-
   virtual task body();
-    `uvm_fatal(`gtn, "Need to override this when you extend from this class!")
+    run_reqs();
   endtask
 
   // Generate and run a single item using class parameters

dv/uvm/icache/dv/ibex_icache_core_agent/seq_lib/ibex_icache_core_passthru_seq.sv

@@ -1,21 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-// Passthru test sequence
-//
-// This is used for the passthru test. We constrain branch targets and leave the cache disabled.
-
-class ibex_icache_core_passthru_seq extends ibex_icache_core_base_seq;
-  `uvm_object_utils(ibex_icache_core_passthru_seq)
-  `uvm_object_new
-
-  task body();
-    // Overrides for base sequence
-    constrain_branches = 1'b1;
-    force_disable = 1'b1;
-
-    run_reqs();
-  endtask
-
-endclass

dv/uvm/icache/dv/ibex_icache_core_agent/seq_lib/ibex_icache_core_sanity_seq.sv

@@ -1,18 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-// Sanity test seq
-//
-// This is unlikely to find many cache hits (since it branches all over the 4GiB address space).
-
-class ibex_icache_core_sanity_seq extends ibex_icache_core_base_seq;
-  `uvm_object_utils(ibex_icache_core_sanity_seq)
-  `uvm_object_new
-
-  task body();
-    // No overrides needed in base sequence
-    run_reqs();
-  endtask
-
-endclass

dv/uvm/icache/dv/ibex_icache_core_agent/seq_lib/ibex_icache_core_seq_list.sv

@@ -3,5 +3,3 @@
 // SPDX-License-Identifier: Apache-2.0
 
 `include "ibex_icache_core_base_seq.sv"
-`include "ibex_icache_core_sanity_seq.sv"
-`include "ibex_icache_core_passthru_seq.sv"