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[style] Format module instantiations in tabular format

Browse source 
The style guide mandates tabular format in port expressions in module
instantiations
(https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#module-instantiation).

The style guide also mandates a two-space indentation for ports and
parameters in module instantiations.

Apply the formatting produced by verible-format to match our style
guide.
This commit is contained in:
Philipp Wagner 2021-07-22 11:23:15 +01:00 • committed by Philipp Wagner
parent 48f11c6733
commit b5011ecec6
7 changed files with 989 additions and 992 deletions
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24
dv/uvm/icache/dv/prim_badbit/prim_badbit_ram_1p.sv
View file

@ -31,20 +31,20 @@ module prim_badbit_ram_1p #(
logic [Width-1:0] sram_rdata;
prim_generic_ram_1p #(
.Width (Width),
.Depth (Depth),
.DataBitsPerMask (DataBitsPerMask),
.MemInitFile (MemInitFile)
.Width (Width),
.Depth (Depth),
.DataBitsPerMask(DataBitsPerMask),
.MemInitFile (MemInitFile)
) u_mem (
.clk_i (clk_i),
.clk_i(clk_i),
.cfg_i ('0),
.req_i (req_i),
.write_i (write_i),
.addr_i (addr_i),
.wdata_i (wdata_i),
.wmask_i (wmask_i),
.rdata_o (sram_rdata)
.cfg_i ('0),
.req_i (req_i),
.write_i(write_i),
.addr_i (addr_i),
.wdata_i(wdata_i),
.wmask_i(wmask_i),
.rdata_o(sram_rdata)
);
// This module doesn't work with Verilator (because of the wired-or). Because we define the

820
rtl/ibex_core.sv
View file

@ -390,90 +390,90 @@ module ibex_core import ibex_pkg::*; #(
//////////////
ibex_if_stage #(
.DmHaltAddr ( DmHaltAddr ),
.DmExceptionAddr ( DmExceptionAddr ),
.DummyInstructions ( DummyInstructions ),
.ICache ( ICache ),
.ICacheECC ( ICacheECC ),
.BusSizeECC ( BusSizeECC ),
.TagSizeECC ( TagSizeECC ),
.LineSizeECC ( LineSizeECC ),
.PCIncrCheck ( PCIncrCheck ),
.ResetAll ( ResetAll ),
.RndCnstLfsrSeed ( RndCnstLfsrSeed ),
.RndCnstLfsrPerm ( RndCnstLfsrPerm ),
.BranchPredictor ( BranchPredictor )
.DmHaltAddr (DmHaltAddr),
.DmExceptionAddr (DmExceptionAddr),
.DummyInstructions(DummyInstructions),
.ICache (ICache),
.ICacheECC (ICacheECC),
.BusSizeECC (BusSizeECC),
.TagSizeECC (TagSizeECC),
.LineSizeECC (LineSizeECC),
.PCIncrCheck (PCIncrCheck),
.ResetAll ( ResetAll ),
.RndCnstLfsrSeed ( RndCnstLfsrSeed ),
.RndCnstLfsrPerm ( RndCnstLfsrPerm ),
.BranchPredictor (BranchPredictor)
) if_stage_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.clk_i (clk_i),
.rst_ni(rst_ni),
.boot_addr_i ( boot_addr_i ),
.req_i ( instr_req_gated ), // instruction request control
.boot_addr_i(boot_addr_i),
.req_i (instr_req_gated), // instruction request control
// instruction cache interface
.instr_req_o ( instr_req_out ),
.instr_addr_o ( instr_addr_o ),
.instr_gnt_i ( instr_gnt_i ),
.instr_rvalid_i ( instr_rvalid_i ),
.instr_rdata_i ( instr_rdata_i ),
.instr_err_i ( instr_err_i ),
.instr_pmp_err_i ( pmp_req_err[PMP_I] ),
// instruction cache interface
.instr_req_o (instr_req_out),
.instr_addr_o (instr_addr_o),
.instr_gnt_i (instr_gnt_i),
.instr_rvalid_i (instr_rvalid_i),
.instr_rdata_i (instr_rdata_i),
.instr_err_i (instr_err_i),
.instr_pmp_err_i(pmp_req_err[PMP_I]),
.ic_tag_req_o ( ic_tag_req_o ),
.ic_tag_write_o ( ic_tag_write_o ),
.ic_tag_addr_o ( ic_tag_addr_o ),
.ic_tag_wdata_o ( ic_tag_wdata_o ),
.ic_tag_rdata_i ( ic_tag_rdata_i ),
.ic_data_req_o ( ic_data_req_o ),
.ic_data_write_o ( ic_data_write_o ),
.ic_data_addr_o ( ic_data_addr_o ),
.ic_data_wdata_o ( ic_data_wdata_o ),
.ic_data_rdata_i ( ic_data_rdata_i ),
.ic_tag_req_o (ic_tag_req_o),
.ic_tag_write_o (ic_tag_write_o),
.ic_tag_addr_o (ic_tag_addr_o),
.ic_tag_wdata_o (ic_tag_wdata_o),
.ic_tag_rdata_i (ic_tag_rdata_i),
.ic_data_req_o (ic_data_req_o),
.ic_data_write_o(ic_data_write_o),
.ic_data_addr_o (ic_data_addr_o),
.ic_data_wdata_o(ic_data_wdata_o),
.ic_data_rdata_i(ic_data_rdata_i),
// outputs to ID stage
.instr_valid_id_o ( instr_valid_id ),
.instr_new_id_o ( instr_new_id ),
.instr_rdata_id_o ( instr_rdata_id ),
.instr_rdata_alu_id_o ( instr_rdata_alu_id ),
.instr_rdata_c_id_o ( instr_rdata_c_id ),
.instr_is_compressed_id_o ( instr_is_compressed_id ),
.instr_bp_taken_o ( instr_bp_taken_id ),
.instr_fetch_err_o ( instr_fetch_err ),
.instr_fetch_err_plus2_o ( instr_fetch_err_plus2 ),
.illegal_c_insn_id_o ( illegal_c_insn_id ),
.dummy_instr_id_o ( dummy_instr_id ),
.pc_if_o ( pc_if ),
.pc_id_o ( pc_id ),
// outputs to ID stage
.instr_valid_id_o (instr_valid_id),
.instr_new_id_o (instr_new_id),
.instr_rdata_id_o (instr_rdata_id),
.instr_rdata_alu_id_o (instr_rdata_alu_id),
.instr_rdata_c_id_o (instr_rdata_c_id),
.instr_is_compressed_id_o(instr_is_compressed_id),
.instr_bp_taken_o (instr_bp_taken_id),
.instr_fetch_err_o (instr_fetch_err),
.instr_fetch_err_plus2_o (instr_fetch_err_plus2),
.illegal_c_insn_id_o (illegal_c_insn_id),
.dummy_instr_id_o (dummy_instr_id),
.pc_if_o (pc_if),
.pc_id_o (pc_id),
// control signals
.instr_valid_clear_i ( instr_valid_clear ),
.pc_set_i ( pc_set ),
.pc_set_spec_i ( pc_set_spec ),
.pc_mux_i ( pc_mux_id ),
.nt_branch_mispredict_i ( nt_branch_mispredict ),
.exc_pc_mux_i ( exc_pc_mux_id ),
.exc_cause ( exc_cause ),
.dummy_instr_en_i ( dummy_instr_en ),
.dummy_instr_mask_i ( dummy_instr_mask ),
.dummy_instr_seed_en_i ( dummy_instr_seed_en ),
.dummy_instr_seed_i ( dummy_instr_seed ),
.icache_enable_i ( icache_enable ),
.icache_inval_i ( icache_inval ),
// control signals
.instr_valid_clear_i (instr_valid_clear),
.pc_set_i (pc_set),
.pc_set_spec_i (pc_set_spec),
.pc_mux_i (pc_mux_id),
.nt_branch_mispredict_i(nt_branch_mispredict),
.exc_pc_mux_i (exc_pc_mux_id),
.exc_cause (exc_cause),
.dummy_instr_en_i (dummy_instr_en),
.dummy_instr_mask_i (dummy_instr_mask),
.dummy_instr_seed_en_i (dummy_instr_seed_en),
.dummy_instr_seed_i (dummy_instr_seed),
.icache_enable_i (icache_enable),
.icache_inval_i (icache_inval),
// branch targets
.branch_target_ex_i ( branch_target_ex ),
// branch targets
.branch_target_ex_i(branch_target_ex),
// CSRs
.csr_mepc_i ( csr_mepc ), // exception return address
.csr_depc_i ( csr_depc ), // debug return address
.csr_mtvec_i ( csr_mtvec ), // trap-vector base address
.csr_mtvec_init_o ( csr_mtvec_init ),
// CSRs
.csr_mepc_i (csr_mepc), // exception return address
.csr_depc_i (csr_depc), // debug return address
.csr_mtvec_i (csr_mtvec), // trap-vector base address
.csr_mtvec_init_o(csr_mtvec_init),
// pipeline stalls
.id_in_ready_i ( id_in_ready ),
// pipeline stalls
.id_in_ready_i(id_in_ready),
.pc_mismatch_alert_o ( pc_mismatch_alert ),
.if_busy_o ( if_busy )
.pc_mismatch_alert_o(pc_mismatch_alert),
.if_busy_o (if_busy)
);
// Core is waiting for the ISide when ID/EX stage is ready for a new instruction but none are
@ -491,207 +491,207 @@ module ibex_core import ibex_pkg::*; #(
//////////////
ibex_id_stage #(
.RV32E ( RV32E ),
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.BranchTargetALU ( BranchTargetALU ),
.DataIndTiming ( DataIndTiming ),
.SpecBranch ( SpecBranch ),
.WritebackStage ( WritebackStage ),
.BranchPredictor ( BranchPredictor )
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU(BranchTargetALU),
.DataIndTiming (DataIndTiming),
.SpecBranch (SpecBranch),
.WritebackStage (WritebackStage),
.BranchPredictor(BranchPredictor)
) id_stage_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.clk_i (clk_i),
.rst_ni(rst_ni),
// Processor Enable
.ctrl_busy_o ( ctrl_busy ),
.illegal_insn_o ( illegal_insn_id ),
// Processor Enable
.ctrl_busy_o (ctrl_busy),
.illegal_insn_o(illegal_insn_id),
// from/to IF-ID pipeline register
.instr_valid_i ( instr_valid_id ),
.instr_rdata_i ( instr_rdata_id ),
.instr_rdata_alu_i ( instr_rdata_alu_id ),
.instr_rdata_c_i ( instr_rdata_c_id ),
.instr_is_compressed_i ( instr_is_compressed_id ),
.instr_bp_taken_i ( instr_bp_taken_id ),
// from/to IF-ID pipeline register
.instr_valid_i (instr_valid_id),
.instr_rdata_i (instr_rdata_id),
.instr_rdata_alu_i (instr_rdata_alu_id),
.instr_rdata_c_i (instr_rdata_c_id),
.instr_is_compressed_i(instr_is_compressed_id),
.instr_bp_taken_i (instr_bp_taken_id),
// Jumps and branches
.branch_decision_i ( branch_decision ),
// Jumps and branches
.branch_decision_i(branch_decision),
// IF and ID control signals
.instr_first_cycle_id_o ( instr_first_cycle_id ),
.instr_valid_clear_o ( instr_valid_clear ),
.id_in_ready_o ( id_in_ready ),
.instr_req_o ( instr_req_int ),
.pc_set_o ( pc_set ),
.pc_set_spec_o ( pc_set_spec ),
.pc_mux_o ( pc_mux_id ),
.nt_branch_mispredict_o ( nt_branch_mispredict ),
.exc_pc_mux_o ( exc_pc_mux_id ),
.exc_cause_o ( exc_cause ),
.icache_inval_o ( icache_inval ),
// IF and ID control signals
.instr_first_cycle_id_o(instr_first_cycle_id),
.instr_valid_clear_o (instr_valid_clear),
.id_in_ready_o (id_in_ready),
.instr_req_o (instr_req_int),
.pc_set_o (pc_set),
.pc_set_spec_o (pc_set_spec),
.pc_mux_o (pc_mux_id),
.nt_branch_mispredict_o(nt_branch_mispredict),
.exc_pc_mux_o (exc_pc_mux_id),
.exc_cause_o (exc_cause),
.icache_inval_o (icache_inval),
.instr_fetch_err_i ( instr_fetch_err ),
.instr_fetch_err_plus2_i ( instr_fetch_err_plus2 ),
.illegal_c_insn_i ( illegal_c_insn_id ),
.instr_fetch_err_i (instr_fetch_err),
.instr_fetch_err_plus2_i(instr_fetch_err_plus2),
.illegal_c_insn_i (illegal_c_insn_id),
.pc_id_i ( pc_id ),
.pc_id_i(pc_id),
// Stalls
.ex_valid_i ( ex_valid ),
.lsu_resp_valid_i ( lsu_resp_valid ),
// Stalls
.ex_valid_i (ex_valid),
.lsu_resp_valid_i(lsu_resp_valid),
.alu_operator_ex_o ( alu_operator_ex ),
.alu_operand_a_ex_o ( alu_operand_a_ex ),
.alu_operand_b_ex_o ( alu_operand_b_ex ),
.alu_operator_ex_o (alu_operator_ex),
.alu_operand_a_ex_o(alu_operand_a_ex),
.alu_operand_b_ex_o(alu_operand_b_ex),
.imd_val_q_ex_o ( imd_val_q_ex ),
.imd_val_d_ex_i ( imd_val_d_ex ),
.imd_val_we_ex_i ( imd_val_we_ex ),
.imd_val_q_ex_o (imd_val_q_ex),
.imd_val_d_ex_i (imd_val_d_ex),
.imd_val_we_ex_i(imd_val_we_ex),
.bt_a_operand_o ( bt_a_operand ),
.bt_b_operand_o ( bt_b_operand ),
.bt_a_operand_o(bt_a_operand),
.bt_b_operand_o(bt_b_operand),
.mult_en_ex_o ( mult_en_ex ),
.div_en_ex_o ( div_en_ex ),
.mult_sel_ex_o ( mult_sel_ex ),
.div_sel_ex_o ( div_sel_ex ),
.multdiv_operator_ex_o ( multdiv_operator_ex ),
.multdiv_signed_mode_ex_o ( multdiv_signed_mode_ex ),
.multdiv_operand_a_ex_o ( multdiv_operand_a_ex ),
.multdiv_operand_b_ex_o ( multdiv_operand_b_ex ),
.multdiv_ready_id_o ( multdiv_ready_id ),
.mult_en_ex_o (mult_en_ex),
.div_en_ex_o (div_en_ex),
.mult_sel_ex_o (mult_sel_ex),
.div_sel_ex_o (div_sel_ex),
.multdiv_operator_ex_o (multdiv_operator_ex),
.multdiv_signed_mode_ex_o(multdiv_signed_mode_ex),
.multdiv_operand_a_ex_o (multdiv_operand_a_ex),
.multdiv_operand_b_ex_o (multdiv_operand_b_ex),
.multdiv_ready_id_o (multdiv_ready_id),
// CSR ID/EX
.csr_access_o ( csr_access ),
.csr_op_o ( csr_op ),
.csr_op_en_o ( csr_op_en ),
.csr_save_if_o ( csr_save_if ), // control signal to save PC
.csr_save_id_o ( csr_save_id ), // control signal to save PC
.csr_save_wb_o ( csr_save_wb ), // control signal to save PC
.csr_restore_mret_id_o ( csr_restore_mret_id ), // restore mstatus upon MRET
.csr_restore_dret_id_o ( csr_restore_dret_id ), // restore mstatus upon MRET
.csr_save_cause_o ( csr_save_cause ),
.csr_mtval_o ( csr_mtval ),
.priv_mode_i ( priv_mode_id ),
.csr_mstatus_tw_i ( csr_mstatus_tw ),
.illegal_csr_insn_i ( illegal_csr_insn_id ),
.data_ind_timing_i ( data_ind_timing ),
// CSR ID/EX
.csr_access_o (csr_access),
.csr_op_o (csr_op),
.csr_op_en_o (csr_op_en),
.csr_save_if_o (csr_save_if), // control signal to save PC
.csr_save_id_o (csr_save_id), // control signal to save PC
.csr_save_wb_o (csr_save_wb), // control signal to save PC
.csr_restore_mret_id_o(csr_restore_mret_id), // restore mstatus upon MRET
.csr_restore_dret_id_o(csr_restore_dret_id), // restore mstatus upon MRET
.csr_save_cause_o (csr_save_cause),
.csr_mtval_o (csr_mtval),
.priv_mode_i (priv_mode_id),
.csr_mstatus_tw_i (csr_mstatus_tw),
.illegal_csr_insn_i (illegal_csr_insn_id),
.data_ind_timing_i (data_ind_timing),
// LSU
.lsu_req_o ( lsu_req ), // to load store unit
.lsu_we_o ( lsu_we ), // to load store unit
.lsu_type_o ( lsu_type ), // to load store unit
.lsu_sign_ext_o ( lsu_sign_ext ), // to load store unit
.lsu_wdata_o ( lsu_wdata ), // to load store unit
.lsu_req_done_i ( lsu_req_done ), // from load store unit
// LSU
.lsu_req_o (lsu_req), // to load store unit
.lsu_we_o (lsu_we), // to load store unit
.lsu_type_o (lsu_type), // to load store unit
.lsu_sign_ext_o(lsu_sign_ext), // to load store unit
.lsu_wdata_o (lsu_wdata), // to load store unit
.lsu_req_done_i(lsu_req_done), // from load store unit
.lsu_addr_incr_req_i ( lsu_addr_incr_req ),
.lsu_addr_last_i ( lsu_addr_last ),
.lsu_addr_incr_req_i(lsu_addr_incr_req),
.lsu_addr_last_i (lsu_addr_last),
.lsu_load_err_i ( lsu_load_err ),
.lsu_store_err_i ( lsu_store_err ),
.lsu_load_err_i (lsu_load_err),
.lsu_store_err_i(lsu_store_err),
// Interrupt Signals
.csr_mstatus_mie_i ( csr_mstatus_mie ),
.irq_pending_i ( irq_pending_o ),
.irqs_i ( irqs ),
.irq_nm_i ( irq_nm_i ),
.nmi_mode_o ( nmi_mode ),
// Interrupt Signals
.csr_mstatus_mie_i(csr_mstatus_mie),
.irq_pending_i (irq_pending_o),
.irqs_i (irqs),
.irq_nm_i (irq_nm_i),
.nmi_mode_o (nmi_mode),
// Debug Signal
.debug_mode_o ( debug_mode ),
.debug_cause_o ( debug_cause ),
.debug_csr_save_o ( debug_csr_save ),
.debug_req_i ( debug_req_i ),
.debug_single_step_i ( debug_single_step ),
.debug_ebreakm_i ( debug_ebreakm ),
.debug_ebreaku_i ( debug_ebreaku ),
.trigger_match_i ( trigger_match ),
// Debug Signal
.debug_mode_o (debug_mode),
.debug_cause_o (debug_cause),
.debug_csr_save_o (debug_csr_save),
.debug_req_i (debug_req_i),
.debug_single_step_i(debug_single_step),
.debug_ebreakm_i (debug_ebreakm),
.debug_ebreaku_i (debug_ebreaku),
.trigger_match_i (trigger_match),
// write data to commit in the register file
.result_ex_i ( result_ex ),
.csr_rdata_i ( csr_rdata ),
// write data to commit in the register file
.result_ex_i(result_ex),
.csr_rdata_i(csr_rdata),
.rf_raddr_a_o ( rf_raddr_a ),
.rf_rdata_a_i ( rf_rdata_a ),
.rf_raddr_b_o ( rf_raddr_b ),
.rf_rdata_b_i ( rf_rdata_b ),
.rf_ren_a_o ( rf_ren_a ),
.rf_ren_b_o ( rf_ren_b ),
.rf_waddr_id_o ( rf_waddr_id ),
.rf_wdata_id_o ( rf_wdata_id ),
.rf_we_id_o ( rf_we_id ),
.rf_rd_a_wb_match_o ( rf_rd_a_wb_match ),
.rf_rd_b_wb_match_o ( rf_rd_b_wb_match ),
.rf_raddr_a_o (rf_raddr_a),
.rf_rdata_a_i (rf_rdata_a),
.rf_raddr_b_o (rf_raddr_b),
.rf_rdata_b_i (rf_rdata_b),
.rf_ren_a_o (rf_ren_a),
.rf_ren_b_o (rf_ren_b),
.rf_waddr_id_o (rf_waddr_id),
.rf_wdata_id_o (rf_wdata_id),
.rf_we_id_o (rf_we_id),
.rf_rd_a_wb_match_o(rf_rd_a_wb_match),
.rf_rd_b_wb_match_o(rf_rd_b_wb_match),
.rf_waddr_wb_i ( rf_waddr_wb ),
.rf_wdata_fwd_wb_i ( rf_wdata_fwd_wb ),
.rf_write_wb_i ( rf_write_wb ),
.rf_waddr_wb_i (rf_waddr_wb),
.rf_wdata_fwd_wb_i(rf_wdata_fwd_wb),
.rf_write_wb_i (rf_write_wb),
.en_wb_o ( en_wb ),
.instr_type_wb_o ( instr_type_wb ),
.instr_perf_count_id_o ( instr_perf_count_id ),
.ready_wb_i ( ready_wb ),
.outstanding_load_wb_i ( outstanding_load_wb ),
.outstanding_store_wb_i ( outstanding_store_wb ),
.en_wb_o (en_wb),
.instr_type_wb_o (instr_type_wb),
.instr_perf_count_id_o (instr_perf_count_id),
.ready_wb_i (ready_wb),
.outstanding_load_wb_i (outstanding_load_wb),
.outstanding_store_wb_i(outstanding_store_wb),
// Performance Counters
.perf_jump_o ( perf_jump ),
.perf_branch_o ( perf_branch ),
.perf_tbranch_o ( perf_tbranch ),
.perf_dside_wait_o ( perf_dside_wait ),
.perf_mul_wait_o ( perf_mul_wait ),
.perf_div_wait_o ( perf_div_wait ),
.instr_id_done_o ( instr_id_done )
// Performance Counters
.perf_jump_o (perf_jump),
.perf_branch_o (perf_branch),
.perf_tbranch_o (perf_tbranch),
.perf_dside_wait_o(perf_dside_wait),
.perf_mul_wait_o (perf_mul_wait),
.perf_div_wait_o (perf_div_wait),
.instr_id_done_o (instr_id_done)
);
// for RVFI only
assign unused_illegal_insn_id = illegal_insn_id;
ibex_ex_block #(
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.BranchTargetALU ( BranchTargetALU )
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU(BranchTargetALU)
) ex_block_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.clk_i (clk_i),
.rst_ni(rst_ni),
// ALU signal from ID stage
.alu_operator_i ( alu_operator_ex ),
.alu_operand_a_i ( alu_operand_a_ex ),
.alu_operand_b_i ( alu_operand_b_ex ),
.alu_instr_first_cycle_i ( instr_first_cycle_id ),
// ALU signal from ID stage
.alu_operator_i (alu_operator_ex),
.alu_operand_a_i (alu_operand_a_ex),
.alu_operand_b_i (alu_operand_b_ex),
.alu_instr_first_cycle_i(instr_first_cycle_id),
// Branch target ALU signal from ID stage
.bt_a_operand_i ( bt_a_operand ),
.bt_b_operand_i ( bt_b_operand ),
// Branch target ALU signal from ID stage
.bt_a_operand_i(bt_a_operand),
.bt_b_operand_i(bt_b_operand),
// Multipler/Divider signal from ID stage
.multdiv_operator_i ( multdiv_operator_ex ),
.mult_en_i ( mult_en_ex ),
.div_en_i ( div_en_ex ),
.mult_sel_i ( mult_sel_ex ),
.div_sel_i ( div_sel_ex ),
.multdiv_signed_mode_i ( multdiv_signed_mode_ex ),
.multdiv_operand_a_i ( multdiv_operand_a_ex ),
.multdiv_operand_b_i ( multdiv_operand_b_ex ),
.multdiv_ready_id_i ( multdiv_ready_id ),
.data_ind_timing_i ( data_ind_timing ),
// Multipler/Divider signal from ID stage
.multdiv_operator_i (multdiv_operator_ex),
.mult_en_i (mult_en_ex),
.div_en_i (div_en_ex),
.mult_sel_i (mult_sel_ex),
.div_sel_i (div_sel_ex),
.multdiv_signed_mode_i(multdiv_signed_mode_ex),
.multdiv_operand_a_i (multdiv_operand_a_ex),
.multdiv_operand_b_i (multdiv_operand_b_ex),
.multdiv_ready_id_i (multdiv_ready_id),
.data_ind_timing_i (data_ind_timing),
// Intermediate value register
.imd_val_we_o ( imd_val_we_ex ),
.imd_val_d_o ( imd_val_d_ex ),
.imd_val_q_i ( imd_val_q_ex ),
// Intermediate value register
.imd_val_we_o(imd_val_we_ex),
.imd_val_d_o (imd_val_d_ex),
.imd_val_q_i (imd_val_q_ex),
// Outputs
.alu_adder_result_ex_o ( alu_adder_result_ex ), // to LSU
.result_ex_o ( result_ex ), // to ID
// Outputs
.alu_adder_result_ex_o(alu_adder_result_ex), // to LSU
.result_ex_o (result_ex), // to ID
.branch_target_o ( branch_target_ex ), // to IF
.branch_decision_o ( branch_decision ), // to ID
.branch_target_o (branch_target_ex), // to IF
.branch_decision_o(branch_decision), // to ID
.ex_valid_o ( ex_valid )
.ex_valid_o(ex_valid)
);
/////////////////////
@ -702,88 +702,88 @@ module ibex_core import ibex_pkg::*; #(
assign lsu_resp_err = lsu_load_err | lsu_store_err;
ibex_load_store_unit load_store_unit_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.clk_i (clk_i),
.rst_ni(rst_ni),
// data interface
.data_req_o ( data_req_out ),
.data_gnt_i ( data_gnt_i ),
.data_rvalid_i ( data_rvalid_i ),
.data_err_i ( data_err_i ),
.data_pmp_err_i ( pmp_req_err[PMP_D] ),
// data interface
.data_req_o (data_req_out),
.data_gnt_i (data_gnt_i),
.data_rvalid_i (data_rvalid_i),
.data_err_i (data_err_i),
.data_pmp_err_i(pmp_req_err[PMP_D]),
.data_addr_o ( data_addr_o ),
.data_we_o ( data_we_o ),
.data_be_o ( data_be_o ),
.data_wdata_o ( data_wdata_o ),
.data_rdata_i ( data_rdata_i ),
.data_addr_o (data_addr_o),
.data_we_o (data_we_o),
.data_be_o (data_be_o),
.data_wdata_o(data_wdata_o),
.data_rdata_i(data_rdata_i),
// signals to/from ID/EX stage
.lsu_we_i ( lsu_we ),
.lsu_type_i ( lsu_type ),
.lsu_wdata_i ( lsu_wdata ),
.lsu_sign_ext_i ( lsu_sign_ext ),
// signals to/from ID/EX stage
.lsu_we_i (lsu_we),
.lsu_type_i (lsu_type),
.lsu_wdata_i (lsu_wdata),
.lsu_sign_ext_i(lsu_sign_ext),
.lsu_rdata_o ( rf_wdata_lsu ),
.lsu_rdata_valid_o ( rf_we_lsu ),
.lsu_req_i ( lsu_req ),
.lsu_req_done_o ( lsu_req_done ),
.lsu_rdata_o (rf_wdata_lsu),
.lsu_rdata_valid_o(rf_we_lsu),
.lsu_req_i (lsu_req),
.lsu_req_done_o (lsu_req_done),
.adder_result_ex_i ( alu_adder_result_ex ),
.adder_result_ex_i(alu_adder_result_ex),
.addr_incr_req_o ( lsu_addr_incr_req ),
.addr_last_o ( lsu_addr_last ),
.addr_incr_req_o(lsu_addr_incr_req),
.addr_last_o (lsu_addr_last),
.lsu_resp_valid_o ( lsu_resp_valid ),
.lsu_resp_valid_o(lsu_resp_valid),
// exception signals
.load_err_o ( lsu_load_err ),
.store_err_o ( lsu_store_err ),
// exception signals
.load_err_o (lsu_load_err),
.store_err_o(lsu_store_err),
.busy_o ( lsu_busy ),
.busy_o(lsu_busy),
.perf_load_o ( perf_load ),
.perf_store_o ( perf_store )
.perf_load_o (perf_load),
.perf_store_o(perf_store)
);
ibex_wb_stage #(
.ResetAll ( ResetAll ),
.WritebackStage ( WritebackStage )
.WritebackStage(WritebackStage)
) wb_stage_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.en_wb_i ( en_wb ),
.instr_type_wb_i ( instr_type_wb ),
.pc_id_i ( pc_id ),
.instr_is_compressed_id_i ( instr_is_compressed_id ),
.instr_perf_count_id_i ( instr_perf_count_id ),
.clk_i (clk_i),
.rst_ni (rst_ni),
.en_wb_i (en_wb),
.instr_type_wb_i (instr_type_wb),
.pc_id_i (pc_id),
.instr_is_compressed_id_i(instr_is_compressed_id),
.instr_perf_count_id_i (instr_perf_count_id),
.ready_wb_o ( ready_wb ),
.rf_write_wb_o ( rf_write_wb ),
.outstanding_load_wb_o ( outstanding_load_wb ),
.outstanding_store_wb_o ( outstanding_store_wb ),
.pc_wb_o ( pc_wb ),
.perf_instr_ret_wb_o ( perf_instr_ret_wb ),
.perf_instr_ret_compressed_wb_o ( perf_instr_ret_compressed_wb ),
.ready_wb_o (ready_wb),
.rf_write_wb_o (rf_write_wb),
.outstanding_load_wb_o (outstanding_load_wb),
.outstanding_store_wb_o (outstanding_store_wb),
.pc_wb_o (pc_wb),
.perf_instr_ret_wb_o (perf_instr_ret_wb),
.perf_instr_ret_compressed_wb_o(perf_instr_ret_compressed_wb),
.rf_waddr_id_i ( rf_waddr_id ),
.rf_wdata_id_i ( rf_wdata_id ),
.rf_we_id_i ( rf_we_id ),
.rf_waddr_id_i(rf_waddr_id),
.rf_wdata_id_i(rf_wdata_id),
.rf_we_id_i (rf_we_id),
.rf_wdata_lsu_i ( rf_wdata_lsu ),
.rf_we_lsu_i ( rf_we_lsu ),
.rf_wdata_lsu_i(rf_wdata_lsu),
.rf_we_lsu_i (rf_we_lsu),
.rf_wdata_fwd_wb_o ( rf_wdata_fwd_wb ),
.rf_wdata_fwd_wb_o(rf_wdata_fwd_wb),
.rf_waddr_wb_o ( rf_waddr_wb ),
.rf_wdata_wb_o ( rf_wdata_wb ),
.rf_we_wb_o ( rf_we_wb ),
.rf_waddr_wb_o(rf_waddr_wb),
.rf_wdata_wb_o(rf_wdata_wb),
.rf_we_wb_o (rf_we_wb),
.lsu_resp_valid_i ( lsu_resp_valid ),
.lsu_resp_err_i ( lsu_resp_err ),
.lsu_resp_valid_i(lsu_resp_valid),
.lsu_resp_err_i (lsu_resp_err),
.instr_done_wb_o ( instr_done_wb )
.instr_done_wb_o(instr_done_wb)
);
/////////////////////////////
@ -803,22 +803,22 @@ module ibex_core import ibex_pkg::*; #(
// ECC checkbit generation for regiter file wdata
prim_secded_39_32_enc regfile_ecc_enc (
.data_i (rf_wdata_wb),
.data_o (rf_wdata_wb_ecc_o)
.data_i(rf_wdata_wb),
.data_o(rf_wdata_wb_ecc_o)
);
// ECC checking on register file rdata
prim_secded_39_32_dec regfile_ecc_dec_a (
.data_i (rf_rdata_a_ecc_i),
.data_o (),
.syndrome_o (),
.err_o (rf_ecc_err_a)
.data_i (rf_rdata_a_ecc_i),
.data_o (),
.syndrome_o(),
.err_o (rf_ecc_err_a)
);
prim_secded_39_32_dec regfile_ecc_dec_b (
.data_i (rf_rdata_b_ecc_i),
.data_o (),
.syndrome_o (),
.err_o (rf_ecc_err_b)
.data_i (rf_rdata_b_ecc_i),
.data_o (),
.syndrome_o(),
.err_o (rf_ecc_err_b)
);
// Assign read outputs - no error correction, just trigger an alert
@ -923,104 +923,104 @@ module ibex_core import ibex_pkg::*; #(
assign csr_addr = csr_num_e'(csr_access ? alu_operand_b_ex[11:0] : 12'b0);
ibex_cs_registers #(
.DbgTriggerEn ( DbgTriggerEn ),
.DbgHwBreakNum ( DbgHwBreakNum ),
.DataIndTiming ( DataIndTiming ),
.DummyInstructions ( DummyInstructions ),
.ShadowCSR ( ShadowCSR ),
.ICache ( ICache ),
.MHPMCounterNum ( MHPMCounterNum ),
.MHPMCounterWidth ( MHPMCounterWidth ),
.PMPEnable ( PMPEnable ),
.PMPGranularity ( PMPGranularity ),
.PMPNumRegions ( PMPNumRegions ),
.RV32E ( RV32E ),
.RV32M ( RV32M ),
.RV32B ( RV32B )
.DbgTriggerEn (DbgTriggerEn),
.DbgHwBreakNum (DbgHwBreakNum),
.DataIndTiming (DataIndTiming),
.DummyInstructions(DummyInstructions),
.ShadowCSR (ShadowCSR),
.ICache (ICache),
.MHPMCounterNum (MHPMCounterNum),
.MHPMCounterWidth (MHPMCounterWidth),
.PMPEnable (PMPEnable),
.PMPGranularity (PMPGranularity),
.PMPNumRegions (PMPNumRegions),
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B)
) cs_registers_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.clk_i (clk_i),
.rst_ni(rst_ni),
// Hart ID from outside
.hart_id_i ( hart_id_i ),
.priv_mode_id_o ( priv_mode_id ),
.priv_mode_if_o ( priv_mode_if ),
.priv_mode_lsu_o ( priv_mode_lsu ),
// Hart ID from outside
.hart_id_i (hart_id_i),
.priv_mode_id_o (priv_mode_id),
.priv_mode_if_o (priv_mode_if),
.priv_mode_lsu_o(priv_mode_lsu),
// mtvec
.csr_mtvec_o ( csr_mtvec ),
.csr_mtvec_init_i ( csr_mtvec_init ),
.boot_addr_i ( boot_addr_i ),
// mtvec
.csr_mtvec_o (csr_mtvec),
.csr_mtvec_init_i(csr_mtvec_init),
.boot_addr_i (boot_addr_i),
// Interface to CSRs ( SRAM like )
.csr_access_i ( csr_access ),
.csr_addr_i ( csr_addr ),
.csr_wdata_i ( csr_wdata ),
.csr_op_i ( csr_op ),
.csr_op_en_i ( csr_op_en ),
.csr_rdata_o ( csr_rdata ),
// Interface to CSRs ( SRAM like )
.csr_access_i(csr_access),
.csr_addr_i (csr_addr),
.csr_wdata_i (csr_wdata),
.csr_op_i (csr_op),
.csr_op_en_i (csr_op_en),
.csr_rdata_o (csr_rdata),
// Interrupt related control signals
.irq_software_i ( irq_software_i ),
.irq_timer_i ( irq_timer_i ),
.irq_external_i ( irq_external_i ),
.irq_fast_i ( irq_fast_i ),
.nmi_mode_i ( nmi_mode ),
.irq_pending_o ( irq_pending_o ),
.irqs_o ( irqs ),
.csr_mstatus_mie_o ( csr_mstatus_mie ),
.csr_mstatus_tw_o ( csr_mstatus_tw ),
.csr_mepc_o ( csr_mepc ),
// Interrupt related control signals
.irq_software_i (irq_software_i),
.irq_timer_i (irq_timer_i),
.irq_external_i (irq_external_i),
.irq_fast_i (irq_fast_i),
.nmi_mode_i (nmi_mode),
.irq_pending_o (irq_pending_o),
.irqs_o (irqs),
.csr_mstatus_mie_o(csr_mstatus_mie),
.csr_mstatus_tw_o (csr_mstatus_tw),
.csr_mepc_o (csr_mepc),
// PMP
.csr_pmp_cfg_o ( csr_pmp_cfg ),
.csr_pmp_addr_o ( csr_pmp_addr ),
.csr_pmp_mseccfg_o ( csr_pmp_mseccfg ),
// PMP
.csr_pmp_cfg_o (csr_pmp_cfg),
.csr_pmp_addr_o (csr_pmp_addr),
.csr_pmp_mseccfg_o(csr_pmp_mseccfg),
// debug
.csr_depc_o ( csr_depc ),
.debug_mode_i ( debug_mode ),
.debug_cause_i ( debug_cause ),
.debug_csr_save_i ( debug_csr_save ),
.debug_single_step_o ( debug_single_step ),
.debug_ebreakm_o ( debug_ebreakm ),
.debug_ebreaku_o ( debug_ebreaku ),
.trigger_match_o ( trigger_match ),
// debug
.csr_depc_o (csr_depc),
.debug_mode_i (debug_mode),
.debug_cause_i (debug_cause),
.debug_csr_save_i (debug_csr_save),
.debug_single_step_o(debug_single_step),
.debug_ebreakm_o (debug_ebreakm),
.debug_ebreaku_o (debug_ebreaku),
.trigger_match_o (trigger_match),
.pc_if_i ( pc_if ),
.pc_id_i ( pc_id ),
.pc_wb_i ( pc_wb ),
.pc_if_i(pc_if),
.pc_id_i(pc_id),
.pc_wb_i(pc_wb),
.data_ind_timing_o ( data_ind_timing ),
.dummy_instr_en_o ( dummy_instr_en ),
.dummy_instr_mask_o ( dummy_instr_mask ),
.dummy_instr_seed_en_o ( dummy_instr_seed_en ),
.dummy_instr_seed_o ( dummy_instr_seed ),
.icache_enable_o ( icache_enable ),
.csr_shadow_err_o ( csr_shadow_err ),
.data_ind_timing_o (data_ind_timing),
.dummy_instr_en_o (dummy_instr_en),
.dummy_instr_mask_o (dummy_instr_mask),
.dummy_instr_seed_en_o(dummy_instr_seed_en),
.dummy_instr_seed_o (dummy_instr_seed),
.icache_enable_o (icache_enable),
.csr_shadow_err_o (csr_shadow_err),
.csr_save_if_i ( csr_save_if ),
.csr_save_id_i ( csr_save_id ),
.csr_save_wb_i ( csr_save_wb ),
.csr_restore_mret_i ( csr_restore_mret_id ),
.csr_restore_dret_i ( csr_restore_dret_id ),
.csr_save_cause_i ( csr_save_cause ),
.csr_mcause_i ( exc_cause ),
.csr_mtval_i ( csr_mtval ),
.illegal_csr_insn_o ( illegal_csr_insn_id ),
.csr_save_if_i (csr_save_if),
.csr_save_id_i (csr_save_id),
.csr_save_wb_i (csr_save_wb),
.csr_restore_mret_i(csr_restore_mret_id),
.csr_restore_dret_i(csr_restore_dret_id),
.csr_save_cause_i (csr_save_cause),
.csr_mcause_i (exc_cause),
.csr_mtval_i (csr_mtval),
.illegal_csr_insn_o(illegal_csr_insn_id),
// performance counter related signals
.instr_ret_i ( perf_instr_ret_wb ),
.instr_ret_compressed_i ( perf_instr_ret_compressed_wb ),
.iside_wait_i ( perf_iside_wait ),
.jump_i ( perf_jump ),
.branch_i ( perf_branch ),
.branch_taken_i ( perf_tbranch ),
.mem_load_i ( perf_load ),
.mem_store_i ( perf_store ),
.dside_wait_i ( perf_dside_wait ),
.mul_wait_i ( perf_mul_wait ),
.div_wait_i ( perf_div_wait )
// performance counter related signals
.instr_ret_i (perf_instr_ret_wb),
.instr_ret_compressed_i(perf_instr_ret_compressed_wb),
.iside_wait_i (perf_iside_wait),
.jump_i (perf_jump),
.branch_i (perf_branch),
.branch_taken_i (perf_tbranch),
.mem_load_i (perf_load),
.mem_store_i (perf_store),
.dside_wait_i (perf_dside_wait),
.mul_wait_i (perf_mul_wait),
.div_wait_i (perf_div_wait)
);
// These assertions are in top-level as instr_valid_id required as the enable term
@ -1037,29 +1037,29 @@ module ibex_core import ibex_pkg::*; #(
pmp_req_e pmp_req_type [PMP_NUM_CHAN];
priv_lvl_e pmp_priv_lvl [PMP_NUM_CHAN];
assign pmp_req_addr[PMP_I] = {2'b00,instr_addr_o[31:0]};
assign pmp_req_addr[PMP_I] = {2'b00, instr_addr_o[31:0]};
assign pmp_req_type[PMP_I] = PMP_ACC_EXEC;
assign pmp_priv_lvl[PMP_I] = priv_mode_if;
assign pmp_req_addr[PMP_D] = {2'b00,data_addr_o[31:0]};
assign pmp_req_addr[PMP_D] = {2'b00, data_addr_o[31:0]};
assign pmp_req_type[PMP_D] = data_we_o ? PMP_ACC_WRITE : PMP_ACC_READ;
assign pmp_priv_lvl[PMP_D] = priv_mode_lsu;
ibex_pmp #(
.PMPGranularity ( PMPGranularity ),
.PMPNumChan ( PMP_NUM_CHAN ),
.PMPNumRegions ( PMPNumRegions )
.PMPGranularity(PMPGranularity),
.PMPNumChan (PMP_NUM_CHAN),
.PMPNumRegions (PMPNumRegions)
) pmp_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
// Interface to CSRs
.csr_pmp_cfg_i ( csr_pmp_cfg ),
.csr_pmp_addr_i ( csr_pmp_addr ),
.csr_pmp_mseccfg_i ( csr_pmp_mseccfg ),
.priv_mode_i ( pmp_priv_lvl ),
// Access checking channels
.pmp_req_addr_i ( pmp_req_addr ),
.pmp_req_type_i ( pmp_req_type ),
.pmp_req_err_o ( pmp_req_err )
.clk_i (clk_i),
.rst_ni (rst_ni),
// Interface to CSRs
.csr_pmp_cfg_i (csr_pmp_cfg),
.csr_pmp_addr_i (csr_pmp_addr),
.csr_pmp_mseccfg_i(csr_pmp_mseccfg),
.priv_mode_i (pmp_priv_lvl),
// Access checking channels
.pmp_req_addr_i (pmp_req_addr),
.pmp_req_type_i (pmp_req_type),
.pmp_req_err_o (pmp_req_err)
);
end else begin : g_no_pmp
// Unused signal tieoff

391
rtl/ibex_cs_registers.sv
View file

@ -769,30 +769,30 @@ module ibex_cs_registers #(
mprv: 1'b0,
tw: 1'b0};
ibex_csr #(
.Width ($bits(status_t)),
.ShadowCopy (ShadowCSR),
.ResetValue ({MSTATUS_RST_VAL})
.Width ($bits(status_t)),
.ShadowCopy(ShadowCSR),
.ResetValue({MSTATUS_RST_VAL})
) u_mstatus_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i ({mstatus_d}),
.wr_en_i (mstatus_en),
.rd_data_o (mstatus_q),
.rd_error_o (mstatus_err)
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i ({mstatus_d}),
.wr_en_i (mstatus_en),
.rd_data_o (mstatus_q),
.rd_error_o(mstatus_err)
);
// MEPC
ibex_csr #(
.Width (32),
.ShadowCopy (1'b0),
.ResetValue ('0)
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
) u_mepc_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (mepc_d),
.wr_en_i (mepc_en),
.rd_data_o (mepc_q),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (mepc_d),
.wr_en_i (mepc_en),
.rd_data_o (mepc_q),
.rd_error_o()
);
// MIE
@ -801,180 +801,177 @@ module ibex_cs_registers #(
assign mie_d.irq_external = csr_wdata_int[CSR_MEIX_BIT];
assign mie_d.irq_fast = csr_wdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW];
ibex_csr #(
.Width ($bits(irqs_t)),
.ShadowCopy (1'b0),
.ResetValue ('0)
.Width ($bits(irqs_t)),
.ShadowCopy(1'b0),
.ResetValue('0)
) u_mie_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i ({mie_d}),
.wr_en_i (mie_en),
.rd_data_o (mie_q),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i ({mie_d}),
.wr_en_i (mie_en),
.rd_data_o (mie_q),
.rd_error_o()
);
// MSCRATCH
ibex_csr #(
.Width (32),
.ShadowCopy (1'b0),
.ResetValue ('0)
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
) u_mscratch_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (csr_wdata_int),
.wr_en_i (mscratch_en),
.rd_data_o (mscratch_q),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (csr_wdata_int),
.wr_en_i (mscratch_en),
.rd_data_o (mscratch_q),
.rd_error_o()
);
// MCAUSE
ibex_csr #(
.Width (6),
.ShadowCopy (1'b0),
.ResetValue ('0)
.Width (6),
.ShadowCopy(1'b0),
.ResetValue('0)
) u_mcause_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (mcause_d),
.wr_en_i (mcause_en),
.rd_data_o (mcause_q),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (mcause_d),
.wr_en_i (mcause_en),
.rd_data_o (mcause_q),
.rd_error_o()
);
// MTVAL
ibex_csr #(
.Width (32),
.ShadowCopy (1'b0),
.ResetValue ('0)
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
) u_mtval_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (mtval_d),
.wr_en_i (mtval_en),
.rd_data_o (mtval_q),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (mtval_d),
.wr_en_i (mtval_en),
.rd_data_o (mtval_q),
.rd_error_o()
);
// MTVEC
ibex_csr #(
.Width (32),
.ShadowCopy (ShadowCSR),
.ResetValue (32'd1)
.Width (32),
.ShadowCopy(ShadowCSR),
.ResetValue(32'd1)
) u_mtvec_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (mtvec_d),
.wr_en_i (mtvec_en),
.rd_data_o (mtvec_q),
.rd_error_o (mtvec_err)
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (mtvec_d),
.wr_en_i (mtvec_en),
.rd_data_o (mtvec_q),
.rd_error_o(mtvec_err)
);
// DCSR
localparam dcsr_t DCSR_RESET_VAL = '{
xdebugver: XDEBUGVER_STD,
cause: DBG_CAUSE_NONE, // 3'h0
prv: PRIV_LVL_M,
default: '0
cause: DBG_CAUSE_NONE, // 3'h0
prv: PRIV_LVL_M,
default: '0
};
ibex_csr #(
.Width ($bits(dcsr_t)),
.ShadowCopy (1'b0),
.ResetValue ({DCSR_RESET_VAL})
.Width ($bits(dcsr_t)),
.ShadowCopy(1'b0),
.ResetValue({DCSR_RESET_VAL})
) u_dcsr_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i ({dcsr_d}),
.wr_en_i (dcsr_en),
.rd_data_o (dcsr_q),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i ({dcsr_d}),
.wr_en_i (dcsr_en),
.rd_data_o (dcsr_q),
.rd_error_o()
);
// DEPC
ibex_csr #(
.Width (32),
.ShadowCopy (1'b0),
.ResetValue ('0)
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
) u_depc_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (depc_d),
.wr_en_i (depc_en),
.rd_data_o (depc_q),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (depc_d),
.wr_en_i (depc_en),
.rd_data_o (depc_q),
.rd_error_o()
);
// DSCRATCH0
ibex_csr #(
.Width (32),
.ShadowCopy (1'b0),
.ResetValue ('0)
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
) u_dscratch0_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (csr_wdata_int),
.wr_en_i (dscratch0_en),
.rd_data_o (dscratch0_q),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (csr_wdata_int),
.wr_en_i (dscratch0_en),
.rd_data_o (dscratch0_q),
.rd_error_o()
);
// DSCRATCH1
ibex_csr #(
.Width (32),
.ShadowCopy (1'b0),
.ResetValue ('0)
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
) u_dscratch1_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (csr_wdata_int),
.wr_en_i (dscratch1_en),
.rd_data_o (dscratch1_q),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (csr_wdata_int),
.wr_en_i (dscratch1_en),
.rd_data_o (dscratch1_q),
.rd_error_o()
);
// MSTACK
localparam status_stk_t MSTACK_RESET_VAL = '{
mpie: 1'b1,
mpp: PRIV_LVL_U
};
localparam status_stk_t MSTACK_RESET_VAL = '{mpie: 1'b1, mpp: PRIV_LVL_U};
ibex_csr #(
.Width ($bits(status_stk_t)),
.ShadowCopy (1'b0),
.ResetValue ({MSTACK_RESET_VAL})
.Width ($bits(status_stk_t)),
.ShadowCopy(1'b0),
.ResetValue({MSTACK_RESET_VAL})
) u_mstack_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i ({mstack_d}),
.wr_en_i (mstack_en),
.rd_data_o (mstack_q),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i ({mstack_d}),
.wr_en_i (mstack_en),
.rd_data_o (mstack_q),
.rd_error_o()
);
// MSTACK_EPC
ibex_csr #(
.Width (32),
.ShadowCopy (1'b0),
.ResetValue ('0)
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
) u_mstack_epc_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (mstack_epc_d),
.wr_en_i (mstack_en),
.rd_data_o (mstack_epc_q),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (mstack_epc_d),
.wr_en_i (mstack_en),
.rd_data_o (mstack_epc_q),
.rd_error_o()
);
// MSTACK_CAUSE
ibex_csr #(
.Width (6),
.ShadowCopy (1'b0),
.ResetValue ('0)
.Width (6),
.ShadowCopy(1'b0),
.ResetValue('0)
) u_mstack_cause_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (mstack_cause_d),
.wr_en_i (mstack_en),
.rd_data_o (mstack_cause_q),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (mstack_cause_d),
.wr_en_i (mstack_en),
.rd_data_o (mstack_cause_q),
.rd_error_o()
);
// -----------------
@ -1066,16 +1063,16 @@ module ibex_cs_registers #(
assign pmp_cfg_wdata[i].read = csr_wdata_int[(i%4)*PMP_CFG_W];
ibex_csr #(
.Width ($bits(pmp_cfg_t)),
.ShadowCopy (ShadowCSR),
.ResetValue ('0)
.Width ($bits(pmp_cfg_t)),
.ShadowCopy(ShadowCSR),
.ResetValue('0)
) u_pmp_cfg_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i ({pmp_cfg_wdata[i]}),
.wr_en_i (pmp_cfg_we[i]),
.rd_data_o (pmp_cfg[i]),
.rd_error_o (pmp_cfg_err[i])
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i ({pmp_cfg_wdata[i]}),
.wr_en_i (pmp_cfg_we[i]),
.rd_data_o (pmp_cfg[i]),
.rd_error_o(pmp_cfg_err[i])
);
// MSECCFG.RLB allows the lock bit to be bypassed (allowing cfg writes when MSECCFG.RLB is
@ -1095,16 +1092,16 @@ module ibex_cs_registers #(
end
ibex_csr #(
.Width (PMPAddrWidth),
.ShadowCopy (ShadowCSR),
.ResetValue ('0)
.Width (PMPAddrWidth),
.ShadowCopy(ShadowCSR),
.ResetValue('0)
) u_pmp_addr_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (csr_wdata_int[31-:PMPAddrWidth]),
.wr_en_i (pmp_addr_we[i]),
.rd_data_o (pmp_addr[i]),
.rd_error_o (pmp_addr_err[i])
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (csr_wdata_int[31-:PMPAddrWidth]),
.wr_en_i (pmp_addr_we[i]),
.rd_data_o (pmp_addr[i]),
.rd_error_o(pmp_addr_err[i])
);
assign csr_pmp_cfg_o[i] = pmp_cfg[i];
@ -1126,16 +1123,16 @@ module ibex_cs_registers #(
assign pmp_mseccfg_d.rlb = any_pmp_entry_locked ? 1'b0 : csr_wdata_int[CSR_MSECCFG_RLB_BIT];
ibex_csr #(
.Width ($bits(pmp_mseccfg_t)),
.ShadowCopy (ShadowCSR),
.ResetValue ('0)
.Width ($bits(pmp_mseccfg_t)),
.ShadowCopy(ShadowCSR),
.ResetValue('0)
) u_pmp_mseccfg (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (pmp_mseccfg_d),
.wr_en_i (pmp_mseccfg_we),
.rd_data_o (pmp_mseccfg_q),
.rd_error_o (pmp_mseccfg_err)
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (pmp_mseccfg_d),
.wr_en_i (pmp_mseccfg_we),
.rd_data_o (pmp_mseccfg_q),
.rd_error_o(pmp_mseccfg_err)
);
assign pmp_csr_err = (|pmp_cfg_err) | (|pmp_addr_err) | pmp_mseccfg_err;
@ -1331,43 +1328,43 @@ module ibex_cs_registers #(
// Registers
ibex_csr #(
.Width (DbgHwNumLen),
.ShadowCopy (1'b0),
.ResetValue ('0)
.Width (DbgHwNumLen),
.ShadowCopy(1'b0),
.ResetValue('0)
) u_tselect_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (tselect_d),
.wr_en_i (tselect_we),
.rd_data_o (tselect_q),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (tselect_d),
.wr_en_i (tselect_we),
.rd_data_o (tselect_q),
.rd_error_o()
);
for (genvar i = 0; i < DbgHwBreakNum; i++) begin : g_dbg_tmatch_reg
ibex_csr #(
.Width (1),
.ShadowCopy (1'b0),
.ResetValue ('0)
.Width (1),
.ShadowCopy(1'b0),
.ResetValue('0)
) u_tmatch_control_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (tmatch_control_d),
.wr_en_i (tmatch_control_we[i]),
.rd_data_o (tmatch_control_q[i]),
.rd_error_o ()
);
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (tmatch_control_d),
.wr_en_i (tmatch_control_we[i]),
.rd_data_o (tmatch_control_q[i]),
.rd_error_o()
);
ibex_csr #(
.Width (32),
.ShadowCopy (1'b0),
.ResetValue ('0)
.Width (32),
.ShadowCopy(1'b0),
.ResetValue('0)
) u_tmatch_value_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (tmatch_value_d),
.wr_en_i (tmatch_value_we[i]),
.rd_data_o (tmatch_value_q[i]),
.rd_error_o ()
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i (tmatch_value_d),
.wr_en_i (tmatch_value_we[i]),
.rd_data_o (tmatch_value_q[i]),
.rd_error_o()
);
end
@ -1483,16 +1480,16 @@ module ibex_cs_registers #(
assign icache_enable_o = cpuctrl_q.icache_enable;
ibex_csr #(
.Width ($bits(cpu_ctrl_t)),
.ShadowCopy (ShadowCSR),
.ResetValue ('0)
.Width ($bits(cpu_ctrl_t)),
.ShadowCopy(ShadowCSR),
.ResetValue('0)
) u_cpuctrl_csr (
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i ({cpuctrl_d}),
.wr_en_i (cpuctrl_we),
.rd_data_o (cpuctrl_q),
.rd_error_o (cpuctrl_err)
.clk_i (clk_i),
.rst_ni (rst_ni),
.wr_data_i ({cpuctrl_d}),
.wr_en_i (cpuctrl_we),
.rd_data_o (cpuctrl_q),
.rd_error_o(cpuctrl_err)
);
assign csr_shadow_err_o = mstatus_err | mtvec_err | pmp_csr_err | cpuctrl_err;

126
rtl/ibex_ex_block.sv
View file

@ -115,22 +115,22 @@ module ibex_ex_block #(
ibex_alu #(
.RV32B(RV32B)
) alu_i (
.operator_i ( alu_operator_i ),
.operand_a_i ( alu_operand_a_i ),
.operand_b_i ( alu_operand_b_i ),
.instr_first_cycle_i ( alu_instr_first_cycle_i ),
.imd_val_q_i ( alu_imd_val_q ),
.imd_val_we_o ( alu_imd_val_we ),
.imd_val_d_o ( alu_imd_val_d ),
.multdiv_operand_a_i ( multdiv_alu_operand_a ),
.multdiv_operand_b_i ( multdiv_alu_operand_b ),
.multdiv_sel_i ( multdiv_sel ),
.adder_result_o ( alu_adder_result_ex_o ),
.adder_result_ext_o ( alu_adder_result_ext ),
.result_o ( alu_result ),
.comparison_result_o ( alu_cmp_result ),
.is_equal_result_o ( alu_is_equal_result )
) alu_i (
.operator_i (alu_operator_i),
.operand_a_i (alu_operand_a_i),
.operand_b_i (alu_operand_b_i),
.instr_first_cycle_i(alu_instr_first_cycle_i),
.imd_val_q_i (alu_imd_val_q),
.imd_val_we_o (alu_imd_val_we),
.imd_val_d_o (alu_imd_val_d),
.multdiv_operand_a_i(multdiv_alu_operand_a),
.multdiv_operand_b_i(multdiv_alu_operand_b),
.multdiv_sel_i (multdiv_sel),
.adder_result_o (alu_adder_result_ex_o),
.adder_result_ext_o (alu_adder_result_ext),
.result_o (alu_result),
.comparison_result_o(alu_cmp_result),
.is_equal_result_o (alu_is_equal_result)
);
////////////////
@ -139,55 +139,55 @@ module ibex_ex_block #(
if (RV32M == RV32MSlow) begin : gen_multdiv_slow
ibex_multdiv_slow multdiv_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.mult_en_i ( mult_en_i ),
.div_en_i ( div_en_i ),
.mult_sel_i ( mult_sel_i ),
.div_sel_i ( div_sel_i ),
.operator_i ( multdiv_operator_i ),
.signed_mode_i ( multdiv_signed_mode_i ),
.op_a_i ( multdiv_operand_a_i ),
.op_b_i ( multdiv_operand_b_i ),
.alu_adder_ext_i ( alu_adder_result_ext ),
.alu_adder_i ( alu_adder_result_ex_o ),
.equal_to_zero_i ( alu_is_equal_result ),
.data_ind_timing_i ( data_ind_timing_i ),
.valid_o ( multdiv_valid ),
.alu_operand_a_o ( multdiv_alu_operand_a ),
.alu_operand_b_o ( multdiv_alu_operand_b ),
.imd_val_q_i ( imd_val_q_i ),
.imd_val_d_o ( multdiv_imd_val_d ),
.imd_val_we_o ( multdiv_imd_val_we ),
.multdiv_ready_id_i ( multdiv_ready_id_i ),
.multdiv_result_o ( multdiv_result )
.clk_i (clk_i),
.rst_ni (rst_ni),
.mult_en_i (mult_en_i),
.div_en_i (div_en_i),
.mult_sel_i (mult_sel_i),
.div_sel_i (div_sel_i),
.operator_i (multdiv_operator_i),
.signed_mode_i (multdiv_signed_mode_i),
.op_a_i (multdiv_operand_a_i),
.op_b_i (multdiv_operand_b_i),
.alu_adder_ext_i (alu_adder_result_ext),
.alu_adder_i (alu_adder_result_ex_o),
.equal_to_zero_i (alu_is_equal_result),
.data_ind_timing_i (data_ind_timing_i),
.valid_o (multdiv_valid),
.alu_operand_a_o (multdiv_alu_operand_a),
.alu_operand_b_o (multdiv_alu_operand_b),
.imd_val_q_i (imd_val_q_i),
.imd_val_d_o (multdiv_imd_val_d),
.imd_val_we_o (multdiv_imd_val_we),
.multdiv_ready_id_i(multdiv_ready_id_i),
.multdiv_result_o (multdiv_result)
);
end else if (RV32M == RV32MFast || RV32M == RV32MSingleCycle) begin : gen_multdiv_fast
ibex_multdiv_fast # (
.RV32M ( RV32M )
) multdiv_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.mult_en_i ( mult_en_i ),
.div_en_i ( div_en_i ),
.mult_sel_i ( mult_sel_i ),
.div_sel_i ( div_sel_i ),
.operator_i ( multdiv_operator_i ),
.signed_mode_i ( multdiv_signed_mode_i ),
.op_a_i ( multdiv_operand_a_i ),
.op_b_i ( multdiv_operand_b_i ),
.alu_operand_a_o ( multdiv_alu_operand_a ),
.alu_operand_b_o ( multdiv_alu_operand_b ),
.alu_adder_ext_i ( alu_adder_result_ext ),
.alu_adder_i ( alu_adder_result_ex_o ),
.equal_to_zero_i ( alu_is_equal_result ),
.data_ind_timing_i ( data_ind_timing_i ),
.imd_val_q_i ( imd_val_q_i ),
.imd_val_d_o ( multdiv_imd_val_d ),
.imd_val_we_o ( multdiv_imd_val_we ),
.multdiv_ready_id_i ( multdiv_ready_id_i ),
.valid_o ( multdiv_valid ),
.multdiv_result_o ( multdiv_result )
ibex_multdiv_fast #(
.RV32M(RV32M)
) multdiv_i (
.clk_i (clk_i),
.rst_ni (rst_ni),
.mult_en_i (mult_en_i),
.div_en_i (div_en_i),
.mult_sel_i (mult_sel_i),
.div_sel_i (div_sel_i),
.operator_i (multdiv_operator_i),
.signed_mode_i (multdiv_signed_mode_i),
.op_a_i (multdiv_operand_a_i),
.op_b_i (multdiv_operand_b_i),
.alu_operand_a_o (multdiv_alu_operand_a),
.alu_operand_b_o (multdiv_alu_operand_b),
.alu_adder_ext_i (alu_adder_result_ext),
.alu_adder_i (alu_adder_result_ex_o),
.equal_to_zero_i (alu_is_equal_result),
.data_ind_timing_i (data_ind_timing_i),
.imd_val_q_i (imd_val_q_i),
.imd_val_d_o (multdiv_imd_val_d),
.imd_val_we_o (multdiv_imd_val_we),
.multdiv_ready_id_i(multdiv_ready_id_i),
.valid_o (multdiv_valid),
.multdiv_result_o (multdiv_result)
);
end

278
rtl/ibex_id_stage.sv
View file

@ -421,81 +421,81 @@ module ibex_id_stage #(
/////////////
ibex_decoder #(
.RV32E ( RV32E ),
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.BranchTargetALU ( BranchTargetALU )
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU(BranchTargetALU)
) decoder_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.clk_i (clk_i),
.rst_ni(rst_ni),
// controller
.illegal_insn_o ( illegal_insn_dec ),
.ebrk_insn_o ( ebrk_insn ),
.mret_insn_o ( mret_insn_dec ),
.dret_insn_o ( dret_insn_dec ),
.ecall_insn_o ( ecall_insn_dec ),
.wfi_insn_o ( wfi_insn_dec ),
.jump_set_o ( jump_set_dec ),
.branch_taken_i ( branch_taken ),
.icache_inval_o ( icache_inval_o ),
// controller
.illegal_insn_o(illegal_insn_dec),
.ebrk_insn_o (ebrk_insn),
.mret_insn_o (mret_insn_dec),
.dret_insn_o (dret_insn_dec),
.ecall_insn_o (ecall_insn_dec),
.wfi_insn_o (wfi_insn_dec),
.jump_set_o (jump_set_dec),
.branch_taken_i(branch_taken),
.icache_inval_o(icache_inval_o),
// from IF-ID pipeline register
.instr_first_cycle_i ( instr_first_cycle ),
.instr_rdata_i ( instr_rdata_i ),
.instr_rdata_alu_i ( instr_rdata_alu_i ),
.illegal_c_insn_i ( illegal_c_insn_i ),
// from IF-ID pipeline register
.instr_first_cycle_i(instr_first_cycle),
.instr_rdata_i (instr_rdata_i),
.instr_rdata_alu_i (instr_rdata_alu_i),
.illegal_c_insn_i (illegal_c_insn_i),
// immediates
.imm_a_mux_sel_o ( imm_a_mux_sel ),
.imm_b_mux_sel_o ( imm_b_mux_sel_dec ),
.bt_a_mux_sel_o ( bt_a_mux_sel ),
.bt_b_mux_sel_o ( bt_b_mux_sel ),
// immediates
.imm_a_mux_sel_o(imm_a_mux_sel),
.imm_b_mux_sel_o(imm_b_mux_sel_dec),
.bt_a_mux_sel_o (bt_a_mux_sel),
.bt_b_mux_sel_o (bt_b_mux_sel),
.imm_i_type_o ( imm_i_type ),
.imm_s_type_o ( imm_s_type ),
.imm_b_type_o ( imm_b_type ),
.imm_u_type_o ( imm_u_type ),
.imm_j_type_o ( imm_j_type ),
.zimm_rs1_type_o ( zimm_rs1_type ),
.imm_i_type_o (imm_i_type),
.imm_s_type_o (imm_s_type),
.imm_b_type_o (imm_b_type),
.imm_u_type_o (imm_u_type),
.imm_j_type_o (imm_j_type),
.zimm_rs1_type_o(zimm_rs1_type),
// register file
.rf_wdata_sel_o ( rf_wdata_sel ),
.rf_we_o ( rf_we_dec ),
// register file
.rf_wdata_sel_o(rf_wdata_sel),
.rf_we_o (rf_we_dec),
.rf_raddr_a_o ( rf_raddr_a_o ),
.rf_raddr_b_o ( rf_raddr_b_o ),
.rf_waddr_o ( rf_waddr_id_o ),
.rf_ren_a_o ( rf_ren_a_dec ),
.rf_ren_b_o ( rf_ren_b_dec ),
.rf_raddr_a_o(rf_raddr_a_o),
.rf_raddr_b_o(rf_raddr_b_o),
.rf_waddr_o (rf_waddr_id_o),
.rf_ren_a_o (rf_ren_a_dec),
.rf_ren_b_o (rf_ren_b_dec),
// ALU
.alu_operator_o ( alu_operator ),
.alu_op_a_mux_sel_o ( alu_op_a_mux_sel_dec ),
.alu_op_b_mux_sel_o ( alu_op_b_mux_sel_dec ),
.alu_multicycle_o ( alu_multicycle_dec ),
// ALU
.alu_operator_o (alu_operator),
.alu_op_a_mux_sel_o(alu_op_a_mux_sel_dec),
.alu_op_b_mux_sel_o(alu_op_b_mux_sel_dec),
.alu_multicycle_o (alu_multicycle_dec),
// MULT & DIV
.mult_en_o ( mult_en_dec ),
.div_en_o ( div_en_dec ),
.mult_sel_o ( mult_sel_ex_o ),
.div_sel_o ( div_sel_ex_o ),
.multdiv_operator_o ( multdiv_operator ),
.multdiv_signed_mode_o ( multdiv_signed_mode ),
// MULT & DIV
.mult_en_o (mult_en_dec),
.div_en_o (div_en_dec),
.mult_sel_o (mult_sel_ex_o),
.div_sel_o (div_sel_ex_o),
.multdiv_operator_o (multdiv_operator),
.multdiv_signed_mode_o(multdiv_signed_mode),
// CSRs
.csr_access_o ( csr_access_o ),
.csr_op_o ( csr_op_o ),
// CSRs
.csr_access_o(csr_access_o),
.csr_op_o (csr_op_o),
// LSU
.data_req_o ( lsu_req_dec ),
.data_we_o ( lsu_we ),
.data_type_o ( lsu_type ),
.data_sign_extension_o ( lsu_sign_ext ),
// LSU
.data_req_o (lsu_req_dec),
.data_we_o (lsu_we),
.data_type_o (lsu_type),
.data_sign_extension_o(lsu_sign_ext),
// jump/branches
.jump_in_dec_o ( jump_in_dec ),
.branch_in_dec_o ( branch_in_dec )
// jump/branches
.jump_in_dec_o (jump_in_dec),
.branch_in_dec_o(branch_in_dec)
);
/////////////////////////////////
@ -531,95 +531,95 @@ module ibex_id_stage #(
assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i);
ibex_controller #(
.WritebackStage ( WritebackStage ),
.BranchPredictor ( BranchPredictor )
.WritebackStage (WritebackStage),
.BranchPredictor(BranchPredictor)
) controller_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.clk_i (clk_i),
.rst_ni(rst_ni),
.ctrl_busy_o ( ctrl_busy_o ),
.ctrl_busy_o(ctrl_busy_o),
// decoder related signals
.illegal_insn_i ( illegal_insn_o ),
.ecall_insn_i ( ecall_insn_dec ),
.mret_insn_i ( mret_insn_dec ),
.dret_insn_i ( dret_insn_dec ),
.wfi_insn_i ( wfi_insn_dec ),
.ebrk_insn_i ( ebrk_insn ),
.csr_pipe_flush_i ( csr_pipe_flush ),
// decoder related signals
.illegal_insn_i (illegal_insn_o),
.ecall_insn_i (ecall_insn_dec),
.mret_insn_i (mret_insn_dec),
.dret_insn_i (dret_insn_dec),
.wfi_insn_i (wfi_insn_dec),
.ebrk_insn_i (ebrk_insn),
.csr_pipe_flush_i(csr_pipe_flush),
// from IF-ID pipeline
.instr_valid_i ( instr_valid_i ),
.instr_i ( instr_rdata_i ),
.instr_compressed_i ( instr_rdata_c_i ),
.instr_is_compressed_i ( instr_is_compressed_i ),
.instr_bp_taken_i ( instr_bp_taken_i ),
.instr_fetch_err_i ( instr_fetch_err_i ),
.instr_fetch_err_plus2_i ( instr_fetch_err_plus2_i ),
.pc_id_i ( pc_id_i ),
// from IF-ID pipeline
.instr_valid_i (instr_valid_i),
.instr_i (instr_rdata_i),
.instr_compressed_i (instr_rdata_c_i),
.instr_is_compressed_i (instr_is_compressed_i),
.instr_bp_taken_i (instr_bp_taken_i),
.instr_fetch_err_i (instr_fetch_err_i),
.instr_fetch_err_plus2_i(instr_fetch_err_plus2_i),
.pc_id_i (pc_id_i),
// to IF-ID pipeline
.instr_valid_clear_o ( instr_valid_clear_o ),
.id_in_ready_o ( id_in_ready_o ),
.controller_run_o ( controller_run ),
// to IF-ID pipeline
.instr_valid_clear_o(instr_valid_clear_o),
.id_in_ready_o (id_in_ready_o),
.controller_run_o (controller_run),
// to prefetcher
.instr_req_o ( instr_req_o ),
.pc_set_o ( pc_set_o ),
.pc_set_spec_o ( pc_set_spec_o ),
.pc_mux_o ( pc_mux_o ),
.nt_branch_mispredict_o ( nt_branch_mispredict_o ),
.exc_pc_mux_o ( exc_pc_mux_o ),
.exc_cause_o ( exc_cause_o ),
// to prefetcher
.instr_req_o (instr_req_o),
.pc_set_o (pc_set_o),
.pc_set_spec_o (pc_set_spec_o),
.pc_mux_o (pc_mux_o),
.nt_branch_mispredict_o(nt_branch_mispredict_o),
.exc_pc_mux_o (exc_pc_mux_o),
.exc_cause_o (exc_cause_o),
// LSU
.lsu_addr_last_i ( lsu_addr_last_i ),
.load_err_i ( lsu_load_err_i ),
.store_err_i ( lsu_store_err_i ),
.wb_exception_o ( wb_exception ),
// LSU
.lsu_addr_last_i(lsu_addr_last_i),
.load_err_i (lsu_load_err_i),
.store_err_i (lsu_store_err_i),
.wb_exception_o (wb_exception),
// jump/branch control
.branch_set_i ( branch_set ),
.branch_set_spec_i ( branch_set_spec ),
.branch_not_set_i ( branch_not_set ),
.jump_set_i ( jump_set ),
// jump/branch control
.branch_set_i (branch_set),
.branch_set_spec_i(branch_set_spec),
.branch_not_set_i (branch_not_set),
.jump_set_i (jump_set),
// interrupt signals
.csr_mstatus_mie_i ( csr_mstatus_mie_i ),
.irq_pending_i ( irq_pending_i ),
.irqs_i ( irqs_i ),
.irq_nm_i ( irq_nm_i ),
.nmi_mode_o ( nmi_mode_o ),
// interrupt signals
.csr_mstatus_mie_i(csr_mstatus_mie_i),
.irq_pending_i (irq_pending_i),
.irqs_i (irqs_i),
.irq_nm_i (irq_nm_i),
.nmi_mode_o (nmi_mode_o),
// CSR Controller Signals
.csr_save_if_o ( csr_save_if_o ),
.csr_save_id_o ( csr_save_id_o ),
.csr_save_wb_o ( csr_save_wb_o ),
.csr_restore_mret_id_o ( csr_restore_mret_id_o ),
.csr_restore_dret_id_o ( csr_restore_dret_id_o ),
.csr_save_cause_o ( csr_save_cause_o ),
.csr_mtval_o ( csr_mtval_o ),
.priv_mode_i ( priv_mode_i ),
.csr_mstatus_tw_i ( csr_mstatus_tw_i ),
// CSR Controller Signals
.csr_save_if_o (csr_save_if_o),
.csr_save_id_o (csr_save_id_o),
.csr_save_wb_o (csr_save_wb_o),
.csr_restore_mret_id_o(csr_restore_mret_id_o),
.csr_restore_dret_id_o(csr_restore_dret_id_o),
.csr_save_cause_o (csr_save_cause_o),
.csr_mtval_o (csr_mtval_o),
.priv_mode_i (priv_mode_i),
.csr_mstatus_tw_i (csr_mstatus_tw_i),
// Debug Signal
.debug_mode_o ( debug_mode_o ),
.debug_cause_o ( debug_cause_o ),
.debug_csr_save_o ( debug_csr_save_o ),
.debug_req_i ( debug_req_i ),
.debug_single_step_i ( debug_single_step_i ),
.debug_ebreakm_i ( debug_ebreakm_i ),
.debug_ebreaku_i ( debug_ebreaku_i ),
.trigger_match_i ( trigger_match_i ),
// Debug Signal
.debug_mode_o (debug_mode_o),
.debug_cause_o (debug_cause_o),
.debug_csr_save_o (debug_csr_save_o),
.debug_req_i (debug_req_i),
.debug_single_step_i(debug_single_step_i),
.debug_ebreakm_i (debug_ebreakm_i),
.debug_ebreaku_i (debug_ebreaku_i),
.trigger_match_i (trigger_match_i),
.stall_id_i ( stall_id ),
.stall_wb_i ( stall_wb ),
.flush_id_o ( flush_id ),
.ready_wb_i ( ready_wb_i ),
.stall_id_i(stall_id),
.stall_wb_i(stall_wb),
.flush_id_o(flush_id),
.ready_wb_i(ready_wb_i),
// Performance Counters
.perf_jump_o ( perf_jump_o ),
.perf_tbranch_o ( perf_tbranch_o )
// Performance Counters
.perf_jump_o (perf_jump_o),
.perf_tbranch_o(perf_tbranch_o)
);
assign multdiv_en_dec = mult_en_dec | div_en_dec;

48
rtl/ibex_if_stage.sv
View file

@ -318,13 +318,13 @@ module ibex_if_stage import ibex_pkg::*; #(
logic instr_is_compressed;
ibex_compressed_decoder compressed_decoder_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.valid_i ( fetch_valid & ~fetch_err ),
.instr_i ( if_instr_rdata ),
.instr_o ( instr_decompressed ),
.is_compressed_o ( instr_is_compressed ),
.illegal_instr_o ( illegal_c_insn )
.clk_i (clk_i),
.rst_ni (rst_ni),
.valid_i (fetch_valid & ~fetch_err),
.instr_i (if_instr_rdata),
.instr_o (instr_decompressed),
.is_compressed_o(instr_is_compressed),
.illegal_instr_o(illegal_c_insn)
);
// Dummy instruction insertion
@ -336,16 +336,16 @@ module ibex_if_stage import ibex_pkg::*; #(
.RndCnstLfsrSeed (RndCnstLfsrSeed),
.RndCnstLfsrPerm (RndCnstLfsrPerm)
) dummy_instr_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.dummy_instr_en_i ( dummy_instr_en_i ),
.dummy_instr_mask_i ( dummy_instr_mask_i ),
.dummy_instr_seed_en_i ( dummy_instr_seed_en_i ),
.dummy_instr_seed_i ( dummy_instr_seed_i ),
.fetch_valid_i ( fetch_valid ),
.id_in_ready_i ( id_in_ready_i ),
.insert_dummy_instr_o ( insert_dummy_instr ),
.dummy_instr_data_o ( dummy_instr_data )
.clk_i (clk_i),
.rst_ni (rst_ni),
.dummy_instr_en_i (dummy_instr_en_i),
.dummy_instr_mask_i (dummy_instr_mask_i),
.dummy_instr_seed_en_i(dummy_instr_seed_en_i),
.dummy_instr_seed_i (dummy_instr_seed_i),
.fetch_valid_i (fetch_valid),
.id_in_ready_i (id_in_ready_i),
.insert_dummy_instr_o (insert_dummy_instr),
.dummy_instr_data_o (dummy_instr_data)
);
// Mux between actual instructions and dummy instructions
@ -548,14 +548,14 @@ module ibex_if_stage import ibex_pkg::*; #(
end
ibex_branch_predict branch_predict_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.fetch_rdata_i ( fetch_rdata ),
.fetch_pc_i ( fetch_addr ),
.fetch_valid_i ( fetch_valid ),
.clk_i (clk_i),
.rst_ni (rst_ni),
.fetch_rdata_i(fetch_rdata),
.fetch_pc_i (fetch_addr),
.fetch_valid_i(fetch_valid),
.predict_branch_taken_o ( predict_branch_taken_raw ),
.predict_branch_pc_o ( predict_branch_pc )
.predict_branch_taken_o(predict_branch_taken_raw),
.predict_branch_pc_o (predict_branch_pc)
);
// If there is an instruction in the skid buffer there must be no branch prediction.

294
rtl/ibex_top.sv
View file

@ -172,10 +172,10 @@ module ibex_top import ibex_pkg::*; #(
assign core_sleep_o = ~clock_en;
prim_clock_gating core_clock_gate_i (
.clk_i ( clk_i ),
.en_i ( clock_en ),
.test_en_i ( test_en_i ),
.clk_o ( clk )
.clk_i (clk_i),
.en_i (clock_en),
.test_en_i(test_en_i),
.clk_o (clk)
);
////////////////////////
@ -183,35 +183,35 @@ module ibex_top import ibex_pkg::*; #(
////////////////////////
ibex_core #(
.PMPEnable ( PMPEnable ),
.PMPGranularity ( PMPGranularity ),
.PMPNumRegions ( PMPNumRegions ),
.MHPMCounterNum ( MHPMCounterNum ),
.MHPMCounterWidth ( MHPMCounterWidth ),
.RV32E ( RV32E ),
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.BranchTargetALU ( BranchTargetALU ),
.ICache ( ICache ),
.ICacheECC ( ICacheECC ),
.BusSizeECC ( BusSizeECC ),
.TagSizeECC ( TagSizeECC ),
.LineSizeECC ( LineSizeECC ),
.BranchPredictor ( BranchPredictor ),
.DbgTriggerEn ( DbgTriggerEn ),
.DbgHwBreakNum ( DbgHwBreakNum ),
.WritebackStage ( WritebackStage ),
.ResetAll ( ResetAll ),
.RndCnstLfsrSeed ( RndCnstLfsrSeed ),
.RndCnstLfsrPerm ( RndCnstLfsrPerm ),
.SecureIbex ( SecureIbex ),
.DummyInstructions ( DummyInstructions ),
.RegFileECC ( RegFileECC ),
.RegFileDataWidth ( RegFileDataWidth ),
.DmHaltAddr ( DmHaltAddr ),
.DmExceptionAddr ( DmExceptionAddr )
.PMPEnable (PMPEnable),
.PMPGranularity (PMPGranularity),
.PMPNumRegions (PMPNumRegions),
.MHPMCounterNum (MHPMCounterNum),
.MHPMCounterWidth (MHPMCounterWidth),
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU (BranchTargetALU),
.ICache (ICache),
.ICacheECC (ICacheECC),
.BusSizeECC (BusSizeECC),
.TagSizeECC (TagSizeECC),
.LineSizeECC (LineSizeECC),
.BranchPredictor (BranchPredictor),
.DbgTriggerEn (DbgTriggerEn),
.DbgHwBreakNum (DbgHwBreakNum),
.WritebackStage (WritebackStage),
.ResetAll (ResetAll),
.RndCnstLfsrSeed (RndCnstLfsrSeed),
.RndCnstLfsrPerm (RndCnstLfsrPerm),
.SecureIbex (SecureIbex),
.DummyInstructions(DummyInstructions),
.RegFileECC (RegFileECC),
.RegFileDataWidth (RegFileDataWidth),
.DmHaltAddr (DmHaltAddr),
.DmExceptionAddr (DmExceptionAddr)
) u_ibex_core (
.clk_i (clk),
.clk_i(clk),
.rst_ni,
.hart_id_i,
@ -234,32 +234,32 @@ module ibex_top import ibex_pkg::*; #(
.data_rdata_i,
.data_err_i,
.dummy_instr_id_o (dummy_instr_id),
.rf_raddr_a_o (rf_raddr_a),
.rf_raddr_b_o (rf_raddr_b),
.rf_waddr_wb_o (rf_waddr_wb),
.rf_we_wb_o (rf_we_wb),
.rf_wdata_wb_ecc_o (rf_wdata_wb_ecc),
.rf_rdata_a_ecc_i (rf_rdata_a_ecc),
.rf_rdata_b_ecc_i (rf_rdata_b_ecc),
.dummy_instr_id_o (dummy_instr_id),
.rf_raddr_a_o (rf_raddr_a),
.rf_raddr_b_o (rf_raddr_b),
.rf_waddr_wb_o (rf_waddr_wb),
.rf_we_wb_o (rf_we_wb),
.rf_wdata_wb_ecc_o(rf_wdata_wb_ecc),
.rf_rdata_a_ecc_i (rf_rdata_a_ecc),
.rf_rdata_b_ecc_i (rf_rdata_b_ecc),
.ic_tag_req_o (ic_tag_req),
.ic_tag_write_o (ic_tag_write),
.ic_tag_addr_o (ic_tag_addr),
.ic_tag_wdata_o (ic_tag_wdata),
.ic_tag_rdata_i (ic_tag_rdata),
.ic_data_req_o (ic_data_req),
.ic_data_write_o (ic_data_write),
.ic_data_addr_o (ic_data_addr),
.ic_data_wdata_o (ic_data_wdata),
.ic_data_rdata_i (ic_data_rdata),
.ic_tag_req_o (ic_tag_req),
.ic_tag_write_o (ic_tag_write),
.ic_tag_addr_o (ic_tag_addr),
.ic_tag_wdata_o (ic_tag_wdata),
.ic_tag_rdata_i (ic_tag_rdata),
.ic_data_req_o (ic_data_req),
.ic_data_write_o(ic_data_write),
.ic_data_addr_o (ic_data_addr),
.ic_data_wdata_o(ic_data_wdata),
.ic_data_rdata_i(ic_data_rdata),
.irq_software_i,
.irq_timer_i,
.irq_external_i,
.irq_fast_i,
.irq_nm_i,
.irq_pending_o (irq_pending),
.irq_pending_o(irq_pending),
.debug_req_i,
.crash_dump_o,
@ -291,9 +291,9 @@ module ibex_top import ibex_pkg::*; #(
`endif
.fetch_enable_i,
.alert_minor_o (core_alert_minor),
.alert_major_o (core_alert_major),
.core_busy_o (core_busy_d)
.alert_minor_o(core_alert_minor),
.alert_major_o(core_alert_major),
.core_busy_o (core_busy_d)
);
/////////////////////////////////
@ -302,63 +302,63 @@ module ibex_top import ibex_pkg::*; #(
if (RegFile == RegFileFF) begin : gen_regfile_ff
ibex_register_file_ff #(
.RV32E ( RV32E ),
.DataWidth ( RegFileDataWidth ),
.DummyInstructions ( DummyInstructions )
.RV32E (RV32E),
.DataWidth (RegFileDataWidth),
.DummyInstructions(DummyInstructions)
) register_file_i (
.clk_i ( clk ),
.rst_ni ( rst_ni ),
.clk_i (clk),
.rst_ni(rst_ni),
.test_en_i ( test_en_i ),
.dummy_instr_id_i ( dummy_instr_id ),
.test_en_i (test_en_i),
.dummy_instr_id_i(dummy_instr_id),
.raddr_a_i ( rf_raddr_a ),
.rdata_a_o ( rf_rdata_a_ecc ),
.raddr_b_i ( rf_raddr_b ),
.rdata_b_o ( rf_rdata_b_ecc ),
.waddr_a_i ( rf_waddr_wb ),
.wdata_a_i ( rf_wdata_wb_ecc ),
.we_a_i ( rf_we_wb )
.raddr_a_i(rf_raddr_a),
.rdata_a_o(rf_rdata_a_ecc),
.raddr_b_i(rf_raddr_b),
.rdata_b_o(rf_rdata_b_ecc),
.waddr_a_i(rf_waddr_wb),
.wdata_a_i(rf_wdata_wb_ecc),
.we_a_i (rf_we_wb)
);
end else if (RegFile == RegFileFPGA) begin : gen_regfile_fpga
ibex_register_file_fpga #(
.RV32E ( RV32E ),
.DataWidth ( RegFileDataWidth ),
.DummyInstructions ( DummyInstructions )
.RV32E (RV32E),
.DataWidth (RegFileDataWidth),
.DummyInstructions(DummyInstructions)
) register_file_i (
.clk_i ( clk ),
.rst_ni ( rst_ni ),
.clk_i (clk),
.rst_ni(rst_ni),
.test_en_i ( test_en_i ),
.dummy_instr_id_i ( dummy_instr_id ),
.test_en_i (test_en_i),
.dummy_instr_id_i(dummy_instr_id),
.raddr_a_i ( rf_raddr_a ),
.rdata_a_o ( rf_rdata_a_ecc ),
.raddr_b_i ( rf_raddr_b ),
.rdata_b_o ( rf_rdata_b_ecc ),
.waddr_a_i ( rf_waddr_wb ),
.wdata_a_i ( rf_wdata_wb_ecc ),
.we_a_i ( rf_we_wb )
.raddr_a_i(rf_raddr_a),
.rdata_a_o(rf_rdata_a_ecc),
.raddr_b_i(rf_raddr_b),
.rdata_b_o(rf_rdata_b_ecc),
.waddr_a_i(rf_waddr_wb),
.wdata_a_i(rf_wdata_wb_ecc),
.we_a_i (rf_we_wb)
);
end else if (RegFile == RegFileLatch) begin : gen_regfile_latch
ibex_register_file_latch #(
.RV32E ( RV32E ),
.DataWidth ( RegFileDataWidth ),
.DummyInstructions ( DummyInstructions )
.RV32E (RV32E),
.DataWidth (RegFileDataWidth),
.DummyInstructions(DummyInstructions)
) register_file_i (
.clk_i ( clk ),
.rst_ni ( rst_ni ),
.clk_i (clk),
.rst_ni(rst_ni),
.test_en_i ( test_en_i ),
.dummy_instr_id_i ( dummy_instr_id ),
.test_en_i (test_en_i),
.dummy_instr_id_i(dummy_instr_id),
.raddr_a_i ( rf_raddr_a ),
.rdata_a_o ( rf_rdata_a_ecc ),
.raddr_b_i ( rf_raddr_b ),
.rdata_b_o ( rf_rdata_b_ecc ),
.waddr_a_i ( rf_waddr_wb ),
.wdata_a_i ( rf_wdata_wb_ecc ),
.we_a_i ( rf_we_wb )
.raddr_a_i(rf_raddr_a),
.rdata_a_o(rf_rdata_a_ecc),
.raddr_b_i(rf_raddr_b),
.rdata_b_o(rf_rdata_b_ecc),
.waddr_a_i(rf_waddr_wb),
.wdata_a_i(rf_wdata_wb_ecc),
.we_a_i (rf_we_wb)
);
end
@ -371,33 +371,33 @@ module ibex_top import ibex_pkg::*; #(
for (genvar way = 0; way < IC_NUM_WAYS; way++) begin : gen_rams_inner
// Tag RAM instantiation
prim_ram_1p #(
.Width (TagSizeECC),
.Depth (IC_NUM_LINES),
.DataBitsPerMask (TagSizeECC)
.Width (TagSizeECC),
.Depth (IC_NUM_LINES),
.DataBitsPerMask(TagSizeECC)
) tag_bank (
.clk_i (clk_i),
.req_i (ic_tag_req[way]),
.cfg_i (ram_cfg_i),
.write_i (ic_tag_write),
.wmask_i ({TagSizeECC{1'b1}}),
.addr_i (ic_tag_addr),
.wdata_i (ic_tag_wdata),
.rdata_o (ic_tag_rdata[way])
.clk_i (clk_i),
.req_i (ic_tag_req[way]),
.cfg_i (ram_cfg_i),
.write_i(ic_tag_write),
.wmask_i({TagSizeECC{1'b1}}),
.addr_i (ic_tag_addr),
.wdata_i(ic_tag_wdata),
.rdata_o(ic_tag_rdata[way])
);
// Data RAM instantiation
prim_ram_1p #(
.Width (LineSizeECC),
.Depth (IC_NUM_LINES),
.DataBitsPerMask (LineSizeECC)
.Width (LineSizeECC),
.Depth (IC_NUM_LINES),
.DataBitsPerMask(LineSizeECC)
) data_bank (
.clk_i (clk_i),
.req_i (ic_data_req[way]),
.cfg_i (ram_cfg_i),
.write_i (ic_data_write),
.wmask_i ({LineSizeECC{1'b1}}),
.addr_i (ic_data_addr),
.wdata_i (ic_data_wdata),
.rdata_o (ic_data_rdata[way])
.clk_i (clk_i),
.req_i (ic_data_req[way]),
.cfg_i (ram_cfg_i),
.write_i(ic_data_write),
.wmask_i({LineSizeECC{1'b1}}),
.addr_i (ic_data_addr),
.wdata_i(ic_data_wdata),
.rdata_o(ic_data_rdata[way])
);
end
@ -643,33 +643,33 @@ module ibex_top import ibex_pkg::*; #(
logic lockstep_alert_minor_local, lockstep_alert_major_local;
ibex_lockstep #(
.PMPEnable ( PMPEnable ),
.PMPGranularity ( PMPGranularity ),
.PMPNumRegions ( PMPNumRegions ),
.MHPMCounterNum ( MHPMCounterNum ),
.MHPMCounterWidth ( MHPMCounterWidth ),
.RV32E ( RV32E ),
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.BranchTargetALU ( BranchTargetALU ),
.ICache ( ICache ),
.ICacheECC ( ICacheECC ),
.BusSizeECC ( BusSizeECC ),
.TagSizeECC ( TagSizeECC ),
.LineSizeECC ( LineSizeECC ),
.BranchPredictor ( BranchPredictor ),
.DbgTriggerEn ( DbgTriggerEn ),
.DbgHwBreakNum ( DbgHwBreakNum ),
.WritebackStage ( WritebackStage ),
.ResetAll ( ResetAll ),
.RndCnstLfsrSeed ( RndCnstLfsrSeed ),
.RndCnstLfsrPerm ( RndCnstLfsrPerm ),
.SecureIbex ( SecureIbex ),
.DummyInstructions ( DummyInstructions ),
.RegFileECC ( RegFileECC ),
.RegFileDataWidth ( RegFileDataWidth ),
.DmHaltAddr ( DmHaltAddr ),
.DmExceptionAddr ( DmExceptionAddr )
.PMPEnable (PMPEnable),
.PMPGranularity (PMPGranularity),
.PMPNumRegions (PMPNumRegions),
.MHPMCounterNum (MHPMCounterNum),
.MHPMCounterWidth (MHPMCounterWidth),
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU (BranchTargetALU),
.ICache (ICache),
.ICacheECC (ICacheECC),
.BusSizeECC (BusSizeECC),
.TagSizeECC (TagSizeECC),
.LineSizeECC (LineSizeECC),
.BranchPredictor (BranchPredictor),
.DbgTriggerEn (DbgTriggerEn),
.DbgHwBreakNum (DbgHwBreakNum),
.WritebackStage (WritebackStage),
.ResetAll (ResetAll),
.RndCnstLfsrSeed (RndCnstLfsrSeed),
.RndCnstLfsrPerm (RndCnstLfsrPerm),
.SecureIbex (SecureIbex),
.DummyInstructions(DummyInstructions),
.RegFileECC (RegFileECC),
.RegFileDataWidth (RegFileDataWidth),
.DmHaltAddr (DmHaltAddr),
.DmExceptionAddr (DmExceptionAddr)
) u_ibex_lockstep (
.clk_i (clk),
.rst_ni (rst_ni),
@ -742,12 +742,12 @@ module ibex_top import ibex_pkg::*; #(
);
prim_buf u_prim_buf_alert_minor (
.in_i(lockstep_alert_minor_local),
.in_i (lockstep_alert_minor_local),
.out_o(lockstep_alert_minor)
);
prim_buf u_prim_buf_alert_major (
.in_i(lockstep_alert_major_local),
.in_i (lockstep_alert_major_local),
.out_o(lockstep_alert_major)
);