[dv] Add matched instruction count to cosim

dv/cosim/cosim.h

@@ -132,6 +132,10 @@ class Cosim {
 
   // Clear internal vector of error descriptions
   virtual void clear_errors() = 0;
+
+  // Returns a count of instructions executed by co-simulator and DUT without
+  // failures.
+  virtual int get_insn_cnt() = 0;
 };
 
 #endif  // COSIM_H_

dv/cosim/cosim_dpi.cc

@@ -92,3 +92,9 @@ void riscv_cosim_write_mem_byte(Cosim *cosim, const svBitVecVal *addr,
   uint8_t byte = d[0] & 0xff;
   cosim->backdoor_write_mem(addr[0], 1, &byte);
 }
+
+int riscv_cosim_get_insn_cnt(Cosim *cosim) {
+  assert(cosim);
+
+  return cosim->get_insn_cnt();
+}

dv/cosim/cosim_dpi.h

@@ -30,6 +30,7 @@ const char *riscv_cosim_get_error(Cosim *cosim, int index);
 void riscv_cosim_clear_errors(Cosim *cosim);
 void riscv_cosim_write_mem_byte(Cosim *cosim, const svBitVecVal *addr,
                                 const svBitVecVal *d);
+int riscv_cosim_get_insn_cnt(Cosim *cosim);
 }
 
 #endif  // COSIM_DPI_H_

dv/cosim/cosim_dpi.svh

@@ -22,3 +22,4 @@ import "DPI-C" function string riscv_cosim_get_error(chandle cosim_handle, int i
 import "DPI-C" function void riscv_cosim_clear_errors(chandle cosim_handle);
 import "DPI-C" function void riscv_cosim_write_mem_byte(chandle cosim_handle, bit [31:0] addr,
   bit [7:0] d);
+import "DPI-C" function int riscv_cosim_get_insn_cnt(chandle cosim_handle);

dv/cosim/spike_cosim.cc

@@ -222,8 +222,14 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
   pending_iside_error = false;
 
   // Errors may have been generated outside of step() (e.g. in
-  // check_mem_access()), return false if there are any.
-  return errors.size() == 0;
+  // check_mem_access()). Only increment insn_cnt and return true if there are
+  // no errors
+  if (errors.size() == 0) {
+    insn_cnt++;
+    return true;
+  }
+
+  return false;
 }
 
 bool SpikeCosim::check_gpr_write(const commit_log_reg_t::value_type &reg_change,
@@ -538,3 +544,5 @@ bool SpikeCosim::pc_is_mret(uint32_t pc) {
 
   return insn == 0x30200073;
 }
+
+int SpikeCosim::get_insn_cnt() { return insn_cnt; }

dv/cosim/spike_cosim.h

@@ -54,6 +54,8 @@ class SpikeCosim : public simif_t, public Cosim {
 
   void on_csr_write(const commit_log_reg_t::value_type &reg_change);
 
+  int insn_cnt;
+
  public:
   SpikeCosim(uint32_t start_pc, uint32_t start_mtvec,
              const std::string &trace_log_path, bool secure_ibex,
@@ -87,6 +89,7 @@ class SpikeCosim : public simif_t, public Cosim {
   void set_iside_error(uint32_t addr) override;
   const std::vector<std::string> &get_errors() override;
   void clear_errors() override;
+  int get_insn_cnt() override;
 };
 
 #endif  // SPIKE_COSIM_H_

dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv

@@ -224,6 +224,9 @@ class ibex_cosim_scoreboard extends uvm_scoreboard;
   function void final_phase(uvm_phase phase);
     super.final_phase(phase);
 
+    `uvm_info(`gfn, $sformatf("Co-simulation matched %d instructions",
+                                riscv_cosim_get_insn_cnt(cosim_handle)), UVM_LOW)
+
     if (cosim_handle) begin
       spike_cosim_release(cosim_handle);
     end