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minor fix again

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davide schiavone 2025-02-27 19:34:31 +01:00
parent 76247da60d
commit b74beda8f1
1 changed files with 6 additions and 5 deletions
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11
rtl/cve2_id_stage.sv
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@ -265,8 +265,6 @@ module cve2_id_stage #(
// CV-X-IF
logic stall_coproc;
logic coproc_done;
///////////////
// ID-EX FSM //
@ -285,6 +283,10 @@ module cve2_id_stage #(
// CV-X-IF
if (XInterface) begin: gen_xif
logic coproc_done;
assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : (illegal_insn_dec ? coproc_done : ex_valid_i);
assign coproc_done = (x_issue_valid_o & x_issue_ready_i & ~x_issue_resp_i.writeback) | (x_result_valid_i & x_result_i.we);
// Issue Interface
@ -312,7 +314,8 @@ module cve2_id_stage #(
logic unused_x_result_valid;
x_result_t unused_x_result;
assign coproc_done = 1'b0;
assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : ex_valid_i;
// Issue Interface
assign x_issue_valid_o = 1'b0;
@ -834,8 +837,6 @@ module cve2_id_stage #(
// Used by ALU to access RS3 if ternary instruction.
assign instr_first_cycle_id_o = instr_first_cycle;
assign multicycle_done = lsu_req_dec ? lsu_resp_valid_i : (illegal_insn_dec ? coproc_done : ex_valid_i);
assign data_req_allowed = instr_first_cycle;
// Without Writeback Stage always stall the first cycle of a load/store.