Adapt Yosys synthesis script to latch based register file and cve2_clock_gate (#125)

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

syn/rtl/cve2_clock_gating.v

@@ -0,0 +1,23 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Example clock gating module for yosys synthesis
+
+module cve2_clock_gate (
+  input  clk_i,
+  input  en_i,
+  input  scan_cg_en_i,
+  output clk_o
+);
+
+  reg en_latch;
+
+  always @* begin
+    if (!clk_i) begin
+      en_latch = en_i | test_en_i;
+    end
+  end
+  assign clk_o = en_latch & clk_i;
+
+endmodule

syn/syn_setup.sh

@@ -0,0 +1,23 @@
+#!/bin/bash
+
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+if [ $# -eq 1 ]; then
+  export LR_SYNTH_OUT_DIR=$1
+elif [ $# -eq 0 ]; then
+  export LR_SYNTH_OUT_DIR_PREFIX="syn_out/cve2"
+  export LR_SYNTH_OUT_DIR=$(date +"${LR_SYNTH_OUT_DIR_PREFIX}_%d_%m_%Y_%H_%M_%S")
+else
+  echo "Usage $0 [synth_out_dir]"
+  exit 1
+fi
+
+export LR_SYNTH_TIMING_RUN=1
+export LR_SYNTH_FLATTEN=1
+
+# SETUP CELL LIBRARY PATH
+# Uncomment the lines below and set the path to an appropriate .lib file
+#export LR_SYNTH_CELL_LIBRARY_PATH=~/src/OpenROAD-flow-scripts/flow/platforms/nangate45/lib/NangateOpenCellLibrary_typical.lib
+export LR_SYNTH_CELL_LIBRARY_NAME=nangate

syn/syn_yosys.sh

@@ -28,6 +28,10 @@ fi
 #-------------------------------------------------------------------------
 source syn_setup.sh
 
+if [ -z "$LR_SYNTH_CELL_LIBRARY_PATH" ]; then
+    error "See syn_setup.sh file for instructions"
+fi
+
 #-------------------------------------------------------------------------
 # use sv2v to convert all SystemVerilog files to Verilog
 #-------------------------------------------------------------------------
@@ -58,9 +62,9 @@ done
 # remove tracer (not needed for synthesis)
 rm -f $LR_SYNTH_OUT_DIR/generated/cve2_tracer.v
 
-# remove the FPGA & register-based register file (because we will use the
-# latch-based one instead)
-rm -f $LR_SYNTH_OUT_DIR/generated/cve2_register_file_ff.v
+# remove the FPGA & latch-based register file (because we will use the
+# register-based one instead)
+rm -f $LR_SYNTH_OUT_DIR/generated/cve2_register_file_latch.v
 rm -f $LR_SYNTH_OUT_DIR/generated/cve2_register_file_fpga.v
 
 yosys -c ./tcl/yosys_run_synth.tcl |& teelog syn || {

syn/tcl/yosys_run_synth.tcl

@@ -14,18 +14,14 @@ if { $lr_synth_timing_run } {
   write_sdc_out $lr_synth_sdc_file_in $lr_synth_sdc_file_out
 }
 
-yosys "read_verilog -defer -sv ./rtl/prim_clock_gating.v $lr_synth_out_dir/generated/*.v"
+yosys "read_verilog -defer -sv ./rtl/cve2_clock_gating.v $lr_synth_out_dir/generated/*.v"
 
 if { $lr_synth_cve2_writeback_stage } {
   yosys "chparam -set WritebackStage 1 $lr_synth_top_module"
 }
 
-yosys "chparam -set RV32B $lr_synth_cve2_bitmanip $lr_synth_top_module"
-
 yosys "chparam -set RV32M $lr_synth_cve2_multiplier $lr_synth_top_module"
 
-yosys "chparam -set RegFile $lr_synth_cve2_regfile $lr_synth_top_module"
-
 yosys "synth $flatten_opt -top $lr_synth_top_module"
 yosys "opt -purge"