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[DV] Fix lint warnings (#397)

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udinator 2019-10-14 10:20:28 -07:00 • committed by GitHub
parent 5f0be50473
commit bbb688a2aa
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10 changed files with 43 additions and 31 deletions
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3
dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf.sv
View file

@ -2,7 +2,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
interface ibex_mem_intf#(ADDR_WIDTH = 32, DATA_WIDTH = 32);
interface ibex_mem_intf#(parameter int ADDR_WIDTH = 32,
parameter int DATA_WIDTH = 32);
logic clock;
logic reset;

4
dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_agent_pkg.sv
View file

@ -9,8 +9,8 @@ package ibex_mem_intf_agent_pkg;
import uvm_pkg::*;
import mem_model_pkg::*;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter int DATA_WIDTH = 32;
parameter int ADDR_WIDTH = 32;
typedef enum { READ, WRITE } rw_e;

4
dv/uvm/common/irq_agent/irq_agent_pkg.sv
View file

@ -8,8 +8,8 @@ package irq_agent_pkg;
import uvm_pkg::*;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter int DATA_WIDTH = 32;
parameter int ADDR_WIDTH = 32;
`include "uvm_macros.svh"
`include "irq_seq_item.sv"

15
dv/uvm/common/mem_model/mem_model.sv
View file

@ -2,14 +2,15 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
class mem_model#(Addr_width = 32, Data_width = 32) extends uvm_object;
class mem_model#(parameter int ADDR_WIDTH = 32,
parameter int DATA_WIDTH = 32) extends uvm_object;
typedef bit [Addr_width-1:0] mem_addr_t;
typedef bit [Data_width-1:0] mem_data_t;
typedef bit [ADDR_WIDTH-1:0] mem_addr_t;
typedef bit [DATA_WIDTH-1:0] mem_data_t;
bit [7:0] system_memory[mem_addr_t];
`uvm_object_param_utils(mem_model#(Addr_width, Data_width))
`uvm_object_param_utils(mem_model#(ADDR_WIDTH, DATA_WIDTH))
function new(string name="");
super.new(name);
@ -23,7 +24,7 @@ class mem_model#(Addr_width = 32, Data_width = 32) extends uvm_object;
$sformatf("Read Mem : Addr[0x%0h], Data[0x%0h]", addr, data), UVM_HIGH)
end
else begin
void'(std::randomize(data));
`DV_CHECK_STD_RANDOMIZE_FATAL(data)
`uvm_error(get_full_name(), $sformatf("read to uninitialzed addr 0x%0h", addr))
end
return data;
@ -37,7 +38,7 @@ class mem_model#(Addr_width = 32, Data_width = 32) extends uvm_object;
function void write(input mem_addr_t addr, mem_data_t data);
bit [7:0] byte_data;
for(int i=0; i<Data_width/8; i++) begin
for(int i=0; i<DATA_WIDTH/8; i++) begin
byte_data = data[7:0];
write_byte(addr+i, byte_data);
data = data >> 8;
@ -46,7 +47,7 @@ class mem_model#(Addr_width = 32, Data_width = 32) extends uvm_object;
function mem_data_t read(mem_addr_t addr);
mem_data_t data;
for(int i=Data_width/8-1; i>=0; i--) begin
for(int i=DATA_WIDTH/8-1; i>=0; i--) begin
data = data << 8;
data[7:0] = read_byte(addr+i);
end

6
dv/uvm/common/utils/clk_if.sv
View file

@ -21,17 +21,17 @@ interface clk_if(inout clk,
endclocking
// Wait for 'n' clocks based of postive clock edge
task wait_clks(int num_clks);
task automatic wait_clks(int num_clks);
repeat (num_clks) @cb;
endtask
// Wait for 'n' clocks based of negative clock edge
task wait_n_clks(int num_clks);
task automatic wait_n_clks(int num_clks);
repeat (num_clks) @cbn;
endtask
// generate mid-test reset
task reset();
task automatic reset();
rst_no = 1'b0;
wait_clks(100);
rst_no = 1'b1;

2
dv/uvm/tb/prim_clock_gating.sv
View file

@ -5,7 +5,7 @@
// Dummy clock gating module compatible with latch-based register file
module prim_clock_gating #(
parameter Impl = "default"
parameter string Impl = "default"
) (
input clk_i,
input en_i,

20
dv/uvm/tests/core_ibex_base_test.sv
View file

@ -53,7 +53,8 @@ class core_ibex_base_test extends uvm_test;
virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
env.data_if_slave_agent.monitor.item_collected_port.connect(this.item_collected_port.analysis_export);
env.data_if_slave_agent.monitor.item_collected_port.connect(
this.item_collected_port.analysis_export);
if (cfg.enable_irq_seq) begin
env.irq_agent.monitor.irq_port.connect(this.irq_collected_port.analysis_export);
end
@ -134,7 +135,8 @@ class core_ibex_base_test extends uvm_test;
forever begin
// The first write to this address is guaranteed to contain the signature type in bits [7:0]
item_collected_port.get(mem_txn);
if (mem_txn.addr == ref_addr && mem_txn.data[7:0] === ref_type && mem_txn.read_write == WRITE) begin
if (mem_txn.addr == ref_addr && mem_txn.data[7:0] === ref_type &&
mem_txn.read_write == WRITE) begin
signature_data = mem_txn.data;
case (ref_type)
// The very first write to the signature address in every test is guaranteed to be a write
@ -163,7 +165,9 @@ class core_ibex_base_test extends uvm_test;
signature_data_q.push_back(mem_txn.data);
end
default: begin
`uvm_fatal(`gfn, $sformatf("The data 0x%0h written to the signature address is formatted incorrectly.", signature_data))
`uvm_fatal(`gfn,
$sformatf("The data 0x%0h written to the signature address is formatted incorrectly.",
signature_data))
end
endcase
return;
@ -188,8 +192,9 @@ class core_ibex_base_test extends uvm_test;
end
begin : wait_timeout
clk_vif.wait_clks(timeout);
`uvm_fatal(`gfn, $sformatf("Did not receive core_status 0x%0x within %0d cycle timeout period",
core_status, timeout))
`uvm_fatal(`gfn,
$sformatf("Did not receive core_status 0x%0x within %0d cycle timeout period",
core_status, timeout))
end
join_any
// Will only get here if we successfully beat the timeout period
@ -211,8 +216,9 @@ class core_ibex_base_test extends uvm_test;
end
begin : wait_timeout
clk_vif.wait_clks(timeout);
`uvm_fatal(`gfn, $sformatf("Did not receive write to csr 0x%0x within %0d cycle timeout period",
csr, timeout))
`uvm_fatal(`gfn,
$sformatf("Did not receive write to csr 0x%0x within %0d cycle timeout period",
csr, timeout))
end
join_any
// Will only get here if we successfully beat the timeout period

4
dv/uvm/tests/core_ibex_seq_lib.sv
View file

@ -33,13 +33,13 @@ class core_base_seq #(type REQ = uvm_sequence_item) extends uvm_sequence#(REQ);
if(!uvm_config_db#(virtual clk_if)::get(null, "", "clk_if", clk_vif)) begin
`uvm_fatal(get_full_name(), "Cannot get clk_if")
end
void'(randomize(delay));
`DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay)
clk_vif.wait_clks(delay);
`uvm_info(get_full_name(), "Starting sequence...", UVM_LOW)
while (!stop_seq) begin
send_req();
iteration_cnt++;
void'(randomize(interval));
`DV_CHECK_MEMBER_RANDOMIZE_FATAL(interval)
clk_vif.wait_clks(interval);
if (num_of_iterations > 0 && iteration_cnt >= num_of_iterations) begin
break;

14
dv/uvm/tests/core_ibex_test_lib.sv
View file

@ -407,7 +407,8 @@ class core_ibex_debug_wfi_test extends core_ibex_directed_test;
vseq.start_debug_single_seq();
// After assserting this signal, core should wake up and jump into debug mode from WFI state
// - next handshake should be a notification that the core is now in debug mode
check_next_core_status(IN_DEBUG_MODE, "Core did not jump into debug mode from WFI state", 1000);
check_next_core_status(IN_DEBUG_MODE, "Core did not jump into debug mode from WFI state",
1000);
// We don't want to trigger debug stimulus for any WFI instructions encountered inside the
// debug rom - those should act as NOP instructions - so we wait until hitting the end of the
// debug rom.
@ -431,7 +432,8 @@ class core_ibex_dret_test extends core_ibex_directed_test;
wait (dut_vif.dret === 1'b1);
// After hitting a dret, the core will jump to the vectored trap handler, which sends a
// handshake write to the bench
check_next_core_status(HANDLING_EXCEPTION, "Core did not jump to vectored exception handler", 1000);
check_next_core_status(HANDLING_EXCEPTION, "Core did not jump to vectored exception handler",
1000);
// The core will receive an illegal instruction handshake after jumping from the vectored trap
// handler to the illegal instruction exception handler
check_next_core_status(ILLEGAL_INSTR_EXCEPTION,
@ -546,8 +548,9 @@ class core_ibex_debug_single_step_test extends core_ibex_directed_test;
wait_for_csr_write(CSR_DPC, 500);
if (signature_data - ret_pc !== 'h2 &&
signature_data - ret_pc !== 'h4) begin
`uvm_fatal(`gfn, $sformatf("DPC value [0x%0x] is not the next instruction after ret_pc [0x%0x]",
signature_data, ret_pc))
`uvm_fatal(`gfn,
$sformatf("DPC value [0x%0x] is not the next instruction after ret_pc [0x%0x]",
signature_data, ret_pc))
end
ret_pc = signature_data;
wait_for_csr_write(CSR_DSCRATCH0, 500);
@ -621,7 +624,8 @@ class core_ibex_mem_error_test extends core_ibex_directed_test;
end
`uvm_info(`gfn, $sformatf("0x%0x", exc_type), UVM_LOW)
end else begin
check_next_core_status(INSTR_FAULT_EXCEPTION, "Core did not register correct memory fault type", 500);
check_next_core_status(INSTR_FAULT_EXCEPTION,
"Core did not register correct memory fault type", 500);
exc_type = EXC_CAUSE_INSTR_ACCESS_FAULT;
end
wait_for_csr_write(CSR_MCAUSE, 750);

2
dv/uvm/tests/core_ibex_vseq.sv
View file

@ -26,7 +26,7 @@ class core_ibex_vseq extends uvm_sequence;
instr_intf_seq = ibex_mem_intf_slave_seq::type_id::create("instr_intf_seq");
data_intf_seq = ibex_mem_intf_slave_seq::type_id::create("data_intf_seq");
if (cfg.enable_irq_seq) begin
irq_single_seq_h = irq_raise_single_seq::type_id::create("irq_seq_single_h");
irq_single_seq_h = irq_raise_single_seq::type_id::create("irq_single_seq_h");
irq_single_seq_h.num_of_iterations = 1;
irq_single_seq_h.max_interval = 1;
irq_single_seq_h.max_delay = 500;