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RiscV: exception controller and CSR core and synthesis update

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This commit is contained in:
Sven Stucki 2015-05-26 00:08:28 +02:00
parent 01caa041c4
commit c0c5b5f8a1
6 changed files with 38 additions and 38 deletions
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5
controller.sv
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@ -320,6 +320,11 @@ module controller
regfile_alu_we = 1'b1;
end
`OPCODE_CUST1: begin // Custom-1 opcode: Flush pipeline
// TODO: Replace with WFI instruction as soon as compiler support available
pipe_flush_o = 1'b1;
end
//////////////////////////////////////
// _ _ _ __ __ ____ ____ //

4
exc_controller.sv
View file

@ -188,7 +188,7 @@ module exc_controller
// execute pending delay slot (l.psync won't have one),
// flush the pipeline and stop
ExcFlush: begin
if (jump_in_id_i == 1'b0)
if (jump_in_id_i == 2'b00)
begin // no delay slot
force_nop_o = 1'b1;
exc_pc_sel_o = 1'b1;
@ -206,7 +206,7 @@ module exc_controller
// an IRQ is present, execute pending delay slots and jump
// to the ISR without flushing the pipeline
ExcIR: begin
if (jump_in_id_i == 1'b0)
if (jump_in_id_i == 2'b00)
begin // no delay slot
// synopsys translate_off
$display("%t: Entering exception routine.", $time);

2
id_stage.sv
View file

@ -696,7 +696,7 @@ module id_stage
.stall_id_i ( stall_id_o ),
.illegal_insn_i ( illegal_insn ),
.trap_insn_i ( trap_insn ),
//.drop_instruction_i ( drop_instruction_o), // TODO: check if needed
.drop_instruction_i ( 1'b0 ),
.pipe_flush_i ( pipe_flush ),
.pc_valid_o ( pc_valid ),
.clear_isr_running_i ( clear_isr_running ),

1
if_stage.sv
View file

@ -135,7 +135,6 @@ module if_stage
else
next_pc = current_pc_if_o;
end
end

6
include/defines.sv
View file

@ -55,6 +55,7 @@
`define OPCODE_CUST1 7'h2b
`define INSTR_CUSTOM0 { {25 {1'b?}}, `OPCODE_CUST0 }
`define INSTR_CUSTOM1 { {25 {1'b?}}, `OPCODE_CUST1 }
`define INSTR_LUI { {25 {1'b?}}, `OPCODE_LUI }
`define INSTR_AUIPC { {25 {1'b?}}, `OPCODE_AUIPC }
`define INSTR_JAL { {25 {1'b?}}, `OPCODE_JAL }
@ -253,6 +254,11 @@ endfunction // prettyPrintInstruction
// |___/ //
////////////////////////////////////////////////////////
`define CSR_IDX_MSCRATCH 0
`define CSR_IDX_MEPC 1
`define CSR_MAX_IDX 1
// Special-Purpose Register Addresses
// see OpenRISC manual p. 22ff
`define SP_GRP_SYS 5'h00

58
riscv_core.sv
View file

@ -152,8 +152,7 @@ module riscv_core
logic sp_we_ex; // Output of ID_stage to EX stage
logic sp_we_wb;
logic [31:0] sp_rdata;
logic [15:0] sp_addr;
logic [11:0] sp_addr;
logic [31:0] sp_wdata;
logic sp_we;
@ -255,6 +254,13 @@ module riscv_core
`endif
// TODO: Temporary assignments while not everything from OR10N is implemented (e.g. debug unit)
assign dbg_dsr = 2'b0;
assign dbg_st_en = 1'b0;
assign dbg_sp_mux = 1'b0;
assign dbg_flush_pipe = 1'b0;
//////////////////////////////////////////////////
// ___ _____ ____ _____ _ ____ _____ //
// |_ _| ___| / ___|_ _|/ \ / ___| ____| //
@ -637,18 +643,17 @@ module riscv_core
.ex_stall_i ( stall_ex )
);
/*
//////////////////////////////////////////////
// ____ ____ ____ //
// / ___|| _ \ | _ \ ___ __ _ ___ //
// \___ \| |_) | | |_) / _ \/ _` / __| //
// ___) | __/ | _ < __/ (_| \__ \ //
// |____/|_| |_| \_\___|\__, |___/ //
// |___/ //
// Special Purpose REGISTERS //
//////////////////////////////////////////////
sp_registers sp_registers_i
//////////////////////////////////////
// ____ ____ ____ //
// / ___/ ___|| _ \ ___ //
// | | \___ \| |_) / __| //
// | |___ ___) | _ <\__ \ //
// \____|____/|_| \_\___/ //
// //
// Control and Status Registers //
//////////////////////////////////////
cs_registers cs_registers_i
(
.clk ( clk ),
.rst_n ( rst_n ),
@ -660,22 +665,8 @@ module riscv_core
// Interface to Special register (SRAM LIKE)
.sp_addr_i ( sp_addr ),
.sp_wdata_i ( sp_wdata ),
.sp_we_i ( sp_we ), // from ex-wb pipe regs
.sp_rdata_o ( sp_rdata ), // to write back stage
// Direct interface with MUL-ALU and Controller
// Flag
.flag_i ( alu_flag_ex ), // comparison flag
// Overflow and Carry - From ALU
.carry_i ( carry_ex ),
.overflow_i ( overflow_ex ),
// From the controller
.set_flag_i ( set_flag_ex ), // From EX stage
.set_carry_i ( set_carry_fw_ex ), // From EX stage
.set_overflow_i ( set_overflow_fw_ex ), // From EX stage
.sp_we_i ( sp_we ),
.sp_rdata_o ( sp_rdata ),
// Stall direct write
.enable_direct_write_i ( stall_wb ),
@ -701,11 +692,7 @@ module riscv_core
.irq_enable_o ( irq_enable ),
.npc_o ( dbg_npc ), // PC from debug unit
.set_npc_o ( dbg_set_npc ), // set PC to new value
.flag_fw_o ( sr_flag_fw ),
.flag_o ( sr_flag ),
.carry_o ( carry_sp )
.set_npc_o ( dbg_set_npc ) // set PC to new value
);
// Mux for SPR access through Debug Unit
@ -715,6 +702,8 @@ module riscv_core
assign dbg_rdata = (dbg_sp_mux == 1'b0) ? dbg_reg_rdata : sp_rdata;
/*
//////////////////////////////////////////////
// Hardware Loop Registers //
//////////////////////////////////////////////
@ -849,6 +838,7 @@ module riscv_core
32'h00_00_00_13: printMnemonic("NOP");
// Regular opcodes
`INSTR_CUSTOM0: printMnemonic("CUSTOM0");
`INSTR_CUSTOM1: printMnemonic("CUSTOM1");
`INSTR_LUI: printIInstr("LUI");
`INSTR_AUIPC: printIInstr("AUIPC");
`INSTR_JAL: printUJInstr("JAL");