mirror of
https://github.com/openhwgroup/cve2.git
synced 2025-04-23 05:27:30 -04:00
Allow nested interrupts and save current value of MSTATUS to MESTATUS
upon entering an interrupt handler
This commit is contained in:
Andreas Traber
parent
d99c3c9f24
commit
c39e27f3ac
8 changed files with 120 additions and 71 deletions
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@ -71,7 +71,8 @@ module riscv_controller
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input logic trap_hit_i, // a trap was hit, so we have to flush EX and WB
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output logic save_pc_id_o,
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output logic exc_save_id_o,
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output logic exc_restore_id_o,
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// Debug Unit Signals
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input logic dbg_stall_i, // Pipeline stall is requested
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@ -158,23 +159,24 @@ module riscv_controller
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always_comb
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begin
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// Default values
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instr_req_o = 1'b1;
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instr_req_o = 1'b1;
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exc_ack_o = 1'b0;
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save_pc_id_o = 1'b0;
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exc_ack_o = 1'b0;
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exc_save_id_o = 1'b0;
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exc_restore_id_o = 1'b0;
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pc_mux_o = `PC_BOOT;
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pc_set_o = 1'b0;
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jump_done = jump_done_q;
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pc_mux_o = `PC_BOOT;
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pc_set_o = 1'b0;
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jump_done = jump_done_q;
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ctrl_fsm_ns = ctrl_fsm_cs;
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ctrl_fsm_ns = ctrl_fsm_cs;
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core_busy_o = 1'b1;
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is_decoding_o = 1'b0;
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core_busy_o = 1'b1;
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is_decoding_o = 1'b0;
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halt_if_o = 1'b0;
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halt_id_o = 1'b0;
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dbg_trap_o = 1'b0;
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halt_if_o = 1'b0;
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halt_id_o = 1'b0;
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dbg_trap_o = 1'b0;
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unique case (ctrl_fsm_cs)
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// We were just reset, wait for fetch_enable
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@ -227,7 +229,7 @@ module riscv_controller
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// TODO: This assumes that the pipeline is always flushed before
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// going to sleep.
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save_pc_id_o = 1'b1;
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exc_save_id_o = 1'b1;
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end
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end
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@ -266,7 +268,7 @@ module riscv_controller
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exc_ack_o = 1'b1;
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halt_id_o = 1'b1; // we don't want to propagate this instruction to EX
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save_pc_id_o = 1'b1;
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exc_save_id_o = 1'b1;
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// we don't have to change our current state here as the prefetch
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// buffer is automatically invalidated, thus the next instruction
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@ -276,8 +278,9 @@ module riscv_controller
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end
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if (eret_insn_i) begin
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pc_mux_o = `PC_ERET;
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pc_set_o = 1'b1;
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pc_mux_o = `PC_ERET;
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pc_set_o = 1'b1;
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exc_restore_id_o = 1'b1;
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end
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// handle WFI instruction, flush pipeline and (potentially) go to
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@ -55,10 +55,11 @@ module riscv_cs_registers
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// Interrupts
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output logic irq_enable_o,
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output logic [31:0] epcr_o,
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output logic [31:0] mepc_o,
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input logic [31:0] curr_pc_id_i,
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input logic save_pc_id_i,
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input logic exc_save_i,
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input logic exc_restore_i,
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input logic [5:0] exc_cause_i,
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input logic save_exc_cause_i,
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@ -115,17 +116,16 @@ module riscv_cs_registers
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logic is_pcer;
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logic is_pcmr;
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// Generic CSRs
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logic [31:0] mepc_q, mepc_n;
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// CSR update logic
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logic [31:0] csr_wdata_int;
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logic [31:0] csr_rdata_int;
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logic csr_we_int;
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// Interrupt control signals
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logic irq_enable, irq_enable_n;
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logic [5:0] exc_cause, exc_cause_n;
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logic [31:0] mepc_q, mepc_n;
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logic [ 0:0] mestatus_q, mestatus_n;
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logic [ 0:0] mstatus_q, mstatus_n;
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logic [ 5:0] exc_cause, exc_cause_n;
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////////////////////////////////////////////
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@ -144,7 +144,7 @@ module riscv_cs_registers
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case (csr_addr_i)
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// mstatus: always M-mode, contains IE bit
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12'h300: csr_rdata_int = {29'b0, 2'b11, irq_enable};
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12'h300: csr_rdata_int = {29'b0, 2'b11, mstatus_q};
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// mepc: exception program counter
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12'h341: csr_rdata_int = mepc_q;
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@ -165,6 +165,8 @@ module riscv_cs_registers
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12'h7B4: csr_rdata_int = hwlp_start_i[1];
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12'h7B5: csr_rdata_int = hwlp_end_i[1];
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12'h7B6: csr_rdata_int = hwlp_cnt_i[1];
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12'h7C0: csr_rdata_int = {29'b0, 2'b11, mestatus_q};
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endcase
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end
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@ -173,14 +175,15 @@ module riscv_cs_registers
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always_comb
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begin
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mepc_n = mepc_q;
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irq_enable_n = irq_enable;
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mestatus_n = mestatus_q;
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mstatus_n = mstatus_q;
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exc_cause_n = exc_cause;
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hwlp_we_o = '0;
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hwlp_regid_o = '0;
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case (csr_addr_i)
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// mstatus: IE bit
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12'h300: if (csr_we_int) irq_enable_n = csr_wdata_int[0];
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12'h300: if (csr_we_int) mstatus_n = csr_wdata_int[0];
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// mepc: exception program counter
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12'h341: if (csr_we_int) mepc_n = csr_wdata_int;
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@ -194,7 +197,24 @@ module riscv_cs_registers
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12'h7B4: if (csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b1; end
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12'h7B5: if (csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b1; end
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12'h7B6: if (csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b1; end
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// mestatus: machine exception status
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12'h7C0: if (csr_we_int) mestatus_n = csr_wdata_int[0];
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endcase
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// exception controller gets priority over other writes
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if (exc_save_i) begin
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mepc_n = curr_pc_id_i;
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mestatus_n = mstatus_q;
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mstatus_n = 1'b0;
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end
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if (save_exc_cause_i)
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exc_cause_n = exc_cause_i;
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if (exc_restore_i) begin
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mstatus_n = mestatus_q;
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end
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end
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assign hwlp_data_o = csr_wdata_int;
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@ -231,8 +251,8 @@ module riscv_cs_registers
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// directly output some registers
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assign irq_enable_o = irq_enable;
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assign epcr_o = mepc_q;
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assign irq_enable_o = mstatus_q[0];
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assign mepc_o = mepc_q;
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// actual registers
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@ -240,25 +260,20 @@ module riscv_cs_registers
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begin
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if (rst_n == 1'b0)
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begin
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irq_enable <= 1'b0;
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mstatus_q <= '0;
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mepc_q <= '0;
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mestatus_q <= '0;
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exc_cause <= '0;
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end
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else
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begin
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// update CSRs
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irq_enable <= irq_enable_n;
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mstatus_q <= mstatus_n;
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// exception controller gets priority over other writes
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if (save_pc_id_i == 1'b1)
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mepc_q <= curr_pc_id_i;
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else
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mepc_q <= mepc_n;
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mepc_q <= mepc_n;
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mestatus_q <= mestatus_n;
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if (save_exc_cause_i)
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exc_cause <= exc_cause_i;
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else
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exc_cause <= exc_cause_n;
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exc_cause <= exc_cause_n;
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end
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end
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@ -18,9 +18,10 @@ as possible and avoid any overhead that we do not explicitely need.
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00 & 11 & 01 & 000001 & 0x341 & MEPC & R/W & Machine exception program counter \\ \hline
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00 & 11 & 01 & 000010 & 0x342 & MCAUSE & R/W & Machine trap cause \\ \hline
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01 & 11 & 00 & 0XXXXX & 0x780 - 0x79F & PCCRs & R/W & Performance Counter Counter Registers \\ \hline
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01 & 11 & 10 & 200000 & 0x7A0 & PCER & R/W & Performance Counter Enable Register \\ \hline
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01 & 11 & 10 & 100000 & 0x7A0 & PCER & R/W & Performance Counter Enable Register \\ \hline
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01 & 11 & 10 & 100001 & 0x7A1 & PCMR & R/W & Performance Counter Mode Register \\ \hline
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01 & 11 & 10 & 110XXX & 0x7B0 - 0x7B6 & HWLP & R/W & Hardware Loop Registers \\ \hline
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01 & 11 & 10 & 111000 & 0x7C0 & MESTATUS & R/W & Machine exception Status Register \\ \hline
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11 & 11 & 00 & 000000 & 0xF00 & MCPUID & R & CPU description \\ \hline
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11 & 11 & 00 & 000001 & 0xF01 & MIMPID & R & Vendor ID and version number \\ \hline
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11 & 11 & 00 & 010000 & 0xF10 & MHARTID & R & Hardware Thread ID \\ \bottomrule
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@ -41,6 +42,28 @@ as possible and avoid any overhead that we do not explicitely need.
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}
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Note that \signal{PRV[1:0]} is statically \signal{2'b11} and cannot be altered (read-only).
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When en exception is encountered, \signal{Interrupt Enable} will be set to
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\signal{1'b0}. When the \signal{eret} instruction is executed, the original
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value of \signal{Interrupt Enable} will be restored, as \signal{MESTATUS} will
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replace \signal{MSTATUS}.
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If you want to enable interrupt handling in your exception hanlder, set the
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\signal{Interrupt Enable} to \signal{1'b1} inside your handler code.
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\subsection{MESTATUS}
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\csrDesc{0x7C0}{0x0000\_0006}{MESTATUS}{
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\begin{bytefield}[endianness=big,bitheight=60pt]{32}
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\bitheader{31,2,1,0} \\
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\bitbox{29}{ Unused }
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\bitbox{2}{\rotatebox{90}{\tiny PRV[1:0] }}
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\bitbox{1}{\rotatebox{90}{\tiny Interrupt Enable }}
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\end{bytefield}
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}
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Note that \signal{PRV[1:0]} is statically \signal{2'b11} and cannot be altered (read-only).
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When an exception is encountered, the current value of \signal{MSTATUS} is saved
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in \signal{MESTATUS}. When an \instr{eret} instruction is executed, the value
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from \signal{MESTATUS} replaces the \signal{MSTATUS} register.
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\subsection{MEPC}
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@ -52,9 +75,9 @@ Note that \signal{PRV[1:0]} is statically \signal{2'b11} and cannot be altered (
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}
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When an exception is encountered, the current program counter is saved in
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\signal{mepc} and the core jumps to the exception address.
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When an \instr{eret} instruction is executed, the value from \signal{mepc}
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replaces the current program counter.
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\signal{MEPC}, and the core jumps to the exception address. When an \instr{eret}
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instruction is executed, the value from \signal{MEPC} replaces the current
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program counter.
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\subsection{MCAUSE}
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\csrDesc{0x341}{0x0000\_0000}{MCAUSE}{
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@ -29,7 +29,7 @@ exception/interrupt.
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interrupt lines. Interrupts can only be enabled/disabled on a global basis and
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not individually. It is assumed that there is an event/interrupt controller
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outside of the core that performs masking and buffering of the interrupt lines.
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The global interrupt enable is done via the CSR register \signal{mstatus}.
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The global interrupt enable is done via the CSR register \signal{MSTATUS}.
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\section{Exceptions}
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@ -38,16 +38,21 @@ exceptions and ecall instruction exceptions can not be disabled and are always
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active.
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The illegal instruction exception and the load and store invalid memory access
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exceptions are precise exceptions, i.e. the value of \signal{mepc} will be the
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exceptions are precise exceptions, i.e. the value of \signal{MEPC} will be the
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instruction address that caused it.
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\section{Handling}
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\rvcore does not support nested interrupt/exception handling. Exceptions inside
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interrupt/exception handlers are ignored and thus a user must ensure that such
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a situation does not happen, as otherwise the behaviour is undefined.
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\rvcore does support nested interrupt/exception handling. Exceptions inside
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interrupt/exception handlers cause another exception, thus exceptions during the
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critical part of your exception handlers, i.e. before having saved the
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\signal{MEPC} and \signal{MESTATUS} registers, will cause those register to be
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overwritten.
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Interrupts during interrupt/exception handlers are disabled by default, but can
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be explicitely enabled if desired.
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Upon executing an \instr{eret} instruction, the core jumps to the program
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counter saved in the CSR register \signal{mepc}. When entering an
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interrupt/exception handler, the core sets \signal{mepc} to the current program
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counter.
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counter saved in the CSR register \signal{MEPC} and restores the value of
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register \signal{MESTATUS} to \signal{MSTATUS}. When entering an
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interrupt/exception handler, the core sets \signal{MEPC} to the current program
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counter and saves the current value of \signal{MSTATUS} in \signal{MESTATUS}.
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@ -64,7 +64,7 @@ module riscv_exc_controller
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);
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enum logic [1:0] { IDLE, WAIT_CONTROLLER, IN_ISR } exc_ctrl_cs, exc_ctrl_ns;
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enum logic [0:0] { IDLE, WAIT_CONTROLLER } exc_ctrl_cs, exc_ctrl_ns;
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logic req_int;
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logic [1:0] pc_mux_int, pc_mux_int_q;
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@ -173,7 +173,7 @@ module riscv_exc_controller
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if (ack_i) begin
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save_cause_o = 1'b1;
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exc_ctrl_ns = IN_ISR;
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exc_ctrl_ns = IDLE;
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end
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end
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end
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@ -184,16 +184,10 @@ module riscv_exc_controller
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if (ack_i) begin
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save_cause_o = 1'b1;
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exc_ctrl_ns = IN_ISR;
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exc_ctrl_ns = IDLE;
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end
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end
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IN_ISR:
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begin
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if (eret_insn_i)
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exc_ctrl_ns = IDLE;
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end
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default:
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begin
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exc_ctrl_ns = IDLE;
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@ -140,7 +140,8 @@ module riscv_id_stage
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output logic [5:0] exc_cause_o,
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output logic save_exc_cause_o,
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output logic save_pc_id_o,
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output logic exc_save_id_o,
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output logic exc_restore_id_o,
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input logic lsu_load_err_i,
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input logic lsu_store_err_i,
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@ -714,7 +715,8 @@ module riscv_id_stage
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.exc_ack_o ( exc_ack ),
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.trap_hit_i ( trap_hit ),
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.save_pc_id_o ( save_pc_id_o ),
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.exc_save_id_o ( exc_save_id_o ),
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.exc_restore_id_o ( exc_restore_id_o ),
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// Debug Unit Signals
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.dbg_stall_i ( dbg_stall_i ),
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@ -190,11 +190,12 @@ module riscv_core
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// Interrupts
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logic irq_enable;
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logic [31:0] epcr;
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logic [31:0] mepc;
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logic [5:0] exc_cause;
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logic save_exc_cause;
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logic save_pc_id;
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logic exc_save_id;
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logic exc_restore_id;
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// Hardware loop controller signals
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@ -280,7 +281,7 @@ module riscv_core
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// control signals
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.clear_instr_valid_i ( clear_instr_valid ),
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.pc_set_i ( pc_set ),
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.exception_pc_reg_i ( epcr ), // exception return address
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.exception_pc_reg_i ( mepc ), // exception return address
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.pc_mux_i ( pc_mux_id ), // sel for pc multiplexer
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.exc_pc_mux_i ( exc_pc_mux_id ),
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.exc_vec_pc_mux_i ( exc_vec_pc_mux_id ),
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@ -425,7 +426,8 @@ module riscv_core
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.irq_enable_i ( irq_enable ), // global interrupt enable
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.exc_cause_o ( exc_cause ),
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.save_exc_cause_o ( save_exc_cause ),
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.save_pc_id_o ( save_pc_id ), // control signal to save pc
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.exc_save_id_o ( exc_save_id ), // control signal to save pc
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.exc_restore_id_o ( exc_restore_id ), // control signal to restore pc
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.lsu_load_err_i ( lsu_load_err ),
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.lsu_store_err_i ( lsu_store_err ),
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@ -611,10 +613,11 @@ module riscv_core
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// Interrupt related control signals
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.irq_enable_o ( irq_enable ),
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.epcr_o ( epcr ),
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.mepc_o ( mepc ),
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.curr_pc_id_i ( current_pc_id ), // from IF stage
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.save_pc_id_i ( save_pc_id ),
|
||||
.exc_save_i ( exc_save_id ),
|
||||
.exc_restore_i ( exc_restore_id ),
|
||||
|
||||
.exc_cause_i ( exc_cause ),
|
||||
.save_exc_cause_i ( save_exc_cause ),
|
||||
|
|
@ -775,6 +778,7 @@ module riscv_core
|
|||
.is_compressed ( is_compressed_id ),
|
||||
.id_valid ( id_stage_i.id_valid_o ),
|
||||
.is_decoding ( id_stage_i.is_decoding_o ),
|
||||
.is_illegal ( id_stage_i.illegal_insn_dec ),
|
||||
.pipe_flush ( id_stage_i.controller_i.pipe_flush_i ),
|
||||
|
||||
.ex_valid ( ex_valid ),
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@ module riscv_simchecker
|
|||
input logic is_compressed,
|
||||
input logic id_valid,
|
||||
input logic is_decoding,
|
||||
input logic is_illegal,
|
||||
input logic pipe_flush,
|
||||
|
||||
input logic ex_valid,
|
||||
|
|
@ -239,8 +240,10 @@ module riscv_simchecker
|
|||
while(1) begin
|
||||
@(negedge clk);
|
||||
|
||||
// special case for WFI because we don't wait for unstalling there
|
||||
if ((id_valid && is_decoding) || pipe_flush)
|
||||
// - special case for WFI because we don't wait for unstalling there
|
||||
// - special case for illegal instructions, since they will not go through
|
||||
// the pipe
|
||||
if ((id_valid && is_decoding) || pipe_flush || (is_decoding && is_illegal))
|
||||
begin
|
||||
trace = new ();
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue