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Keep Physical Memory Protection as local parameter (#48)

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Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
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christian-herber-nxp 2023-02-06 14:03:02 +01:00 • committed by GitHub
parent ffa6ab4154
commit c40138f0ef
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5 changed files with 8 additions and 21 deletions
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9
doc/02_user/integration.rst
View file

@ -15,9 +15,6 @@ Instantiation Template
.. code-block:: verilog
cve2_top #(
.PMPEnable ( 0 ),
.PMPGranularity ( 0 ),
.PMPNumRegions ( 4 ),
.MHPMCounterNum ( 0 ),
.MHPMCounterWidth ( 40 ),
.RV32E ( 0 ),
@ -93,12 +90,6 @@ Parameters
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| Name | Type/Range | Default | Description |
+==============================+=====================+============+=======================================================================+
| ``PMPEnable`` | bit | 0 | Enable PMP support |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``PMPGranularity`` | int (0..31) | 0 | Minimum granularity of PMP address matching |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``PMPNumRegions`` | int (1..16) | 4 | Number implemented PMP regions (ignored if PMPEnable == 0) |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``MHPMCounterNum`` | int (0..10) | 0 | Number of performance monitor event counters |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``MHPMCounterWidth`` | int (64..1) | 40 | Bit width of performance monitor event counters |

2
doc/03_reference/cs_registers.rst
View file

@ -329,7 +329,7 @@ Reset Value: ``0x0000_0000_0000_0000``
Note that the reset value means PMP behavior out of reset matches the RISC-V Privileged Architecture.
A write to ``mseccfg`` is required to change it.
Note ``mseccfgh`` reads as all 0s and ignores all writes.
Any access to ``mseccfg`` or ``mseccfgh`` when using an Ibex configuration without PMP (``PMPEnable`` is 0) will trigger an illegal instruction exception.
Any access to ``mseccfg`` or ``mseccfgh`` when using an Ibex configuration without PMP (localparam ``PMPEnable`` set to 0) will trigger an illegal instruction exception.
.. _csr-tselect:

4
doc/03_reference/pmp.rst
View file

@ -4,10 +4,10 @@ Physical Memory Protection (PMP)
================================
The Physical Memory Protection (PMP) unit implements region-based memory access checking in-accordance with the RISC-V Privileged Specification, version 1.11 and includes the Trusted Execution Environment (TEE) working group proposal `PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp) version 0.9.3 <https://github.com/riscv/riscv-tee/blob/61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf>`_.
The following configuration parameters are available to control PMP checking:
The following local parameters are available to control PMP checking:
+----------------+---------------+----------------------------------------------------------+
| Parameter | Default value | Description |
| localparam | Default value | Description |
+================+===============+==========================================================+
| PMPEnable | 0 | PMP support enabled |
+----------------+---------------+----------------------------------------------------------+

8
rtl/cve2_top.sv
View file

@ -13,9 +13,6 @@
* Top level module of the ibex RISC-V core
*/
module cve2_top import cve2_pkg::*; #(
parameter bit PMPEnable = 1'b0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
parameter int unsigned MHPMCounterNum = 0,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit RV32E = 1'b0,
@ -146,6 +143,11 @@ module cve2_top import cve2_pkg::*; #(
localparam int unsigned NumAddrScrRounds = ICacheScramble ? 2 : 0;
localparam int unsigned NumDiffRounds = NumAddrScrRounds;
// Physical Memory Protection
localparam bit PMPEnable = 1'b0;
localparam int unsigned PMPGranularity = 0;
localparam int unsigned PMPNumRegions = 4;
// Clock signals
logic clk;
logic core_busy_d, core_busy_q;

6
rtl/cve2_top_tracing.sv
View file

@ -7,9 +7,6 @@
*/
module cve2_top_tracing import cve2_pkg::*; #(
parameter bit PMPEnable = 1'b0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
parameter int unsigned MHPMCounterNum = 0,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit RV32E = 1'b0,
@ -137,9 +134,6 @@ module cve2_top_tracing import cve2_pkg::*; #(
assign unused_rvfi_ext_mcycle = rvfi_ext_mcycle;
cve2_top #(
.PMPEnable ( PMPEnable ),
.PMPGranularity ( PMPGranularity ),
.PMPNumRegions ( PMPNumRegions ),
.MHPMCounterNum ( MHPMCounterNum ),
.MHPMCounterWidth ( MHPMCounterWidth ),
.RV32E ( RV32E ),