mirror of
https://github.com/openhwgroup/cve2.git
synced 2025-04-22 04:57:25 -04:00
[DV] Add Verilator memory initialization from ELF
Support initialization of memory by loading content from ELF files. All segments of the ELF file with the type `PT_LOAD` are merged into a temporary buffer and then forwarded to a predefined memory. This is an addition for setting the memories with VMEM files. Memories must implement `simutil_verilator_set_mem` to support the setting of values with a width of 32 bits. A return value of 0 must indicate a successful operation and 1 an error. Memories are defined by a call to `RegisterMemoryArea()` before the execution of the simulation, at which point the arguments are parsed and the initialization is started. The memories are identified by unique name. The design specific location is used to set the SystemVerilog scope. Registered memories can be printed by using `-l list`. The unique name is used for `-l name,file.elf` together with the file path. An optional part of the argument is the type of the file, `elf` or `vmem`, and if not provided it is attempted to detect the type by looking at the file extension. The memory specific arguments which already existed accept now also ELF files. They use predefined names and are included to keep the interface stable. Contents of an ELF segment which has a bigger memory size than file size are not set. This is typically required for BSS sections for zero-ing the memory.
This commit is contained in:
Tobias Wölfel
Philipp Wagner
parent
11749c7e4d
commit
ce7e38351e
11 changed files with 516 additions and 229 deletions
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@ -45,6 +45,7 @@ jobs:
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flex \
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bison \
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curl \
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libelf-dev \
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&& sudo pip3 install -U six fusesoc
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displayName: Install dependencies
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@ -2,36 +2,20 @@
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#include "Vtb_cs_registers.h"
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#include "verilated_toplevel.h"
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#include "verilator_sim_ctrl.h"
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tb_cs_registers *top;
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VerilatorSimCtrl *simctrl;
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// dummy definition since this DPI call doesn't exist
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// TODO : remove this - see Ibex #317
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extern "C" {
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void simutil_verilator_memload(const char *file) {}
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int simutil_verilator_set_mem(int index, const svLogicVecVal *val) { return 1; }
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}
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int main(int argc, char **argv) {
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int retcode = 0;
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// init top verilog instance
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top = new tb_cs_registers;
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// Create SimCtrl instance
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simctrl = new VerilatorSimCtrl(top, top->clk_i, top->in_rst_ni,
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VerilatorSimCtrlFlags::ResetPolarityNegative);
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tb_cs_registers top;
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VerilatorSimCtrl simctrl(top, top.clk_i, top.in_rst_ni,
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VerilatorSimCtrlFlags::ResetPolarityNegative);
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// Setup the simulation
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retcode = simctrl->SetupSimulation(argc, argv);
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if (!retcode) {
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// Run the simulation
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simctrl->RunSimulation();
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}
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delete top;
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delete simctrl;
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return retcode;
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return simctrl.Exec(argc, argv);
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}
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@ -109,7 +109,7 @@ targets:
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- '--trace-params'
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- '--trace-max-array 1024'
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- '-CFLAGS "-std=c++14 -Wall -DTOPLEVEL_NAME=tb_cs_registers -DVM_TRACE_FMT_FST -g"'
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- '-LDFLAGS "-pthread -lutil"'
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- '-LDFLAGS "-pthread -lutil -lelf"'
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- "-Wall"
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- "-Wno-PINCONNECTEMPTY"
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# XXX: Cleanup all warnings and remove this option
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@ -2,36 +2,15 @@
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#include <signal.h>
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#include <iostream>
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#include "verilated_toplevel.h"
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#include "verilator_sim_ctrl.h"
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ibex_riscv_compliance *top;
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VerilatorSimCtrl *simctrl;
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int main(int argc, char **argv) {
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int retcode;
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top = new ibex_riscv_compliance;
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simctrl = new VerilatorSimCtrl(top, top->IO_CLK, top->IO_RST_N,
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VerilatorSimCtrlFlags::ResetPolarityNegative);
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ibex_riscv_compliance top;
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VerilatorSimCtrl simctrl(top, top.IO_CLK, top.IO_RST_N,
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VerilatorSimCtrlFlags::ResetPolarityNegative);
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// Setup simctrl
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retcode = simctrl->SetupSimulation(argc, argv);
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if (retcode != 0) {
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goto free_return;
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}
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simctrl.RegisterMemoryArea("ram", "TOP.ibex_riscv_compliance.u_ram");
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// Initialize RAM
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simctrl->InitRam("TOP.ibex_riscv_compliance.u_ram");
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// Run the simulation
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simctrl->RunSimulation();
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free_return:
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delete top;
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delete simctrl;
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return retcode;
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return simctrl.Exec(argc, argv);
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}
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@ -51,7 +51,7 @@ targets:
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- '--trace-params'
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- '--trace-max-array 1024'
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- '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_riscv_compliance -g"'
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- '-LDFLAGS "-pthread -lutil"'
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- '-LDFLAGS "-pthread -lutil -lelf"'
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- "-Wall"
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- "-Wno-PINCONNECTEMPTY"
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# XXX: Cleanup all warnings and remove this option
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@ -7,6 +7,6 @@
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TOPLEVEL_NAME &VerilatedToplevel::dut() {
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// The static_cast below is generally unsafe, but we know the types involved.
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// It's safe for these.
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TOPLEVEL_NAME &dut = static_cast<TOPLEVEL_NAME&>(*this);
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TOPLEVEL_NAME &dut = static_cast<TOPLEVEL_NAME &>(*this);
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return dut;
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}
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@ -4,22 +4,31 @@
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#include "verilator_sim_ctrl.h"
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#include <fcntl.h>
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#include <gelf.h>
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#include <getopt.h>
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#include <libelf.h>
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#include <signal.h>
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#include <sys/stat.h>
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#include <unistd.h>
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#include <vltstd/svdpi.h>
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#include <iostream>
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#include <map>
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#include <utility>
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// This is defined by Verilator and passed through the command line
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#ifndef VM_TRACE
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#define VM_TRACE 0
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#endif
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// Static pointer to a single simctrl instance
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// used by SignalHandler
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static VerilatorSimCtrl *simctrl;
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struct BufferDesc {
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uint8_t *data;
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size_t length;
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};
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// Static pointer to a single simctrl instance used by SignalHandler
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static VerilatorSimCtrl *simctrl = nullptr;
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static void SignalHandler(int sig) {
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if (!simctrl) {
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@ -56,18 +65,16 @@ double sc_time_stamp() {
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// DPI Exports
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extern "C" {
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extern void simutil_verilator_memload(const char *file);
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extern int simutil_verilator_set_mem(int index, const svLogicVecVal *val);
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}
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VerilatorSimCtrl::VerilatorSimCtrl(VerilatedToplevel *top, CData &sig_clk,
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VerilatorSimCtrl::VerilatorSimCtrl(VerilatedToplevel &top, CData &sig_clk,
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CData &sig_rst, VerilatorSimCtrlFlags flags)
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: top_(top),
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sig_clk_(sig_clk),
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sig_rst_(sig_rst),
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flags_(flags),
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time_(0),
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init_rom_(false),
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init_ram_(false),
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init_flash_(false),
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tracing_enabled_(false),
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tracing_enabled_changed_(false),
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tracing_ever_enabled_(false),
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@ -80,13 +87,22 @@ VerilatorSimCtrl::VerilatorSimCtrl(VerilatedToplevel *top, CData &sig_clk,
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term_after_cycles_(0),
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callback_(nullptr) {}
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int VerilatorSimCtrl::SetupSimulation(int argc, char **argv) {
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int retval;
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// Setup the signal handler for this instance
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int VerilatorSimCtrl::Exec(int argc, char **argv) {
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RegisterSignalHandler();
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// Parse the command line argumanets
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if (!ParseCommandArgs(argc,argv,retval)) {
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return retval;
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bool exit_app = false;
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if (!ParseCommandArgs(argc, argv, exit_app)) {
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return 1;
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}
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if (exit_app) {
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// Successful exit requested by command argument parsing
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return 0;
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}
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RunSimulation();
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if (!WasSimulationSuccessful()) {
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return 1;
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}
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return 0;
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}
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@ -97,7 +113,6 @@ void VerilatorSimCtrl::RunSimulation() {
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std::cout << "Tracing can be toggled by sending SIGUSR1 to this process:"
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<< std::endl
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<< "$ kill -USR1 " << getpid() << std::endl;
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}
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// Run the simulation
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Run();
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@ -107,7 +122,7 @@ void VerilatorSimCtrl::RunSimulation() {
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if (TracingEverEnabled()) {
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std::cout << std::endl
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<< "You can view the simulation traces by calling" << std::endl
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<< "$ gtkwave " << GetSimulationFileName() << std::endl;
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<< "$ gtkwave " << GetTraceFileName() << std::endl;
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}
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}
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@ -151,98 +166,241 @@ bool VerilatorSimCtrl::TraceOff() {
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}
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void VerilatorSimCtrl::PrintHelp() const {
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std::cout << "Execute a simulation model for " << top_->name()
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std::cout << "Execute a simulation model for " << top_.name()
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<< "\n"
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"\n";
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if (tracing_possible_) {
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std::cout << "-t|--trace Write trace file from the start\n";
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std::cout << "-t|--trace\n"
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" Write a trace file from the start\n\n";
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}
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std::cout << "-r|--rominit=VMEMFILE Initialize the ROM with VMEMFILE\n"
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"-m|--raminit=VMEMFILE Initialize the RAM with VMEMFILE\n"
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"-f|--flashinit=VMEMFILE Initialize the FLASH with VMEMFILE\n"
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"-c|--term-after-cycles=N Terminate simulation after N cycles\n"
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"-h|--help Show help\n"
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"\n"
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std::cout << "-r|--rominit=FILE\n"
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" Initialize the ROM with FILE (elf/vmem)\n\n"
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"-m|--raminit=FILE\n"
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" Initialize the RAM with FILE (elf/vmem)\n\n"
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"-f|--flashinit=FILE\n"
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" Initialize the FLASH with FILE (elf/vmem)\n\n"
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"-l|--meminit=NAME,FILE[,TYPE]\n"
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" Initialize memory region NAME with FILE [of TYPE]\n"
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" TYPE is either 'elf' or 'vmem'\n\n"
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"-l list|--meminit=list\n"
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" Print registered memory regions\n\n"
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"-c|--term-after-cycles=N\n"
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" Terminate simulation after N cycles\n\n"
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"-h|--help\n"
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" Show help\n\n"
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"All further arguments are passed to the design and can be used "
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"in the \n"
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"design, e.g. by DPI modules.\n";
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"in the design, e.g. by DPI modules.\n";
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}
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void VerilatorSimCtrl::InitRom(std::string rom) {
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if (!init_rom_) {
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return;
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bool VerilatorSimCtrl::RegisterMemoryArea(const std::string name,
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const std::string location) {
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MemArea mem = {.name = name, .location = location};
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auto ret = mem_register_.emplace(name, mem);
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if (ret.second == false) {
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std::cerr << "ERROR: Can not register \"" << name << "\" at: \"" << location
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<< "\" (Previously defined at: \"" << ret.first->second.location
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<< "\")" << std::endl;
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return false;
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}
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return true;
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}
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MemImageType VerilatorSimCtrl::GetMemImageTypeByName(const std::string name) {
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if (name.compare("elf") == 0) {
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return kMemImageElf;
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}
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if (name.compare("vmem") == 0) {
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return kMemImageVmem;
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}
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return kMemImageUnknown;
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}
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MemImageType VerilatorSimCtrl::DetectMemImageType(const std::string filepath) {
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size_t ext_pos = filepath.find_last_of(".");
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std::string ext = filepath.substr(ext_pos + 1);
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if (ext_pos == std::string::npos) {
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// Assume ELF files if no file extension is given.
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// TODO: Make this more robust by actually checking the file contents.
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return kMemImageElf;
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}
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return GetMemImageTypeByName(ext);
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}
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void VerilatorSimCtrl::PrintMemRegions() const {
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std::cout << "Registered memory regions:" << std::endl;
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for (const auto &m : mem_register_) {
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std::cout << "\t'" << m.second.name << "' at location: '"
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<< m.second.location << "'" << std::endl;
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}
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}
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bool VerilatorSimCtrl::ParseMemArg(std::string mem_argument, std::string &name,
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std::string &filepath, MemImageType &type) {
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std::array<std::string, 3> args;
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size_t pos = 0;
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size_t end_pos = 0;
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size_t i;
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for (i = 0; i < 3; ++i) {
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end_pos = mem_argument.find(",", pos);
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// Check for possible exit conditions
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if (pos == end_pos) {
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std::cerr << "ERROR: empty field in: " << mem_argument << std::endl;
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return false;
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}
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if (end_pos == std::string::npos) {
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args[i] = mem_argument.substr(pos);
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break;
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}
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args[i] = mem_argument.substr(pos, end_pos - pos);
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pos = end_pos + 1;
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}
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// mem_argument is not empty as getopt requires an argument,
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// but not a valid argument for memory initialization
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if (i == 0) {
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std::cerr << "ERROR: meminit must be in \"name,file[,type]\""
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<< " got: " << mem_argument << std::endl;
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return false;
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}
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svScope scope;
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name = args[0];
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filepath = args[1];
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scope = svGetScopeFromName(rom.data());
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if (i == 1) {
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// Type not set explicitly
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type = DetectMemImageType(filepath);
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} else {
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type = GetMemImageTypeByName(args[2]);
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}
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return true;
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}
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bool VerilatorSimCtrl::MemWrite(const std::string &name,
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const std::string &filepath) {
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MemImageType type = DetectMemImageType(filepath);
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if (type == kMemImageUnknown) {
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std::cerr << "ERROR: Unable to detect file type for: " << filepath
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<< std::endl;
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// Continuing for more error messages
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}
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return MemWrite(name, filepath, type);
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}
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bool VerilatorSimCtrl::MemWrite(const std::string &name,
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const std::string &filepath,
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MemImageType type) {
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// Search for corresponding registered memory based on the name
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auto it = mem_register_.find(name);
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if (it == mem_register_.end()) {
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std::cerr << "ERROR: Memory location not set for: '" << name << "'"
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<< std::endl;
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PrintMemRegions();
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return false;
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}
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if (!MemWrite(it->second, filepath, type)) {
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std::cerr << "ERROR: Setting memory '" << name << "' failed." << std::endl;
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return false;
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}
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return true;
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}
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bool VerilatorSimCtrl::MemWrite(const MemArea &m, const std::string &filepath,
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MemImageType type) {
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if (!IsFileReadable(filepath)) {
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std::cerr << "ERROR: Memory initialization file "
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<< "'" << filepath << "'"
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<< " is not readable." << std::endl;
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return false;
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}
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svScope scope = svGetScopeFromName(m.location.data());
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if (!scope) {
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std::cerr << "ERROR: No ROM found at " << rom << std::endl;
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exit(1);
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std::cerr << "ERROR: No memory found at " << m.location << std::endl;
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return false;
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}
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svSetScope(scope);
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simutil_verilator_memload(rom_init_file_.data());
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std::cout << std::endl
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<< "Rom initialized with program at " << rom_init_file_
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<< std::endl;
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switch (type) {
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case kMemImageElf:
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if (!WriteElfToMem(scope, filepath)) {
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std::cerr << "ERROR: Writing ELF file to memory \"" << m.name << "\" ("
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<< m.location << ") failed." << std::endl;
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return false;
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}
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break;
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case kMemImageVmem:
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if (!WriteVmemToMem(scope, filepath)) {
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std::cerr << "ERROR: Writing VMEM file to memory \"" << m.name << "\" ("
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<< m.location << ") failed." << std::endl;
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return false;
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}
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break;
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case kMemImageUnknown:
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default:
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std::cerr << "ERROR: Unknown file type for " << m.name << std::endl;
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return false;
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}
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return true;
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}
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void VerilatorSimCtrl::InitRam(std::string ram) {
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if (!init_ram_) {
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return;
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bool VerilatorSimCtrl::WriteElfToMem(const svScope &scope,
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const std::string &filepath) {
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bool retcode;
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svScope prev_scope = svSetScope(scope);
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uint8_t *buf = nullptr;
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size_t len_bytes;
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if (!ElfFileToBinary(filepath, &buf, len_bytes)) {
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||||
std::cerr << "ERROR: Could not load: " << filepath << std::endl;
|
||||
retcode = false;
|
||||
goto ret;
|
||||
}
|
||||
for (int i = 0; i < len_bytes / 4; ++i) {
|
||||
if (simutil_verilator_set_mem(i, (svLogicVecVal *)&buf[4 * i])) {
|
||||
std::cerr << "ERROR: Could not set memory byte: " << i * 4 << "/"
|
||||
<< len_bytes << "" << std::endl;
|
||||
|
||||
retcode = false;
|
||||
goto ret;
|
||||
}
|
||||
}
|
||||
|
||||
svScope scope;
|
||||
retcode = true;
|
||||
|
||||
scope = svGetScopeFromName(ram.data());
|
||||
if (!scope) {
|
||||
std::cerr << "ERROR: No RAM found at " << ram << std::endl;
|
||||
exit(1);
|
||||
}
|
||||
svSetScope(scope);
|
||||
|
||||
simutil_verilator_memload(ram_init_file_.data());
|
||||
|
||||
std::cout << std::endl
|
||||
<< "Ram initialized with program at " << ram_init_file_
|
||||
<< std::endl;
|
||||
ret:
|
||||
svSetScope(prev_scope);
|
||||
free(buf);
|
||||
return retcode;
|
||||
}
|
||||
|
||||
void VerilatorSimCtrl::InitFlash(std::string flash) {
|
||||
if (!init_flash_) {
|
||||
return;
|
||||
}
|
||||
bool VerilatorSimCtrl::WriteVmemToMem(const svScope &scope,
|
||||
const std::string &filepath) {
|
||||
svScope prev_scope = svSetScope(scope);
|
||||
|
||||
svScope scope;
|
||||
// TODO: Add error handling.
|
||||
simutil_verilator_memload(filepath.data());
|
||||
|
||||
scope = svGetScopeFromName(flash.data());
|
||||
if (!scope) {
|
||||
std::cerr << "ERROR: No FLASH found at " << flash << std::endl;
|
||||
exit(1);
|
||||
}
|
||||
svSetScope(scope);
|
||||
|
||||
simutil_verilator_memload(flash_init_file_.data());
|
||||
|
||||
std::cout << std::endl
|
||||
<< "Flash initialized with program at " << flash_init_file_
|
||||
<< std::endl;
|
||||
svSetScope(prev_scope);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool VerilatorSimCtrl::ParseCommandArgs(int argc, char **argv, int &retcode) {
|
||||
bool VerilatorSimCtrl::ParseCommandArgs(int argc, char **argv, bool &exit_app) {
|
||||
const struct option long_options[] = {
|
||||
{"rominit", required_argument, nullptr, 'r'},
|
||||
{"raminit", required_argument, nullptr, 'm'},
|
||||
{"flashinit", required_argument, nullptr, 'f'},
|
||||
{"meminit", required_argument, nullptr, 'l'},
|
||||
{"term-after-cycles", required_argument, nullptr, 'c'},
|
||||
{"trace", no_argument, nullptr, 't'},
|
||||
{"help", no_argument, nullptr, 'h'},
|
||||
{nullptr, no_argument, nullptr, 0}};
|
||||
|
||||
while (1) {
|
||||
int c = getopt_long(argc, argv, ":r:m:f:c:th", long_options, nullptr);
|
||||
int c = getopt_long(argc, argv, ":r:m:f:l:c:th", long_options, nullptr);
|
||||
if (c == -1) {
|
||||
break;
|
||||
}
|
||||
|
|
@ -254,35 +412,43 @@ bool VerilatorSimCtrl::ParseCommandArgs(int argc, char **argv, int &retcode) {
|
|||
case 0:
|
||||
break;
|
||||
case 'r':
|
||||
rom_init_file_ = optarg;
|
||||
init_rom_ = true;
|
||||
if (!IsFileReadable(rom_init_file_)) {
|
||||
std::cerr << "ERROR: ROM initialization file "
|
||||
<< "'" << rom_init_file_ << "'"
|
||||
<< " is not readable." << std::endl;
|
||||
if (!MemWrite("rom", optarg)) {
|
||||
std::cerr << "ERROR: Unable to initialize memory." << std::endl;
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case 'm':
|
||||
ram_init_file_ = optarg;
|
||||
init_ram_ = true;
|
||||
if (!IsFileReadable(ram_init_file_)) {
|
||||
std::cerr << "ERROR: Memory initialization file "
|
||||
<< "'" << ram_init_file_ << "'"
|
||||
<< " is not readable." << std::endl;
|
||||
if (!MemWrite("ram", optarg)) {
|
||||
std::cerr << "ERROR: Unable to initialize memory." << std::endl;
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case 'f':
|
||||
flash_init_file_ = optarg;
|
||||
init_flash_ = true;
|
||||
if (!IsFileReadable(flash_init_file_)) {
|
||||
std::cerr << "ERROR: FLASH initialization file "
|
||||
<< "'" << flash_init_file_ << "'"
|
||||
<< " is not readable." << std::endl;
|
||||
if (!MemWrite("flash", optarg)) {
|
||||
std::cerr << "ERROR: Unable to initialize memory." << std::endl;
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case 'l': {
|
||||
if (strcasecmp(optarg, "list") == 0) {
|
||||
PrintMemRegions();
|
||||
exit_app = true;
|
||||
return true;
|
||||
}
|
||||
|
||||
std::string name;
|
||||
std::string filepath;
|
||||
MemImageType type;
|
||||
if (!ParseMemArg(optarg, name, filepath, type)) {
|
||||
std::cerr << "ERROR: Unable to parse meminit arguments." << std::endl;
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!MemWrite(name, filepath, type)) {
|
||||
std::cerr << "ERROR: Unable to initialize memory." << std::endl;
|
||||
return false;
|
||||
}
|
||||
} break;
|
||||
case 't':
|
||||
if (!tracing_possible_) {
|
||||
std::cerr << "ERROR: Tracing has not been enabled at compile time."
|
||||
|
|
@ -296,10 +462,10 @@ bool VerilatorSimCtrl::ParseCommandArgs(int argc, char **argv, int &retcode) {
|
|||
break;
|
||||
case 'h':
|
||||
PrintHelp();
|
||||
return false;
|
||||
exit_app = true;
|
||||
return true;
|
||||
case ':': // missing argument
|
||||
std::cerr << "ERROR: Missing argument." << std::endl;
|
||||
PrintHelp();
|
||||
std::cerr << "ERROR: Missing argument." << std::endl << std::endl;
|
||||
return false;
|
||||
case '?':
|
||||
default:;
|
||||
|
|
@ -330,15 +496,15 @@ void VerilatorSimCtrl::Trace() {
|
|||
}
|
||||
|
||||
if (!tracer_.isOpen()) {
|
||||
tracer_.open(GetSimulationFileName());
|
||||
std::cout << "Writing simulation traces to " << GetSimulationFileName()
|
||||
tracer_.open(GetTraceFileName());
|
||||
std::cout << "Writing simulation traces to " << GetTraceFileName()
|
||||
<< std::endl;
|
||||
}
|
||||
|
||||
tracer_.dump(GetTime());
|
||||
}
|
||||
|
||||
const char *VerilatorSimCtrl::GetSimulationFileName() const {
|
||||
const char *VerilatorSimCtrl::GetTraceFileName() const {
|
||||
#ifdef VM_TRACE_FMT_FST
|
||||
return "sim.fst";
|
||||
#else
|
||||
|
|
@ -354,11 +520,11 @@ void VerilatorSimCtrl::Run() {
|
|||
// We always need to enable this as tracing can be enabled at runtime
|
||||
if (tracing_possible_) {
|
||||
Verilated::traceEverOn(true);
|
||||
top_->trace(tracer_, 99, 0);
|
||||
top_.trace(tracer_, 99, 0);
|
||||
}
|
||||
|
||||
// Evaluate all initial blocks, including the DPI setup routines
|
||||
top_->eval();
|
||||
top_.eval();
|
||||
|
||||
std::cout << std::endl
|
||||
<< "Simulation running, end by pressing CTRL-c." << std::endl;
|
||||
|
|
@ -380,7 +546,7 @@ void VerilatorSimCtrl::Run() {
|
|||
callback_(time_);
|
||||
}
|
||||
|
||||
top_->eval();
|
||||
top_.eval();
|
||||
time_++;
|
||||
|
||||
Trace();
|
||||
|
|
@ -402,7 +568,7 @@ void VerilatorSimCtrl::Run() {
|
|||
}
|
||||
}
|
||||
|
||||
top_->final();
|
||||
top_.final();
|
||||
time_end_ = std::chrono::steady_clock::now();
|
||||
|
||||
if (TracingEverEnabled()) {
|
||||
|
|
@ -434,12 +600,12 @@ void VerilatorSimCtrl::SetResetDuration(unsigned int cycles) {
|
|||
reset_duration_cycles_ = cycles;
|
||||
}
|
||||
|
||||
bool VerilatorSimCtrl::IsFileReadable(std::string filepath) {
|
||||
bool VerilatorSimCtrl::IsFileReadable(std::string filepath) const {
|
||||
struct stat statbuf;
|
||||
return stat(filepath.data(), &statbuf) == 0;
|
||||
}
|
||||
|
||||
bool VerilatorSimCtrl::FileSize(std::string filepath, int &size_byte) {
|
||||
bool VerilatorSimCtrl::FileSize(std::string filepath, int &size_byte) const {
|
||||
struct stat statbuf;
|
||||
if (stat(filepath.data(), &statbuf) != 0) {
|
||||
size_byte = 0;
|
||||
|
|
@ -450,13 +616,13 @@ bool VerilatorSimCtrl::FileSize(std::string filepath, int &size_byte) {
|
|||
return true;
|
||||
}
|
||||
|
||||
unsigned int VerilatorSimCtrl::GetExecutionTimeMs() {
|
||||
unsigned int VerilatorSimCtrl::GetExecutionTimeMs() const {
|
||||
return std::chrono::duration_cast<std::chrono::milliseconds>(time_end_ -
|
||||
time_begin_)
|
||||
.count();
|
||||
}
|
||||
|
||||
void VerilatorSimCtrl::PrintStatistics() {
|
||||
void VerilatorSimCtrl::PrintStatistics() const {
|
||||
double speed_hz = time_ / 2 / (GetExecutionTimeMs() / 1000.0);
|
||||
double speed_khz = speed_hz / 1000.0;
|
||||
|
||||
|
|
@ -470,7 +636,106 @@ void VerilatorSimCtrl::PrintStatistics() {
|
|||
<< "(" << speed_khz << " kHz)" << std::endl;
|
||||
|
||||
int trace_size_byte;
|
||||
if (tracing_enabled_ && FileSize(GetSimulationFileName(), trace_size_byte)) {
|
||||
if (tracing_enabled_ && FileSize(GetTraceFileName(), trace_size_byte)) {
|
||||
std::cout << "Trace file size: " << trace_size_byte << " B" << std::endl;
|
||||
}
|
||||
}
|
||||
|
||||
bool VerilatorSimCtrl::ElfFileToBinary(const std::string &filepath,
|
||||
uint8_t **data,
|
||||
size_t &len_bytes) const {
|
||||
bool retval;
|
||||
std::list<BufferDesc> buffers;
|
||||
size_t offset = 0;
|
||||
(void)elf_errno();
|
||||
len_bytes = 0;
|
||||
|
||||
if (elf_version(EV_CURRENT) == EV_NONE) {
|
||||
std::cerr << elf_errmsg(-1) << std::endl;
|
||||
return false;
|
||||
}
|
||||
|
||||
int fd = open(filepath.c_str(), O_RDONLY, 0);
|
||||
if (fd < 0) {
|
||||
std::cerr << "Could not open file: " << filepath << std::endl;
|
||||
return false;
|
||||
}
|
||||
|
||||
Elf *elf_desc;
|
||||
elf_desc = elf_begin(fd, ELF_C_READ, NULL);
|
||||
if (elf_desc == NULL) {
|
||||
std::cerr << elf_errmsg(-1) << " in: " << filepath << std::endl;
|
||||
retval = false;
|
||||
goto return_fd_end;
|
||||
}
|
||||
if (elf_kind(elf_desc) != ELF_K_ELF) {
|
||||
std::cerr << "Not a ELF file: " << filepath << std::endl;
|
||||
retval = false;
|
||||
goto return_elf_end;
|
||||
}
|
||||
// TODO: add support for ELFCLASS64
|
||||
if (gelf_getclass(elf_desc) != ELFCLASS32) {
|
||||
std::cerr << "Not a 32-bit ELF file: " << filepath << std::endl;
|
||||
retval = false;
|
||||
goto return_elf_end;
|
||||
}
|
||||
|
||||
size_t phnum;
|
||||
if (elf_getphdrnum(elf_desc, &phnum) != 0) {
|
||||
std::cerr << elf_errmsg(-1) << " in: " << filepath << std::endl;
|
||||
retval = false;
|
||||
goto return_elf_end;
|
||||
}
|
||||
|
||||
GElf_Phdr phdr;
|
||||
Elf_Data *elf_data;
|
||||
elf_data = NULL;
|
||||
for (size_t i = 0; i < phnum; i++) {
|
||||
if (gelf_getphdr(elf_desc, i, &phdr) == NULL) {
|
||||
std::cerr << elf_errmsg(-1) << " segment number: " << i
|
||||
<< " in: " << filepath << std::endl;
|
||||
retval = false;
|
||||
goto return_elf_end;
|
||||
}
|
||||
if (phdr.p_type != PT_LOAD) {
|
||||
std::cout << "Program header number " << i << "is not of type PT_LOAD."
|
||||
<< "Continue." << std::endl;
|
||||
continue;
|
||||
}
|
||||
elf_data = elf_getdata_rawchunk(elf_desc, phdr.p_offset, phdr.p_filesz,
|
||||
ELF_T_BYTE);
|
||||
|
||||
if (elf_data == NULL) {
|
||||
retval = false;
|
||||
goto return_elf_end;
|
||||
}
|
||||
|
||||
BufferDesc buf_data;
|
||||
buf_data.length = elf_data->d_size;
|
||||
len_bytes += buf_data.length;
|
||||
buf_data.data = (uint8_t *)malloc(elf_data->d_size);
|
||||
memcpy(buf_data.data, ((uint8_t *)elf_data->d_buf), buf_data.length);
|
||||
buffers.push_back(buf_data);
|
||||
}
|
||||
|
||||
// TODO: Check for the case that phdr.p_memsz > phdr.p_filesz
|
||||
|
||||
// Put the collected data into a continuous buffer
|
||||
// Memory is freed by the caller
|
||||
*data = (uint8_t *)malloc(len_bytes);
|
||||
for (std::list<BufferDesc>::iterator it = buffers.begin();
|
||||
it != buffers.end(); ++it) {
|
||||
memcpy(((uint8_t *)*data) + offset, it->data, it->length);
|
||||
offset += it->length;
|
||||
free(it->data);
|
||||
}
|
||||
buffers.clear();
|
||||
|
||||
retval = true;
|
||||
|
||||
return_elf_end:
|
||||
elf_end(elf_desc);
|
||||
return_fd_end:
|
||||
close(fd);
|
||||
return retval;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,11 +5,12 @@
|
|||
#ifndef VERILATOR_SIM_CTRL_H_
|
||||
#define VERILATOR_SIM_CTRL_H_
|
||||
|
||||
#include <verilated.h>
|
||||
|
||||
#include <chrono>
|
||||
#include <string>
|
||||
#include <functional>
|
||||
#include <map>
|
||||
#include <string>
|
||||
|
||||
#include <verilated.h>
|
||||
|
||||
#include "verilated_toplevel.h"
|
||||
|
||||
|
|
@ -22,22 +23,43 @@ enum VerilatorSimCtrlFlags {
|
|||
// The parameter is simulation time
|
||||
typedef std::function<void(int /* sim time */)> SimCtrlCallBack;
|
||||
|
||||
enum MemImageType {
|
||||
kMemImageUnknown = 0,
|
||||
kMemImageElf,
|
||||
kMemImageVmem,
|
||||
};
|
||||
|
||||
struct MemArea {
|
||||
std::string name; // Unique identifier
|
||||
std::string location; // Design scope location
|
||||
};
|
||||
|
||||
/**
|
||||
* Simulation controller for verilated simulations
|
||||
*/
|
||||
class VerilatorSimCtrl {
|
||||
public:
|
||||
VerilatorSimCtrl(VerilatedToplevel *top, CData &clk, CData &rst_n,
|
||||
VerilatorSimCtrl(VerilatedToplevel &top, CData &clk, CData &rst_n,
|
||||
VerilatorSimCtrlFlags flags = Defaults);
|
||||
|
||||
/**
|
||||
* A helper function to execute some standard setup commands.
|
||||
* Setup and run the simulation (all in one)
|
||||
*
|
||||
* This function performs the followind tasks:
|
||||
* Use this function as high-level entry point, suitable for most use cases.
|
||||
*
|
||||
* Exec() can be used only once per process as it registers a global signal
|
||||
* handler.
|
||||
*
|
||||
* This function performs the following tasks:
|
||||
* 1. Sets up a signal handler to enable tracing to be turned on/off during
|
||||
* a run by sending SIGUSR1 to the process
|
||||
* 2. Parses a C-style set of command line arguments (see ParseCommandArgs)
|
||||
* 2. Parses a C-style set of command line arguments.
|
||||
* 3. Runs the simulation
|
||||
*
|
||||
* @return return code (0 = success)
|
||||
* @return a main()-compatible process exit code: 0 for success, 1 in case
|
||||
* of an error.
|
||||
*/
|
||||
int SetupSimulation(int argc, char **argv);
|
||||
int Exec(int argc, char **argv);
|
||||
|
||||
/**
|
||||
* A helper function to execute a standard set of run commands.
|
||||
|
|
@ -50,27 +72,11 @@ class VerilatorSimCtrl {
|
|||
*/
|
||||
void RunSimulation();
|
||||
|
||||
/**
|
||||
* Register the signal handler
|
||||
*/
|
||||
void RegisterSignalHandler();
|
||||
|
||||
/**
|
||||
* Print help how to use this tool
|
||||
*/
|
||||
void PrintHelp() const;
|
||||
|
||||
/**
|
||||
* Parse command line arguments
|
||||
*
|
||||
* This removes all recognized command-line arguments from argc/argv.
|
||||
*
|
||||
* The return value of this method indicates if the program should exit with
|
||||
* retcode: if this method returns true, do *not* exit; if it returns *false*,
|
||||
* do exit.
|
||||
*/
|
||||
bool ParseCommandArgs(int argc, char **argv, int &retcode);
|
||||
|
||||
/**
|
||||
* Run the main loop of the simulation
|
||||
*
|
||||
|
|
@ -79,29 +85,35 @@ class VerilatorSimCtrl {
|
|||
void Run();
|
||||
|
||||
/**
|
||||
* Initialize Rom
|
||||
* Register a memory as instantiated by generic ram
|
||||
*
|
||||
* The |name| must be a unique identifier. The function will return false
|
||||
* if |name| is already used. |location| is the path to the scope of the
|
||||
* instantiated memory, which needs to support the DPI-C interfaces
|
||||
* 'simutil_verilator_memload' and 'simutil_verilator_set_mem' used for
|
||||
* 'vmem' and 'elf' files, respectively.
|
||||
*
|
||||
* Memories must be registered before command arguments are parsed by
|
||||
* ParseCommandArgs() in order for them to be known.
|
||||
*/
|
||||
void InitRom(const std::string mem);
|
||||
bool RegisterMemoryArea(const std::string name, const std::string location);
|
||||
|
||||
/**
|
||||
* Initialize Ram
|
||||
* Print a list of all registered memory regions
|
||||
*
|
||||
* @see RegisterMemoryArea()
|
||||
*/
|
||||
void InitRam(const std::string mem);
|
||||
|
||||
/**
|
||||
* Initialize Flash
|
||||
*/
|
||||
void InitFlash(const std::string mem);
|
||||
void PrintMemRegions() const;
|
||||
|
||||
/**
|
||||
* Get the current time in ticks
|
||||
*/
|
||||
unsigned long GetTime() { return time_; }
|
||||
unsigned long GetTime() const { return time_; }
|
||||
|
||||
/**
|
||||
* Get the simulation result
|
||||
*/
|
||||
bool WasSimulationSuccessful() { return simulation_success_; }
|
||||
bool WasSimulationSuccessful() const { return simulation_success_; }
|
||||
|
||||
/**
|
||||
* Set the number of clock cycles (periods) before the reset signal is
|
||||
|
|
@ -139,26 +151,29 @@ class VerilatorSimCtrl {
|
|||
/**
|
||||
* Is tracing currently enabled?
|
||||
*/
|
||||
bool TracingEnabled() { return tracing_enabled_; }
|
||||
bool TracingEnabled() const { return tracing_enabled_; }
|
||||
|
||||
/**
|
||||
* Has tracing been ever enabled during the run?
|
||||
*
|
||||
* Tracing can be enabled and disabled at runtime.
|
||||
*/
|
||||
bool TracingEverEnabled() { return tracing_ever_enabled_; }
|
||||
bool TracingEverEnabled() const { return tracing_ever_enabled_; }
|
||||
|
||||
/**
|
||||
* Is tracing support compiled into the simulation?
|
||||
*/
|
||||
bool TracingPossible() { return tracing_possible_; }
|
||||
bool TracingPossible() const { return tracing_possible_; }
|
||||
|
||||
/**
|
||||
* Print statistics about the simulation run
|
||||
*/
|
||||
void PrintStatistics();
|
||||
void PrintStatistics() const;
|
||||
|
||||
const char *GetSimulationFileName() const;
|
||||
/**
|
||||
* Get the file name of the trace file
|
||||
*/
|
||||
const char *GetTraceFileName() const;
|
||||
|
||||
/**
|
||||
* Set a callback function to run every cycle
|
||||
|
|
@ -166,17 +181,11 @@ class VerilatorSimCtrl {
|
|||
void SetOnClockCallback(SimCtrlCallBack callback);
|
||||
|
||||
private:
|
||||
VerilatedToplevel *top_;
|
||||
VerilatedToplevel &top_;
|
||||
CData &sig_clk_;
|
||||
CData &sig_rst_;
|
||||
VerilatorSimCtrlFlags flags_;
|
||||
unsigned long time_;
|
||||
bool init_rom_;
|
||||
bool init_ram_;
|
||||
bool init_flash_;
|
||||
std::string rom_init_file_;
|
||||
std::string ram_init_file_;
|
||||
std::string flash_init_file_;
|
||||
bool tracing_enabled_;
|
||||
bool tracing_enabled_changed_;
|
||||
bool tracing_ever_enabled_;
|
||||
|
|
@ -188,15 +197,56 @@ class VerilatorSimCtrl {
|
|||
std::chrono::steady_clock::time_point time_begin_;
|
||||
std::chrono::steady_clock::time_point time_end_;
|
||||
VerilatedTracer tracer_;
|
||||
std::map<std::string, MemArea> mem_register_;
|
||||
int term_after_cycles_;
|
||||
SimCtrlCallBack callback_;
|
||||
|
||||
unsigned int GetExecutionTimeMs();
|
||||
/**
|
||||
* Register the signal handler
|
||||
*/
|
||||
void RegisterSignalHandler();
|
||||
|
||||
/**
|
||||
* Parse command line arguments
|
||||
*
|
||||
* This removes all recognized command-line arguments from argc/argv.
|
||||
*
|
||||
* The return value of this method indicates if the program should exit with
|
||||
* retcode: if this method returns true, do *not* exit; if it returns *false*,
|
||||
* do exit.
|
||||
*/
|
||||
bool ParseCommandArgs(int argc, char **argv, bool &exit_app);
|
||||
|
||||
/**
|
||||
* Parse argument section specific to memory initialization.
|
||||
*
|
||||
* Must be in the form of: name,file[,type].
|
||||
*/
|
||||
bool ParseMemArg(std::string mem_argument, std::string &name,
|
||||
std::string &filepath, MemImageType &type);
|
||||
MemImageType DetectMemImageType(const std::string filepath);
|
||||
MemImageType GetMemImageTypeByName(const std::string name);
|
||||
|
||||
unsigned int GetExecutionTimeMs() const;
|
||||
void SetReset();
|
||||
void UnsetReset();
|
||||
bool IsFileReadable(std::string filepath);
|
||||
bool FileSize(std::string filepath, int &size_byte);
|
||||
bool IsFileReadable(std::string filepath) const;
|
||||
bool FileSize(std::string filepath, int &size_byte) const;
|
||||
void Trace();
|
||||
|
||||
/**
|
||||
* Dump an ELF file into a raw binary
|
||||
*/
|
||||
bool ElfFileToBinary(const std::string &filepath, uint8_t **data,
|
||||
size_t &len_bytes) const;
|
||||
|
||||
bool MemWrite(const std::string &name, const std::string &filepath);
|
||||
bool MemWrite(const std::string &name, const std::string &filepath,
|
||||
MemImageType type);
|
||||
bool MemWrite(const MemArea &m, const std::string &filepath,
|
||||
MemImageType type);
|
||||
bool WriteElfToMem(const svScope &scope, const std::string &filepath);
|
||||
bool WriteVmemToMem(const svScope &scope, const std::string &filepath);
|
||||
};
|
||||
|
||||
#endif // VERILATOR_SIM_CTRL_H_
|
||||
|
|
|
|||
|
|
@ -4,47 +4,40 @@
|
|||
|
||||
#include <signal.h>
|
||||
|
||||
#include <fstream>
|
||||
#include <iostream>
|
||||
#include <memory>
|
||||
#include <fstream>
|
||||
|
||||
#include "ibex_pcounts.h"
|
||||
#include "verilated_toplevel.h"
|
||||
#include "verilator_sim_ctrl.h"
|
||||
|
||||
std::shared_ptr<VerilatorSimCtrl> simctrl(nullptr);
|
||||
|
||||
int main(int argc, char **argv) {
|
||||
int retcode;
|
||||
ibex_simple_system top;
|
||||
VerilatorSimCtrl simctrl(top, top.IO_CLK, top.IO_RST_N,
|
||||
VerilatorSimCtrlFlags::ResetPolarityNegative);
|
||||
|
||||
auto top = std::make_shared<ibex_simple_system>();
|
||||
|
||||
simctrl = std::make_shared<VerilatorSimCtrl>(
|
||||
top.get(), top->IO_CLK, top->IO_RST_N,
|
||||
VerilatorSimCtrlFlags::ResetPolarityNegative);
|
||||
|
||||
retcode = simctrl->SetupSimulation(argc, argv);
|
||||
|
||||
if (retcode != 0)
|
||||
return retcode;
|
||||
|
||||
// Initialize RAM
|
||||
simctrl->InitRam("TOP.ibex_simple_system.u_ram");
|
||||
simctrl.RegisterMemoryArea("ram", "TOP.ibex_simple_system.u_ram");
|
||||
|
||||
std::cout << "Simulation of Ibex" << std::endl
|
||||
<< "==================" << std::endl
|
||||
<< std::endl;
|
||||
|
||||
simctrl->RunSimulation();
|
||||
if (simctrl.Exec(argc, argv)) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
// TODO: Exec can return with "true" (e.g. with `-h`), but that does not mean
|
||||
// `RunSimulation()` was executed. The folllowing values will not be useful
|
||||
// in this case.
|
||||
std::cout << "\nPerformance Counters" << std::endl
|
||||
<< "====================" << std::endl;
|
||||
std::cout << ibex_pcount_string(
|
||||
top->ibex_simple_system__DOT__mhpmcounter_vals, false);
|
||||
std::cout << ibex_pcount_string(top.ibex_simple_system__DOT__mhpmcounter_vals,
|
||||
false);
|
||||
|
||||
std::ofstream pcount_csv("ibex_simple_system_pcount.csv");
|
||||
pcount_csv << ibex_pcount_string(
|
||||
top->ibex_simple_system__DOT__mhpmcounter_vals, true);
|
||||
top.ibex_simple_system__DOT__mhpmcounter_vals, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ targets:
|
|||
# Optimization levels have a large impact on the runtime performance of the
|
||||
# simulation model. -O2 and -O3 are pretty similar, -Os is slower than -O2/-O3
|
||||
- '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_simple_system -g -O0"'
|
||||
- '-LDFLAGS "-pthread -lutil"'
|
||||
- '-LDFLAGS "-pthread -lutil -lelf"'
|
||||
- "-Wall"
|
||||
- "-Wno-PINCONNECTEMPTY"
|
||||
# XXX: Cleanup all warnings and remove this option
|
||||
|
|
|
|||
|
|
@ -51,12 +51,27 @@ module ram_1p #(
|
|||
end
|
||||
|
||||
`ifdef VERILATOR
|
||||
// Task for loading 'mem' with SystemVerilog system task readmemh
|
||||
export "DPI-C" task simutil_verilator_memload;
|
||||
// Function for setting a specific 32 bit element in 'mem'
|
||||
// Returns 0 for success, 1 for error
|
||||
export "DPI-C" function simutil_verilator_set_mem;
|
||||
|
||||
task simutil_verilator_memload;
|
||||
input string file;
|
||||
$readmemh(file, mem);
|
||||
endtask
|
||||
|
||||
// TODO: Allow 'val' to have other widths than 32 bit
|
||||
function int simutil_verilator_set_mem(input int index,
|
||||
input logic[31:0] val);
|
||||
if (index < Depth) begin
|
||||
mem[index] = val;
|
||||
return 0;
|
||||
end else begin
|
||||
return 1;
|
||||
end
|
||||
endfunction
|
||||
`endif
|
||||
|
||||
`ifdef SRAM_INIT_FILE
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue