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Different optimizations in the ALU to make it smaller
- New generation for ff1, fl1, clb - Muxing for ff1, fl1, clb is different
This commit is contained in:
Andreas Traber
parent
28b5a8e8dc
commit
d1db668404
1 changed files with 177 additions and 53 deletions
226
alu.sv
226
alu.sv
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@ -49,16 +49,30 @@ module riscv_alu
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logic [31:0] operand_a_rev;
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logic [31:0] operand_a_neg;
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logic [31:0] operand_a_neg_rev;
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assign operand_a_neg = ~operand_a_i;
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// bit reverse operand_a for left shifts and bit counting
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genvar k;
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generate
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genvar k;
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for(k = 0; k < 32; k++)
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begin
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assign operand_a_rev[k] = operand_a_i[31-k];
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end
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endgenerate
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// bit reverse operand_a_neg for left shifts and bit counting
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generate
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genvar m;
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for(m = 0; m < 32; m++)
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begin
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assign operand_a_neg_rev[m] = operand_a_neg[31-m];
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end
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endgenerate
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//////////////////////////////////////////////////////////////////////////////////////////
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// ____ _ _ _ _ _ _ _ _ //
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@ -75,7 +89,7 @@ module riscv_alu
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logic [35:0] adder_result_expanded;
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// prepare operand a
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assign adder_op_a = (operator_i == `ALU_ABS) ? ~operand_a_i : operand_a_i;
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assign adder_op_a = (operator_i == `ALU_ABS) ? operand_a_neg : operand_a_i;
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// prepare operand b
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assign adder_op_b = (operator_i == `ALU_SUB) ? ~operand_b_i : operand_b_i;
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@ -192,7 +206,9 @@ module riscv_alu
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endcase
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end
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assign shift_left = (operator_i == `ALU_SLL) || (operator_i == `ALU_BINS);
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// `ALU_FL1 and `ALU_CBL are used for the bit counting ops later
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assign shift_left = (operator_i == `ALU_SLL) || (operator_i == `ALU_BINS) ||
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(operator_i == `ALU_FL1) || (operator_i == `ALU_CLB);
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// choose the bit reversed or the normal input for shift operand a
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assign shift_op_a = (shift_left == 1'b1) ? operand_a_rev : operand_a_i;
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@ -474,66 +490,61 @@ module riscv_alu
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/////////////////////////////////////////////////////////////////////
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logic [31:0] ff_input; // either op_a_i or its bit reversed version
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logic [5:0] cnt_result; // population count
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logic [5:0] clb_result; // count leading bits
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logic [5:0] ff1_result; // holds the index of the first '1'
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logic ff_no_one; // if no ones are found
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logic [5:0] fl1_result; // holds the index of the last '1'
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logic ff_cmp; // compare value for ff1 and fl1
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integer q;
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logic [5:0] bitop_result; // result of all bitop operations muxed together
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assign ff_input = (operator_i == `ALU_FF1) ? operand_a_i : operand_a_rev;
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assign ff_cmp = (operator_i == `ALU_CLB) ? ~operand_a_i[31] : 1'b1;
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alu_popcnt alu_popcnt_i
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(
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.in_i ( operand_a_i ),
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.result_o ( cnt_result )
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);
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always_comb
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begin
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ff1_result = 6'd0;
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ff_input = 'x;
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for(q = 1; q < 33; q++)
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begin
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if(ff_input[q - 1] == ff_cmp)
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begin
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ff1_result = q;
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break;
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end
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case (operator_i)
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`ALU_FF1: ff_input = operand_a_i;
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`ALU_FL1: ff_input = operand_a_rev;
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`ALU_CLB: begin
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if (operand_a_i[31])
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ff_input = operand_a_neg_rev;
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else
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ff_input = operand_a_rev;
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end
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endcase
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end
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alu_ff alu_ff_i
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(
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.in_i ( ff_input ),
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.first_one_o ( ff1_result ),
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.no_ones_o ( ff_no_one )
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);
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// special case if ff1_res is 0 (no 1 found), then we keep the 0
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assign fl1_result = (ff1_result == 6'd0) ? 6'd0 : (6'd33 - ff1_result);
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assign clb_result = (ff1_result == 6'd0) ? 6'd0 : (ff1_result - 6'd2);
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// this is done in the result mux
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assign fl1_result = 6'd33 - ff1_result;
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assign clb_result = ff1_result - 6'd2;
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// count the number of '1's in a word
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logic [5:0] cnt_result;
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logic [1:0] cnt_l1[16];
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logic [2:0] cnt_l2[8];
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logic [3:0] cnt_l3[4];
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logic [4:0] cnt_l4[2];
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genvar l, m, n, p;
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generate for(l = 0; l < 16; l++)
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always_comb
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begin
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assign cnt_l1[l] = operand_a_i[2*l] + operand_a_i[2*l + 1];
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end
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endgenerate
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bitop_result = 'x;
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case (operator_i)
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`ALU_FF1: bitop_result = ff1_result;
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`ALU_FL1: bitop_result = fl1_result;
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`ALU_CLB: bitop_result = clb_result;
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`ALU_CNT: bitop_result = cnt_result;
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default:;
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endcase
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generate for(m = 0; m < 8; m++)
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begin
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assign cnt_l2[m] = cnt_l1[2*m] + cnt_l1[2*m + 1];
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if (ff_no_one)
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bitop_result = '0;
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end
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endgenerate
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generate for(n = 0; n < 4; n++)
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begin
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assign cnt_l3[n] = cnt_l2[2*n] + cnt_l2[2*n + 1];
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end
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endgenerate
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generate for(p = 0; p < 2; p++)
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begin
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assign cnt_l4[p] = cnt_l3[2*p] + cnt_l3[2*p + 1];
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end
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endgenerate
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assign cnt_result = cnt_l4[0] + cnt_l4[1];
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////////////////////////////////////////////////
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@ -674,10 +685,7 @@ module riscv_alu
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// Set Lower Equal Than Operations (result = 1, if a <= b)
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`ALU_SLETS, `ALU_SLETU: result_o = {31'b0, comparison_result_o};
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`ALU_FF1: result_o = {26'h0, ff1_result};
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`ALU_FL1: result_o = {26'h0, fl1_result};
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`ALU_CLB: result_o = {26'h0, clb_result};
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`ALU_CNT: result_o = {26'h0, cnt_result};
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`ALU_FF1, `ALU_FL1, `ALU_CLB, `ALU_CNT: result_o = {26'h0, bitop_result};
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// Division Unit Commands
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`ALU_DIV, `ALU_DIVU,
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@ -690,3 +698,119 @@ module riscv_alu
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assign ready_o = div_ready;
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endmodule
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module alu_ff
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#(
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parameter LEN = 32
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)
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(
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input logic [LEN-1:0] in_i,
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output logic [$clog2(LEN):0] first_one_o,
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output logic no_ones_o
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);
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localparam NUM_LEVELS = $clog2(LEN);
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logic [LEN-1:0] [NUM_LEVELS:0] index_lut;
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logic [2**NUM_LEVELS-1:0] sel_nodes;
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logic [2**NUM_LEVELS-1:0] [NUM_LEVELS:0] index_nodes;
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//////////////////////////////////////////////////////////////////////////////
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// generate tree structure
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//////////////////////////////////////////////////////////////////////////////
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generate
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genvar j;
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for (j = 0; j < LEN; j++) begin
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assign index_lut[j] = $unsigned(j + 1);
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end
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endgenerate
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generate
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genvar k;
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genvar l;
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genvar level;
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for (level = 0; level < NUM_LEVELS; level++) begin
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//------------------------------------------------------------
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if (level < NUM_LEVELS-1) begin
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for (l = 0; l < 2**level; l++) begin
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assign sel_nodes[2**level-1+l] = sel_nodes[2**(level+1)-1+l*2] | sel_nodes[2**(level+1)-1+l*2+1];
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assign index_nodes[2**level-1+l] = (sel_nodes[2**(level+1)-1+l*2] == 1'b1) ?
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index_nodes[2**(level+1)-1+l*2] : index_nodes[2**(level+1)-1+l*2+1];
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end
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end
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//------------------------------------------------------------
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if (level == NUM_LEVELS-1) begin
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for (k = 0; k < 2**level; k++) begin
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// if two successive indices are still in the vector...
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if (k * 2 < LEN) begin
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assign sel_nodes[2**level-1+k] = in_i[k*2] | in_i[k*2+1];
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assign index_nodes[2**level-1+k] = (in_i[k*2] == 1'b1) ? index_lut[k*2] : index_lut[k*2+1];
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end
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// if only the first index is still in the vector...
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if (k * 2 == LEN) begin
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assign sel_nodes[2**level-1+k] = in_i[k*2];
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assign index_nodes[2**level-1+k] = index_lut[k*2];
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end
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// if index is out of range
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if (k * 2 > LEN) begin
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assign sel_nodes[2**level-1+k] = 1'b0;
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assign index_nodes[2**level-1+k] = '0;
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end
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end
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end
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//------------------------------------------------------------
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end
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endgenerate
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//////////////////////////////////////////////////////////////////////////////
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// connect output
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//////////////////////////////////////////////////////////////////////////////
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assign first_one_o = index_nodes[0];
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assign no_ones_o = ~sel_nodes[0];
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endmodule
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// count the number of '1's in a word
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module alu_popcnt
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(
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input logic [31:0] in_i,
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output logic [5: 0] result_o
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);
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logic [1:0] cnt_l1[16];
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logic [2:0] cnt_l2[8];
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logic [3:0] cnt_l3[4];
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logic [4:0] cnt_l4[2];
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genvar l, m, n, p;
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generate for(l = 0; l < 16; l++)
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begin
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assign cnt_l1[l] = in_i[2*l] + in_i[2*l + 1];
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end
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endgenerate
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generate for(m = 0; m < 8; m++)
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begin
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assign cnt_l2[m] = cnt_l1[2*m] + cnt_l1[2*m + 1];
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end
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endgenerate
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generate for(n = 0; n < 4; n++)
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begin
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assign cnt_l3[n] = cnt_l2[2*n] + cnt_l2[2*n + 1];
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end
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endgenerate
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generate for(p = 0; p < 2; p++)
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begin
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assign cnt_l4[p] = cnt_l3[2*p] + cnt_l3[2*p + 1];
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end
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endgenerate
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assign result_o = cnt_l4[0] + cnt_l4[1];
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endmodule
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