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Import riscv-dv @b4bd0c6cff0456111be966a11c1bd0aeec2d96e4 (#69)
* update ibex patch file * Update google_riscv-dv to b4bd0c6 Update code from upstream repository https://github.com/google/riscv- dv to revision b4bd0c6cff0456111be966a11c1bd0aeec2d96e4 * Merge pull request #24 from google/dev (taoliug) * Add option to skip reading scratch register (Tao Liu)
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taoliug
GitHub
parent
4bbe38fa52
commit
d77bc49595
6 changed files with 104 additions and 47 deletions
2
vendor/google_riscv-dv.lock.hjson
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2
vendor/google_riscv-dv.lock.hjson
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@ -9,6 +9,6 @@
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upstream:
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{
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url: https://github.com/google/riscv-dv
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rev: be14080425cc3b9a5b33c6c29962893c890c62ee
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rev: b4bd0c6cff0456111be966a11c1bd0aeec2d96e4
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}
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}
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@ -245,6 +245,11 @@ class riscv_asm_program_gen extends uvm_object;
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virtual function void gen_program_header();
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// ------------- IBEX modification start --------------------
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// Override the cfg value, below field is not supported by ibex
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cfg.mstatus_mprv = 0;
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cfg.mstatus_mxr = 0;
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cfg.mstatus_sum = 0;
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cfg.mstatus_tvm = 0;
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// The ibex core load the program from 0x80
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// Some address is reserved for hardware interrupt handling, need to decide if we need to copy
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// the init program from crt0.S later.
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@ -255,7 +260,19 @@ class riscv_asm_program_gen extends uvm_object;
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instr_stream.push_back("j _start");
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// Align the start section to 0x80
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instr_stream.push_back(".align 7");
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instr_stream.push_back("_start:");
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instr_stream.push_back("_start: j _reset_entry");
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// ibex reserves 0x84-0x8C for trap handling, redirect everything mtvec_handler
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// 0x84 illegal instruction
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instr_stream.push_back(".align 2");
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instr_stream.push_back("j mtvec_handler");
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// 0x88 ECALL instruction handler
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instr_stream.push_back(".align 2");
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instr_stream.push_back("j mtvec_handler");
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// 0x8C LSU error
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instr_stream.push_back(".align 2");
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instr_stream.push_back("j mtvec_handler");
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// Starting point of the reset entry
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instr_stream.push_back("_reset_entry:");
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// ------------- IBEX modification end --------------------
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endfunction
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32
vendor/google_riscv-dv/src/riscv_core_setting.sv
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32
vendor/google_riscv-dv/src/riscv_core_setting.sv
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@ -82,43 +82,15 @@ int kernel_program_instr_cnt = 400;
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// Implemented previlieged CSR list
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privileged_reg_t implemented_csr[$] = {
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// User mode CSR
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USTATUS, // User status
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UIE, // User interrupt-enable register
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UTVEC, // User trap-handler base address
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USCRATCH, // Scratch register for user trap handlers
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UEPC, // User exception program counter
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UCAUSE, // User trap cause
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UTVAL, // User bad address or instruction
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UIP, // User interrupt pending
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// Supervisor mode CSR
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SSTATUS, // Supervisor status
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SEDELEG, // Supervisor exception delegation register
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SIDELEG, // Supervisor interrupt delegation register
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SIE, // Supervisor interrupt-enable register
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STVEC, // Supervisor trap-handler base address
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SCOUNTEREN, // Supervisor counter enable
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SSCRATCH, // Scratch register for supervisor trap handlers
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SEPC, // Supervisor exception program counter
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SCAUSE, // Supervisor trap cause
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STVAL, // Supervisor bad address or instruction
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SIP, // Supervisor interrupt pending
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SATP, // Supervisor address translation and protection
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// Machine mode mode CSR
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MVENDORID, // Vendor ID
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MARCHID, // Architecture ID
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MIMPID, // Implementation ID
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MHARTID, // Hardware thread ID
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MSTATUS, // Machine status
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MISA, // ISA and extensions
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MEDELEG, // Machine exception delegation register
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MIDELEG, // Machine interrupt delegation register
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MIE, // Machine interrupt-enable register
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MTVEC, // Machine trap-handler base address
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MCOUNTEREN, // Machine counter enable
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MSCRATCH, // Scratch register for machine trap handlers
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MEPC, // Machine exception program counter
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MCAUSE, // Machine trap cause
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MTVAL, // Machine bad address or instruction
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MIP // Machine interrupt pending
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MTVAL // Machine bad address or instruction
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// TODO: Add performance CSRs and debug mode CSR
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};
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22
vendor/google_riscv-dv/src/riscv_instr_pkg.sv
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22
vendor/google_riscv-dv/src/riscv_instr_pkg.sv
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@ -682,11 +682,13 @@ package riscv_instr_pkg;
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bit mprv,
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ref string instr[$]);
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string store_instr = (XLEN == 32) ? "sw" : "sd";
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// Use kernal stack for handling exceptions
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// Save the user mode stack pointer to the scratch register
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instr.push_back($sformatf("csrrw sp, 0x%0x, sp", scratch));
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// Move TP to SP
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instr.push_back("add sp, tp, zero");
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if (scratch inside {implemented_csr}) begin
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// Use kernal stack for handling exceptions
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// Save the user mode stack pointer to the scratch register
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instr.push_back($sformatf("csrrw sp, 0x%0x, sp", scratch));
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// Move TP to SP
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instr.push_back("add sp, tp, zero");
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end
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// If MPRV is set and MPP is S/U mode, it means the address translation and memory protection
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// for load/store instruction is the same as the mode indicated by MPP. In this case, we
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// need to use the virtual address to access the kernel stack.
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@ -724,10 +726,12 @@ package riscv_instr_pkg;
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end
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// Restore kernel stack pointer
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instr.push_back($sformatf("addi sp, sp, %0d", 32 * (XLEN/8)));
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// Move SP to TP
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instr.push_back("add tp, sp, zero");
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// Restore user mode stack pointer
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instr.push_back($sformatf("csrrw sp, 0x%0x, sp", scratch));
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if (scratch inside {implemented_csr}) begin
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// Move SP to TP
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instr.push_back("add tp, sp, zero");
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// Restore user mode stack pointer
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instr.push_back($sformatf("csrrw sp, 0x%0x, sp", scratch));
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end
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endfunction
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`include "riscv_instr_gen_config.sv"
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2
vendor/google_riscv-dv/testlist
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2
vendor/google_riscv-dv/testlist
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@ -24,6 +24,6 @@ riscv_mmu_stress_test : 10
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riscv_page_table_exception_test : 0
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riscv_no_fence_test : 10
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riscv_sfence_exception_test : 0
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riscv_illegal_instr_test : 10
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riscv_illegal_instr_test : 1
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riscv_hint_instr_test : 10
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//------------------------------------------------
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@ -58,14 +58,19 @@ index 0000000..34036bb
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+# Process ibex log
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+process_ibex_sim_log(args.log, args.csv)
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diff --git a/src/riscv_asm_program_gen.sv b/src/riscv_asm_program_gen.sv
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index b538b72..78ab6ed 100644
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index b538b72..2f9f28f 100644
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--- a/src/riscv_asm_program_gen.sv
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+++ b/src/riscv_asm_program_gen.sv
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@@ -244,11 +244,19 @@ class riscv_asm_program_gen extends uvm_object;
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@@ -244,11 +244,36 @@ class riscv_asm_program_gen extends uvm_object;
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//---------------------------------------------------------------------------------------
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virtual function void gen_program_header();
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+ // ------------- IBEX modification start --------------------
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+ // Override the cfg value, below field is not supported by ibex
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+ cfg.mstatus_mprv = 0;
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+ cfg.mstatus_mxr = 0;
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+ cfg.mstatus_sum = 0;
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+ cfg.mstatus_tvm = 0;
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+ // The ibex core load the program from 0x80
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+ // Some address is reserved for hardware interrupt handling, need to decide if we need to copy
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+ // the init program from crt0.S later.
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@ -73,16 +78,29 @@ index b538b72..78ab6ed 100644
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instr_stream.push_back(".endm");
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instr_stream.push_back(".section .text.init");
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instr_stream.push_back(".globl _start");
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- instr_stream.push_back("_start:");
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+ instr_stream.push_back("j _start");
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+ // Align the start section to 0x80
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+ instr_stream.push_back(".align 7");
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instr_stream.push_back("_start:");
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+ instr_stream.push_back("_start: j _reset_entry");
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+ // ibex reserves 0x84-0x8C for trap handling, redirect everything mtvec_handler
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+ // 0x84 illegal instruction
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+ instr_stream.push_back(".align 2");
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+ instr_stream.push_back("j mtvec_handler");
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+ // 0x88 ECALL instruction handler
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+ instr_stream.push_back(".align 2");
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+ instr_stream.push_back("j mtvec_handler");
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+ // 0x8C LSU error
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+ instr_stream.push_back(".align 2");
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+ instr_stream.push_back("j mtvec_handler");
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+ // Starting point of the reset entry
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+ instr_stream.push_back("_reset_entry:");
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+ // ------------- IBEX modification end --------------------
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endfunction
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virtual function void gen_program_end();
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diff --git a/src/riscv_core_setting.sv b/src/riscv_core_setting.sv
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index 5cb3d76..c523573 100644
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index 75c5821..0175d2f 100644
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--- a/src/riscv_core_setting.sv
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+++ b/src/riscv_core_setting.sv
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@@ -18,25 +18,27 @@
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@ -150,6 +168,52 @@ index 5cb3d76..c523573 100644
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// Byte size of kernel data pages
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int kernel_data_page_size = 4096;
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@@ -86,43 +82,15 @@ int kernel_program_instr_cnt = 400;
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// Implemented previlieged CSR list
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privileged_reg_t implemented_csr[$] = {
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- // User mode CSR
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- USTATUS, // User status
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- UIE, // User interrupt-enable register
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- UTVEC, // User trap-handler base address
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- USCRATCH, // Scratch register for user trap handlers
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- UEPC, // User exception program counter
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- UCAUSE, // User trap cause
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- UTVAL, // User bad address or instruction
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- UIP, // User interrupt pending
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- // Supervisor mode CSR
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- SSTATUS, // Supervisor status
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- SEDELEG, // Supervisor exception delegation register
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- SIDELEG, // Supervisor interrupt delegation register
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- SIE, // Supervisor interrupt-enable register
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- STVEC, // Supervisor trap-handler base address
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- SCOUNTEREN, // Supervisor counter enable
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- SSCRATCH, // Scratch register for supervisor trap handlers
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- SEPC, // Supervisor exception program counter
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- SCAUSE, // Supervisor trap cause
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- STVAL, // Supervisor bad address or instruction
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- SIP, // Supervisor interrupt pending
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- SATP, // Supervisor address translation and protection
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// Machine mode mode CSR
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MVENDORID, // Vendor ID
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MARCHID, // Architecture ID
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- MIMPID, // Implementation ID
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MHARTID, // Hardware thread ID
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MSTATUS, // Machine status
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MISA, // ISA and extensions
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- MEDELEG, // Machine exception delegation register
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- MIDELEG, // Machine interrupt delegation register
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- MIE, // Machine interrupt-enable register
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MTVEC, // Machine trap-handler base address
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- MCOUNTEREN, // Machine counter enable
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- MSCRATCH, // Scratch register for machine trap handlers
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MEPC, // Machine exception program counter
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MCAUSE, // Machine trap cause
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- MTVAL, // Machine bad address or instruction
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- MIP // Machine interrupt pending
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+ MTVAL // Machine bad address or instruction
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+ // TODO: Add performance CSRs and debug mode CSR
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};
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diff --git a/testlist b/testlist
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index 123951e..0fd4e31 100644
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--- a/testlist
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@ -178,6 +242,6 @@ index 123951e..0fd4e31 100644
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+riscv_page_table_exception_test : 0
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+riscv_no_fence_test : 10
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+riscv_sfence_exception_test : 0
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+riscv_illegal_instr_test : 10
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+riscv_illegal_instr_test : 1
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+riscv_hint_instr_test : 10
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//------------------------------------------------
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