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Add RV32E assertion warning

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This commit is contained in:
Markus Wegmann 2017-01-07 17:36:15 +01:00
parent e76d5b44a6
commit d83a6d8813
2 changed files with 14 additions and 0 deletions
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10
decoder.sv
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@ -31,6 +31,10 @@ import riscv_defines::*;
module riscv_decoder
(
// CONFIG_REGION: RV32E
`ifdef RV32E
input logic clk,
`endif
// singals running to/from controller
input logic deassert_we_i, // deassert we, we are stalled or not active
// CONFIG_REGION: ONLY_ALIGNED
@ -1324,4 +1328,10 @@ module riscv_decoder
assign jump_in_dec_o = jump_in_id;
// CONFIG_REGION: RV32E
`ifdef RV32E
// the instruction delivered to the ID stage should always be valid
assert property (
@(posedge clk) (illegal_insn_o) |-> (~illegal_reg_addr) ) else $warning("Register address in instruction is out of bounds (RV32E)!!!");
`endif
endmodule // controller

4
id_stage.sv
View file

@ -1071,6 +1071,10 @@ module riscv_id_stage
riscv_decoder decoder_i
(
// CONFIG_REGION: RV32E
`ifdef RV32E
.clk ( clk ),
`endif
// controller related signals
.deassert_we_i ( deassert_we ),
// CONFIG_REGION: ONLY_ALIGNED