Merge branch 'openhwgroup:main' into feature/expmmode

.readthedocs.yaml

@@ -0,0 +1,23 @@
+# Copyright 2023 OpenHW Group
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+# Read the Docs configuration file
+# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
+
+# Required
+version: 2
+
+build:
+  os: "ubuntu-20.04"
+  tools:
+    python: "3.9"
+
+# Build from the docs directory with Sphinx
+sphinx:
+  configuration: doc/conf.py
+
+# Explicitly set the Python requirements
+python:
+  install:
+    - requirements: doc/requirements.txt

README.md

@@ -2,13 +2,13 @@
 
 CVE2 is a class of 2-stage pipeline OpenHW Group cores. Currently, the only core in this class is the CV32E20.
 CV32E20 is a fork of the [Ibex](https://github.com/lowRISC/ibex) core.
-Differently to Ibex, cv32e2 will target low cost as originally intented in the [Zero-riscy](https://doi.org/10.1109/PATMOS.2017.8106976) project.
+Differently to Ibex, cv32e2 will target low cost as originally intended in the [Zero-riscy](https://doi.org/10.1109/PATMOS.2017.8106976) project.
 The core will be made compatible with the OpenHW Group OBI protocol, it will use the same sleep unit of CV32E4 family, and it will achieve TRL5 with the industrial-level verification [core-v-verif](https://github.com/openhwgroup/core-v-verif).
 
 # CV32E20 RISC-V Core
 
 CV32E20 is a production-quality open source source 32-bit RISC-V CPU core written in
-SystemVerilog. The CPU core is heavily parametrizable and well suited for
+SystemVerilog. The CPU core is heavily parametrizable and well-suited for
 embedded control applications. CV32E20 is being extensively verified and has
 seen multiple tape-outs. CV32E20 supports the Integer (I) or Embedded (E),
 Integer Multiplication and Division (M), and Compressed (C) extensions.
@@ -43,13 +43,13 @@ that touches any file in 'rtl' (or any of its subdirectories) with *Component:RT
 ignored for the changelog generation.
 
 Only the person who actually performs the merge can add these labels (you need committer rights). The changelog flow only works if at most
-1 label is applied and therefore pull requests that touches both RTL and documentation files in the same pull request are not allowed.
+1 label is applied and therefore pull requests that touch both RTL and documentation files in the same pull request are not allowed.
 
 ## Configuration
 
 CV32E20 offers several configuration parameters to meet the needs of various application scenarios.
 The options include different choices for the architecture of the multiplier unit, as well as a range of performance and security features.
-The table below indicates performance, area and verification status for a few selected configurations.
+The table below indicates performance, area, and verification status for a few selected configurations.
 These are configurations on which lowRISC is focusing for performance evaluation and design verification (see [supported configs](cve2_configs.yaml)).
 
 | Config                            | "micro" | "small"               |
@@ -67,19 +67,19 @@ Notes:
   See the [Benchmarks README](examples/sw/benchmarks/README.md) for more information.
 * Yosys synthesis area numbers are based on the CV32E20 basic synthesis [flow](syn/README.md) using the latch-based register file.
 * Commercial synthesis area numbers are a rough estimate of what might be achievable with a commercial synthesis flow and technology library.
-* For comparison, the original "Zero-riscy" core yields an area of 23.14kGE using our Yosys synthesis flow.
+* For comparison, the original "zero-riscy" core yields an area of 23.14kGE using our Yosys synthesis flow.
 * Verification status is a rough guide to the overall maturity of a particular configuration.
   Green indicates that verification is close to complete.
   Amber indicates that some verification has been performed, but the configuration is still experimental.
   Red indicates a configuration with minimal/no verification.
 * v.1.0.0 of the RISC-V Bit-Manipulation Extension is supported as well as the remaining sub-extensions of draft v.0.93 of the bitmanip spec.
-  The latter are *not ratified* and there may be changes before ratification.
+  The latter is *not ratified* and there may be changes before ratification.
   See [Standards Compliance](https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html) in the Ibex documentation for more information.
 
 ## Documentation (to be updated)
 
-The Ibex user manual can be
-[read online at ReadTheDocs](https://ibex-core.readthedocs.io/en/latest/). It is also contained in
+The CVE2 documentation can be
+[read online at ReadTheDocs](https://docs.openhwgroup.org/projects/cve2-user-manual/en/latest/). It is also contained in
 the `doc` folder of this repository.
 
 ## Examples
@@ -97,12 +97,12 @@ please:
 * Create your own fork to commit your changes and then open a Pull Request to the **dev** branch.
 * Split large contributions into smaller commits addressing individual changes or bug fixes. Do not
   mix unrelated changes into the same commit!
-* Do not mix updates within the 'rtl' directory with updates within the 'docs' directory ino the same pull request.
+* Do not mix updates within the 'rtl' directory with updates within the 'docs' directory into the same pull request.
 * Write meaningful commit messages. For more information, please check out the [the Ibex contribution
   guide](https://github.com/lowrisc/ibex/blob/master/CONTRIBUTING.md).
-* If asked to modify your changes, do fixup your commits and rebase your branch to maintain a
+* If asked to modify your changes, do fix up your commits and rebase your branch to maintain a
   clean history.
-* If the PR gets accepted and merged into the the **dev** branch, an action is triggered automatically to check whether the changes are logically equivalent to the frozen RTL on a given set of parameters. If the changes are logically equivalent, the **dev** branch is automatically merged into the **master** branch. Otherwise, we need to investigate manually. If a bug is found, thus the changes are not logically equivalent, we follow the procedure documented [here](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/core_versions.html).
+* If the PR gets accepted and merged into the **dev** branch, an action is triggered automatically to check whether the changes are logically equivalent to the frozen RTL on a given set of parameters. If the changes are logically equivalent, the **dev** branch is automatically merged into the **master** branch. Otherwise, we need to investigate manually. If a bug is found, thus the changes are not logically equivalent, we follow the procedure documented [here](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/core_versions.html).
 
 For more details on how this is implemented, have a look at this [page](https://github.com/openhwgroup/cv32e40p/blob/master/.github/workflows/aws_cv32e40p.md).
 
@@ -130,3 +130,11 @@ License, Version 2.0 (see LICENSE for full text).
 
 Many people have contributed to CVE2 and its predecessor projects through the years. Please have a look at
 the [credits file](CREDITS.md) and the commit history for more information.
+
+## References
+
+[Schiavone, Pasquale Davide, et al. "Slow and steady wins the race? A comparison of
+ ultra-low-power RISC-V cores for Internet-of-Things applications."
+ _27th International Symposium on Power and Timing Modeling, Optimization and Simulation
+ (PATMOS 2017)_](https://doi.org/10.1109/PATMOS.2017.8106976)
+

doc/01_overview/compliance.rst

@@ -1,67 +0,0 @@
-Standards Compliance
-====================
-
-Ibex is a standards-compliant 32 bit RISC-V processor.
-It follows these specifications:
-
-* `RISC-V Instruction Set Manual, Volume I: User-Level ISA, document version 20190608-Base-Ratified (June 8, 2019) <https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-spec-20190608.pdf>`_
-* `RISC-V Instruction Set Manual, Volume II: Privileged Architecture, document version 20190608-Base-Ratified (June 8, 2019) <https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf>`_.
-  Ibex implements the Machine ISA version 1.11.
-* `RISC-V External Debug Support, version 0.13.2 <https://content.riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf>`_
-* `RISC-V Bit-Manipulation Extension, version 1.0.0 <https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf>`_ and `version 0.93 (draft from January 10, 2021) <https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf>`_
-* `PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp) version 0.9.3 <https://github.com/riscv/riscv-tee/blob/61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf>`_
-
-Many features in the RISC-V specification are optional, and Ibex can be parametrized to enable or disable some of them.
-
-Ibex can be parametrized to support either of the following two instruction sets.
-
-* The RV32I Base Integer Instruction Set, version 2.1
-* The RV32E Base Integer Instruction Set, version 1.9 (draft from June 8, 2019)
-
-In addition, the following instruction set extensions are available.
-
-.. list-table:: Ibex Instruction Set Extensions
-   :header-rows: 1
-
-   * - Extension
-     - Version
-     - Configurability
-
-   * - **C**: Standard Extension for Compressed Instructions
-     - 2.0
-     - always enabled
-
-   * - **M**: Standard Extension for Integer Multiplication and Division
-     - 2.0
-     - optional
-
-   * - **B**: Standard Extension for Bit-Manipulation Instructions
-     - 1.0.0 + 0.93 [#B_draft]_
-     - optional
-
-   * - **Zicsr**: Control and Status Register Instructions
-     - 2.0
-     - always enabled
-
-   * - **Zifencei**: Instruction-Fetch Fence
-     - 2.0
-     - always enabled
-
-Most content of the RISC-V privileged specification is optional.
-Ibex currently supports the following features according to the RISC-V Privileged Specification, version 1.11.
-
-* M-Mode and U-Mode
-* All CSRs listed in :ref:`cs-registers`
-* Performance counters as described in :ref:`performance-counters`
-* Vectorized trap handling as described at :ref:`exceptions-interrupts`
-
-See :ref:`PMP Enhancements<pmp-enhancements>` for more information on Ibex's experimental and optional support for the PMP Enhancement proposal from the Trusted Execution Environment (TEE) working group.
-
-.. rubric:: Footnotes
-
-.. [#B_draft] Ibex fully implements the ratified version 1.0.0 of the RISC-V Bit-Manipulation Extension including the Zba, Zbb, Zbc and Zbs sub-extensions.
-   In addition, Ibex also supports the remaining Zbe, Zbf, Zbp, Zbr and Zbt sub-extensions as defined in draft version 0.93 of the RISC-V Bit-Manipulation Extension.
-   Note that the latter sub-extensions may change before being ratified as a standard by the RISC-V Foundation.
-   Ibex will be updated to match future versions of the specification.
-   Prior to ratification this may involve backwards incompatible changes.
-   Additionally, neither GCC or Clang have committed to maintaining support upstream for unratified versions of the specification.

doc/01_overview/index.rst

@@ -1,16 +0,0 @@
-Introduction to CVE2
-====================
-
-Ibex is a production-quality open source 32-bit RISC-V CPU core written in SystemVerilog.
-The CPU core is heavily parametrizable and well suited for embedded control applications.
-Ibex is being extensively verified and has seen multiple tape-outs.
-
-Read on for more information Ibex in general: what standards it implements, what synthesis targets it supports, and what legal and financial obligations you have when using Ibex.
-
-.. toctree::
-   :maxdepth: 2
-   :caption: In this section
-
-   compliance
-   targets
-   licensing

doc/01_overview/licensing.rst

@@ -1,16 +0,0 @@
-Licensing
-=========
-
-Ibex is released under the Apache license, version 2.0.
-
-Ibex can be used, modified, and distributed for any purpose (including commercial) and without any royalties.
-There are some requirements on including copyright notices and the original license.
-
-Please see the ``LICENSE`` file in the source code for the full (and legally binding) license text.
-
-Even though the license doesn't require it, we appreciate feedback and contributions to make Ibex work better for everyone.
-Please open an `issue <https://github.com/lowRISC/ibex/issues>`_ for bug reports, questions, or suggested improvements, or a `pull request <https://github.com/lowRISC/ibex/pulls>`_ if you'd like to contribute code.
-
-.. note::
-
-  Commercial support for Ibex is available from `lowRISC <https://www.lowrisc.org/>`_.

doc/01_overview/targets.rst

@@ -1,19 +0,0 @@
-Synthesis Targets
-=================
-
-ASIC Synthesis
---------------
-
-ASIC synthesis is supported for Ibex.
-The whole design is completely synchronous and uses positive-edge triggered flip-flops, except for the register file, which can be implemented either with latches or with flip-flops.
-See :ref:`register-file` for more details.
-The core occupies an area of roughly 24 kGE when using the latch-based register file and implementing the RV32IMC ISA, or 15 kGE when implementing the RV32EC ISA.
-
-
-FPGA Synthesis
---------------
-
-FPGA Synthesis is supported for Ibex.
-The FPGA-optimized register file implementation should be used.
-The flip-flop based register file is also compatible with FPGA synthesis, however it may result in significantly higher resource utilization.
-Since latches are not well supported on FPGAs, the latch-based register file should not be used.

doc/01_specification/index.rst

@@ -0,0 +1,898 @@
+=====================
+CV32E20 Specification
+=====================
+
+License
+=======
+
+Copyright 2022-2023 OpenHW Group
+
+Copyright 2018-2022 lowRISC Revision 8d044a3d
+
+Copyright 2017-2018, ETH Zurich and University of Bologna
+
+Copyright 2018 ETH Zürich and University of Bologna
+
+SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+Licensed under the Solderpad Hardware License v 2.1 (the “License”); you
+may not use this file except in compliance with the License, or, at your
+option, the Apache License version 2.0. You may obtain a copy of the
+License at https://solderpad.org/licenses/SHL-2.1/.
+
+Unless required by applicable law or agreed to in writing, any work
+distributed under the License is distributed on an “AS IS” BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Introduction
+============
+
+The OpenHW Group CV32E20, or simply E20, is a :term:`RISC-V` processor core that
+is targeted for the ultra-low-end of the 32-bit microcontroller (:term:`MCU`)
+application space. Likely uses include any “constrained compute socket”
+or as the processor element in embedded :term:`SoC` subsystems.
+
+The core design was originally developed as the PULPino *ZeroRISCY*
+processor by ETH Zürich and the University of Bologna and later enhanced
+by the lowRISC consortium as the *Ibex* core. For this project, the Ibex
+design description is copied and further enhanced by the OpenHW Group.
+The design is qualified using the industrial-strength
+Core-V-Verification methodologies. The source :term:`RTL` code is written in
+SystemVerilog and maintained by the OpenHW Group.
+
+This specification is organized as requirements that apply to the “Scope
+of the :term:`IP`". The Revision 0.1 of this requirements document is intended
+to specify the “Version 1” E20 design - there are already plans for
+subsequent enhancements that will be included in a Version 2 (and
+possibly beyond) design releases. Subsequent revision numbers are
+placeholders for these enhancements after the initial project freeze
+(PF) gate.
+
+The requirement list is to be approved by the OpenHW Group Technical
+Work Group (:term:`TWG`), as well as any subsequent change requests.
+
+The specification is complemented by a user's guide.
+
+A `List of Abbreviations`_ is available at the end of this document.
+
+This development is co-sponsored by NXP and Intrinsix, a wholly owned
+subsidiary of CEVA.
+
+Scope
+=====
+
+Scope of the IP
+---------------
+
+The **scope of the IP** is the processor core subsystem that is
+specified below and that is verified with a 100% coverage goal. In the
+verification plans, the scope of the IP can be partitioned into two DUTs
+(designs under test) - one covering the processor core itself, and a
+:term:`coreplex` covering the processor "core complex" which adds
+debug capabilities, an interrupt controller and system bus protocol
+wrappers to the E20 core.
+
+The scope of the IP is the **CV32E20 hardware** supporting all the
+features used in products based on the E20 core. A high-level block
+diagram of the E20 core is shown below:
+
+.. image:: ../03_reference/images/blockdiagram.svg
+  :alt: CV32E20 Blockdiagram
+
+As displayed in this core block diagram, the E20 is a 2-stage pipelined
+implementation featuring a 32-bit Harvard memory architecture for
+independent instruction fetch and data load/store interfaces. The first
+pipeline stage is the instruction fetch (:term:`IF`), while the second stage is
+the Instruction Decode and Execute (:term:`ID/EX`).
+
+As displayed in the above figure, the IP comprises:
+
+-  The CV32E20 processor core with dual 32-bit Harvard memory interfaces
+
+   -  Instruction fetch bus, data load/store bus
+
+   -  Support for both RV32I (32 x 32b GPRs) and RV32E (16 x 32b GPRs)
+
+   -  Support for :term:`ISA` extensions: C (compressed) and M (multiply &
+      divide)
+
+   -  Support for basic set of Configuration & Status Registers (CSRs)
+
+-  Dual 32-bit Harvard memory interfaces
+
+   -  Supported core protocol is OBI_1_v1.2 (Open Bus Interface)
+      definition
+
+At the coreplex design level, the following functions are added to the
+processor core:
+
+-  Debug module including the :term:`DTM`
+
+-  Interrupt module
+
+-  System bus wrappers to convert from OBI [OPENHW-OBI]_ to the
+   :term:`AMBA`-:term:`AHB` (Advanced Microcontroller Bus Architecture, Advanced
+   High-performance Bus) protocol [AMBA-AHB]_
+
+In addition to these main configurations, multiple fine grain parameters
+are available.
+
+Unless otherwise stated, optional features are controlled by
+SystemVerilog parameters. If not selected, each optional feature is not
+present in the netlist after synthesis. The reader's attention is drawn
+to the difference between an optional feature ("...\ *shall* support as
+an option...") versus a desired goal ("...\ *should* support...",
+"...\ *should* reduce latency...").
+
+The following topics are beyond the scope of this specification:
+
+-  Software (SW layers), such as compilers, assemblers and :term:`OSes`
+   (although these could be part of the OpenHW Group CV32E20 project)
+
+-  Software emulation of RISC-V optional extensions (feasible but the
+   scope of the IP is the core and coreplex hardware)
+
+-  Other features included in the testbench (main memory, firmware,
+   interconnect…), the coverage of which are not measured
+
+Golden configurations
+---------------------
+
+It is not possible to verify all 2\ :sup:`n` combinations of design
+parameters. Below is the list of golden configurations that will undergo
+verification in the project and their main parameters. The full list of
+parameters for each golden configuration are detailed in the user guide.
+
++----------------------------+-----------------+----------------------+
+| Configuration              | Target          | RV32{E,I} ISA        |
++----------------------------+-----------------+----------------------+
+| cv32e2_emc_fpga            | :term:`FPGA`    | RV32EMC              |
++----------------------------+-----------------+----------------------+
+| cv32e2_imc_fpga            | FPGA            | RV32IMC              |
++----------------------------+-----------------+----------------------+
+| cv32e2_emc_asic            | :term:`ASIC`    | RV32EMC              |
++----------------------------+-----------------+----------------------+
+| cv32e2_imc_asic            | ASIC            | RV32IMC              |
++----------------------------+-----------------+----------------------+
+
+References
+==========
+
+Applicable specifications
+-------------------------
+
+To ease the reading, the reference to these specifications is implicit
+in the requirements below. For the sake of precision, the requirements
+identify the versions of RISC-V extensions from these specifications.
+
+.. [RVunpriv] “The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA,
+   Document Version 20191213”, Editors Andrew Waterman and Krste Asanović,
+   RISC-V Foundation, December 2019.
+
+.. [RVpriv] “The RISC-V Instruction Set Manual, Volume II: Privileged
+   Architecture, Document Version 20211203”, Editors Andrew Waterman,
+   Krste Asanović, and John Hauser, RISC-V International, December 2021.
+
+.. [RVdbg-RATIFIED] “RISC-V External Debug Support, Document Version
+   0.13.2”, Editors Tim Newsome and Megan Wachs, RISC-V Foundation, March
+   22, 2019.
+
+.. [RVdbg-STABLE] “RISC-V External Debug Support, Document Version
+   1.0.0-STABLE”, Editors Ernie Edgar and Tim Newsome, RISC-V Foundation,
+   April 7, 2022.
+
+.. [OPENHW-OBI] OpenHW Open Bus Interface (OBI) protocol, version 1.4,
+   https://github.com/openhwgroup/core-v-docs/blob/master/cores/obi/OBI-v1.4.pdf
+
+.. [AMBA-AHB] “AMBA® AHB Protocol Specification”, ARM IHI 0033C (ID090921),
+   https://developer.arm.com/documentation/ihi0033/latest
+
+.. [RVsmclic] “Smclic” Core-Local Interrupt Controller (CLIC) RISC-V
+   Privileged Architecture Extension, version 0.9-draft, 3/15/2022,
+   https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.pdf
+
+Other documents
+===============
+
+.. [FPGAreset] Ken Chapman, “Get Smart About Reset: Think Local, Not
+   Global”, Xilinx WP272 white paper, https://docs.xilinx.com/v/u/en-US/wp272
+
+CV32E20 core functional requirements
+====================================
+
+General requirement
+-------------------
+
++--------+--------------------------------------------------------------+
+| GEN-10 | CV32E20 shall be **fully compliant with RISC-V               |
+|        | specifications** by implementing all mandatory features for  |
+|        | the selected extensions.                                     |
++--------+--------------------------------------------------------------+
+
+As the RISC-V specification leaves ample space for options, this section
+specifies these options.
+
+RISC-V standard instructions
+----------------------------
+
+To ease tracing for verification, the extensions are split into
+independent requirements. All bases and extensions are specified in 
+[RVunpriv]_.
+
++--------+---------------------------------------------------------------+
+| ISA-10 | CV32E20 shall support **RV32I** base instruction set, version |
+|        | 2.1 (ratified).                                               |
++--------+---------------------------------------------------------------+
+| ISA-20 | CV32E20 shall support **RV32E** base instruction set, version |
+|        | 1.9 (draft).                                                  |
++--------+---------------------------------------------------------------+
+| ISA-30 | CV32E20 shall support the **M** extension (integer multiply & |
+|        | divide), version 2.0 (ratified).                              |
++--------+---------------------------------------------------------------+
+| ISA-40 | CV32E20 shall support the **C** extension (compressed         |
+|        | instructions), version 2.0 (ratified).                        |
++--------+---------------------------------------------------------------+
+| ISA-50 | CV32E20 shall support the **Zicsr** extension (CSR            |
+|        | instructions), version 2.0 (ratified).                        |
++--------+---------------------------------------------------------------+
+| ISA-60 | CV32E20 shall support the **Zifencei** extension, version 2.0 |
+|        | (ratified).                                                   |
++--------+---------------------------------------------------------------+
+
+Operating modes (Privilege Levels)
+----------------------------------
+
++--------+--------------------------------------------------------------+
+| PVL-10 | CV32E20 shall support only little-endian memory              |
+|        | organizations.                                               |
++--------+--------------------------------------------------------------+
+| PVL-20 | CV32E20 shall support **machine** and **unprivileged**       |
+|        | privilege modes.                                             |
++--------+--------------------------------------------------------------+
+| PVL-30 | CV32E20 shall export the CPU's operating mode as an address  |
+|        | phase attribute output signals on the Harvard memory         |
+|        | interfaces (instruction fetch, data load/store) with machine |
+|        | mode defined as 1'b1 and user mode as 1'b0.                  |
++--------+--------------------------------------------------------------+
+| PVL-40 | CV32E20 shall support the **bare** (addressing) mode, that   |
+|        | is, no support for address translation or protection.        |
++--------+--------------------------------------------------------------+
+
+Control and Status Registers (CSRs)
+-----------------------------------
+
++--------+--------------------------------------------------------------+
+| CSR-10 | CV32E20 shall implement all mandatory CSRs of Debug, Machine |
+|        | and User modes as per specifications in [RVpriv]_.           |
++--------+--------------------------------------------------------------+
+
+In keeping with the CV32E20's smallest size and power core targets, the
+implemented set of CSRs is intentionally minimized.
+
+The implemented set of CSRs includes the following registers:
+
++--------+--------------------------------------------------------------+
+| CSR-20 | CV32E20 shall implement these mandatory Machine Mode CSRs as |
+|        | per specifications in [RVpriv]_. Optional registers are      |
+|        | *highlighted*. The registers are listed based on ascending   |
+|        | CSR number.                                                  |
+|        |                                                              |
+|        | CSR Number CSR Register Description                          |
+|        |                                                              |
+|        | 0x300 mstatus // machine status                              |
+|        |                                                              |
+|        | 0x301 misa // machine isa and extensions                     |
+|        |                                                              |
+|        | 0x304 mie // machine interrupt enable register               |
+|        |                                                              |
+|        | 0x305 mtvec // machine trap vector base address              |
+|        |                                                              |
+|        | 0x320 mcountinhibit // HPM-10: machine counter inhibit       |
+|        | register                                                     |
+|        |                                                              |
+|        | *0x323 mhpmevent3 // HPM-20: perf monitor event selector*    |
+|        |                                                              |
+|        | *0x324 mhpmevent4 // HPM-20: perf monitor event selector*    |
+|        |                                                              |
+|        | *0x325 mhpmevent5 // HPM-20: perf monitor event selector*    |
+|        |                                                              |
+|        | *0x326 mhpmevent6 // HPM-20: perf monitor event selector*    |
+|        |                                                              |
+|        | *0x327 mhpmevent7 // HPM-20: perf monitor event selector*    |
+|        |                                                              |
+|        | *0x328 mhpmevent8 // HPM-20: perf monitor event selector*    |
+|        |                                                              |
+|        | *0x329 mhpmevent9 // HPM-20: perf monitor event selector*    |
+|        |                                                              |
+|        | *0x32a mhpmevent10 // HPM-20: perf monitor event selector*   |
+|        |                                                              |
+|        | *0x32b mhpmevent11 // HPM-20: perf monitor event selector*   |
+|        |                                                              |
+|        | *0x32c mhpmevent12 // HPM-20: perf monitor event selector*   |
+|        |                                                              |
+|        | 0x340 mscratch // machine scratch register                   |
+|        |                                                              |
+|        | 0x341 mepc // machine exception program counter              |
+|        |                                                              |
+|        | 0x342 mcause // machine cause register                       |
+|        |                                                              |
+|        | 0x343 mtval // machine trap value register                   |
+|        |                                                              |
+|        | 0x344 mip // machine interrupt pending register              |
+|        |                                                              |
+|        | 0x7a0 tselect // trigger select register                     |
+|        |                                                              |
+|        | 0x7a1 tdata1 // trigger data register 1                      |
+|        |                                                              |
+|        | 0x7a2 tdata2 // trigger data register 2                      |
+|        |                                                              |
+|        | 0x7a3 tdata3 // trigger data register 3                      |
+|        |                                                              |
+|        | 0x7a8 mcontext // machine context register                   |
+|        |                                                              |
+|        | 0x7aa scontext // supervisor context register                |
+|        |                                                              |
+|        | 0x7b0 dcsr // debug control and status register              |
+|        |                                                              |
+|        | 0x7b1 dpc // debug pc register                               |
+|        |                                                              |
+|        | 0x7b2 dscratch0 // debug scratch register 0                  |
+|        |                                                              |
+|        | 0x7b3 dscratch1 // debug scratch register 2                  |
+|        |                                                              |
+|        | 0x7c0 cpuctrl // cpu control register                        |
+|        |                                                              |
+|        | 0xb00 mcycle // HPM-10: machine cycle counter                |
+|        |                                                              |
+|        | 0xb02 minstret // HPM-10: machine insts retired counter      |
+|        |                                                              |
+|        | *0xb03 mpmcounter3 // HPM-10: number of load/store cycles*   |
+|        |                                                              |
+|        | *0xb04 mpmcounter4 // HPM-10: number of inst fetch cycles*   |
+|        |                                                              |
+|        | *0xb05 mpmcounter5 // HPM-10: number of load cycles*         |
+|        |                                                              |
+|        | *0xb06 mpmcounter6 // HPM-10: number of store cycles*        |
+|        |                                                              |
+|        | *0xb07 mpmcounter7 // HPM-10: number of jump cycles*         |
+|        |                                                              |
+|        | *0xb08 mpmcounter8 // HPM-10: number of conditional br       |
+|        | cycles*                                                      |
+|        |                                                              |
+|        | *0xb09 mpmcounter9 // HPM-10: number of cond br taken        |
+|        | cycles*                                                      |
+|        |                                                              |
+|        | *0xb0a mpmcounter10 // HPM-10: number of return inst cycles* |
+|        |                                                              |
+|        | *0xb0b mpmcounter11 // HPM-10: number of wfi cycles*         |
+|        |                                                              |
+|        | *0xb0c mpmcounter12 // HPM-10: number of divide cycles*      |
+|        |                                                              |
+|        | 0xb80 mcycleh // HPM-10: upper word of mcycle                |
+|        |                                                              |
+|        | 0xb82 minstreth // HPM-10: upper word of minstret            |
+|        |                                                              |
+|        | *0xb83 mpmcounter3h // HPM-20: upper word of mpmcounter3*    |
+|        |                                                              |
+|        | *0xb84 mpmcounter4h // HPM-20: upper word of mpmcounter4*    |
+|        |                                                              |
+|        | *0xb85 mpmcounter5h // HPM-20: upper word of mpmcounter5*    |
+|        |                                                              |
+|        | *0xb86 mpmcounter6h // HPM-20: upper word of mpmcounter6*    |
+|        |                                                              |
+|        | *0xb87 mpmcounter7h // HPM-20: upper word of mpmcounter7*    |
+|        |                                                              |
+|        | *0xb88 mpmcounter8h // HPM-20: upper word of mpmcounter8*    |
+|        |                                                              |
+|        | *0xb89 mpmcounter9h // HPM-20: upper word of mpmcounter9*    |
+|        |                                                              |
+|        | *0xb8a mpmcounter10h // HPM-20: upper word of mpmcounter10*  |
+|        |                                                              |
+|        | *0xb8b mpmcounter11h // HPM-20: upper word of mpmcounter11*  |
+|        |                                                              |
+|        | *0xb8c mpmcounter12h // HPM-20: upper word of mpmcounter12*  |
+|        |                                                              |
+|        | 0xc00 cycle // unprivileged mode cycle, lower 32b            |
+|        |                                                              |
+|        | 0xc02 instret // unprivileged mode instret, lower 32b        |
+|        |                                                              |
+|        | 0xc80 cycleh // unprivileged mode cycle, upper 32b           |
+|        |                                                              |
+|        | 0xc82 instreth // unprivileged mode instret, upper 32b       |
+|        |                                                              |
+|        | 0xf11 mvendorid // machine vendor ID                         |
+|        |                                                              |
+|        | 0xf12 marchid // machine architecture ID                     |
+|        |                                                              |
+|        | 0xf13 mimpid // machine implementation ID                    |
+|        |                                                              |
+|        | 0xf14 mhartid // hardware thread ID                          |
++--------+--------------------------------------------------------------+
+
+CSR hardware performance counters
+---------------------------------
+
+For the performance monitor counters, the default CSR configuration for
+the CV32E20 core implements the two 64-bit cycle and
+inst(ructions)ret(ired) counters along with the 32-bit mcountinhibit
+register.
+
+The 64-bit counters are accessed using CSRR instructions separately
+reading the upper and lower 32-bit values. A 4-instruction loop can be
+used to provide a fully coherent 64-bit register read that provides
+protection against any “race condition” involving an overflow from the
+lower order 32-bit register.
+
++--------+---------------------------------------------------------------+
+| HPM-10 | CV32E20 shall implement the 64-bit mcycle and minstret        |
+|        | standard performance counters (including their upper 32 bits  |
+|        | counterparts mcycleh and minstreth) as per [RVpriv]_:         |
+|        |                                                               |
+|        | CSR Number PM Counter Description                             |
+|        |                                                               |
+|        | 0x320 mcountinhibit // machine-mode                           |
+|        |                                                               |
+|        | 0xb00 mcycle // machine mode cycle, lower 32 bits             |
+|        |                                                               |
+|        | 0xb02 minstret // machine mode instret, lower 32 bits         |
+|        |                                                               |
+|        | 0xb80 mcycleh // machine mode cycle, upper 32 bits            |
+|        |                                                               |
+|        | 0xb82 minstreth // machine mode instret, upper 32 bits        |
+|        |                                                               |
+|        | 0xc00 cycle // unprivileged mode cycle, lower 32b             |
+|        |                                                               |
+|        | 0xc02 instret // unprivileged mode instret, lower 32b         |
+|        |                                                               |
+|        | 0xc80 cycleh // unprivileged mode cycle, upper 32b            |
+|        |                                                               |
+|        | 0xc82 instreth // unprivileged mode instret, upper 32b        |
++--------+---------------------------------------------------------------+
+| HPM-20 | CV32E20 should support 10 optional event counters             |
+|        | (mhpmcounterX{h}) and their associated event selector         |
+|        | (mhpmeventX) performance monitoring registers. *The default   |
+|        | width of these registers is 32 bits*.                         |
+|        |                                                               |
+|        | These registers are intended to provide hardware performance  |
+|        | monitoring capabilities in FPGA development targets (and/or   |
+|        | ASIC SoC targets).                                            |
+|        |                                                               |
+|        | CSR Number PM Counter Description                             |
+|        |                                                               |
+|        | 0xb03 mhpmcounter3 // m-mode performance-monitoring counter 3 |
+|        |                                                               |
+|        | // NumCyclesLSU, lower 32 bits                                |
+|        |                                                               |
+|        | 0xb04 mphmcounter4 // m-mode performance-monitoring counter 4 |
+|        |                                                               |
+|        | // NumCyclesIF, lower 32 bits                                 |
+|        |                                                               |
+|        | 0xb05 mphmcounter5 // m-mode performance-monitoring counter 5 |
+|        |                                                               |
+|        | // NumLoads, lower 32 bits                                    |
+|        |                                                               |
+|        | 0xb06 mphmcounter6 // m-mode performance-monitoring counter 6 |
+|        |                                                               |
+|        | // NumStores, lower 32 bits                                   |
+|        |                                                               |
+|        | 0xb07 mphmcounter7 // m-mode performance-monitoring counter 7 |
+|        |                                                               |
+|        | // NumJumps, lower 32 bits                                    |
+|        |                                                               |
+|        | 0xb08 mphmcounter8 // m-mode performance-monitoring counter 8 |
+|        |                                                               |
+|        | // NumBranches, lower 32 bits                                 |
+|        |                                                               |
+|        | 0xb09 mphmcounter9 // m-mode performance-monitoring counter 9 |
+|        |                                                               |
+|        | // NumBranchesTaken, lower 32 bits                            |
+|        |                                                               |
+|        | 0xb0a mphmcounter10 // m-mode performance-monitoring counter  |
+|        | 10                                                            |
+|        |                                                               |
+|        | // NumInstrRetC, lower 32 bits                                |
+|        |                                                               |
+|        | 0xb0b mphmcounter11 // m-mode performance-monitoring counter  |
+|        | 11                                                            |
+|        |                                                               |
+|        | // NumCyclesWFI, lower 32 bits                                |
+|        |                                                               |
+|        | 0xb0c mphmcounter12 // m-mode performance-monitoring counter  |
+|        | 12                                                            |
+|        |                                                               |
+|        | // NumCyclesDivWait, lower 32 bits                            |
+|        |                                                               |
+|        | 0xb83 mhpmcounter3h // m-mode performance-monitoring counter  |
+|        | 3                                                             |
+|        |                                                               |
+|        | // NumCyclesLSU, upper 32 bits                                |
+|        |                                                               |
+|        | 0xb84 mphmcounter4h // m-mode performance-monitoring counter  |
+|        | 4                                                             |
+|        |                                                               |
+|        | // NumCyclesIF, upper 32 bits                                 |
+|        |                                                               |
+|        | 0xb85 mphmcounter5h // m-mode performance-monitoring counter  |
+|        | 5                                                             |
+|        |                                                               |
+|        | // NumLoads, upper 32 bits                                    |
+|        |                                                               |
+|        | 0xb86 mphmcounter6h // m-mode performance-monitoring counter  |
+|        | 6                                                             |
+|        |                                                               |
+|        | // NumStores, upper 32 bits                                   |
+|        |                                                               |
+|        | 0xb87 mphmcounter7h // m-mode performance-monitoring counter  |
+|        | 7                                                             |
+|        |                                                               |
+|        | // NumJumps, upper 32 bits                                    |
+|        |                                                               |
+|        | 0xb88 mphmcounter8h // m-mode performance-monitoring counter  |
+|        | 8                                                             |
+|        |                                                               |
+|        | // NumBranches, upper 32 bits                                 |
+|        |                                                               |
+|        | 0xb89 mphmcounter9h // m-mode performance-monitoring counter  |
+|        | 9                                                             |
+|        |                                                               |
+|        | // NumBranchesTaken, upper 32 bits                            |
+|        |                                                               |
+|        | 0xb8a mphmcounter10h // m-mode performance-monitoring counter |
+|        | 10                                                            |
+|        |                                                               |
+|        | // NumInstrRetC, upper 32 bits                                |
+|        |                                                               |
+|        | 0xb8b mphmcounter11h // m-mode performance-monitoring counter |
+|        | 11                                                            |
+|        |                                                               |
+|        | // NumCyclesWFI, upper 32 bits                                |
+|        |                                                               |
+|        | 0xb8c mphmcounter12h // m-mode performance-monitoring counter |
+|        | 12                                                            |
+|        |                                                               |
+|        | // NumCyclesDivWait, upper 32 bits                            |
+|        |                                                               |
+|        | The mphmeventX registers are the event selectors and          |
+|        | enable/disable the corresponding mphmcounterX registers. The  |
+|        | association of the events with the mphmcounterX registers are |
+|        | hardwired.                                                    |
+|        |                                                               |
+|        | CSR Number Event Selector Description: event ID/bit, reset    |
+|        | value                                                         |
+|        |                                                               |
+|        | 0x323 mhpmevent3 // 3, 0x0000_0008                            |
+|        |                                                               |
+|        | 0x324 mphmevent4 // 4, 0x0000_0010                            |
+|        |                                                               |
+|        | 0x325 mphmevent5 // 5, 0x0000_0020                            |
+|        |                                                               |
+|        | 0x326 mphmevent6 // 6, 0x0000_0040                            |
+|        |                                                               |
+|        | 0x327 mphmevent7 // 7, 0x0000_0080                            |
+|        |                                                               |
+|        | 0x328 mphmevent8 // 8, 0x0000_0100                            |
+|        |                                                               |
+|        | 0x329 mphmevent9 // 9, 0x0000_0200                            |
+|        |                                                               |
+|        | 0x32a mphmevent10 // 10, 0x0000_0400                          |
+|        |                                                               |
+|        | 0x32b mphmevent11 // 11, 0x0000_0800                          |
+|        |                                                               |
+|        | 0x32c mphmevent12 // 12, 0x0000_1000                          |
++--------+---------------------------------------------------------------+
+
+.. note::
+   The Ibex documentation is incorrect/confusing about the optional
+   presence of mpmcounter{11,12}. This specification assumes the Ibex
+   documentation is simply incorrect for these 2 counters.
+
+.. note::
+   It should be mentioned that the event associated with 
+   mphm{event,counter}11 has a different definition for the E20 core versus
+   Ibex. This counter no longer tracks multiply cycles, but rather, the
+   cycles when the core is quiescent in the 'wait for interrupt' state.  
+
+Additional details on the CSRs are available in the user manual.
+
+Interface requirements
+======================
+
+CV32E20 core memory bus
+-----------------------
+
++--------+-------------------------------------------------------------+
+| MEM-10 | CV32E20 core shall support a Harvard memory interface with  |
+|        | two 32-bit OBI interfaces, one for instruction fetch and a  |
+|        | second for data loads & stores. Each bus includes a 32-bit  |
+|        | byte address and dual 32-bit buses for read and write data. |
+|        | Data references support 8-bit byte, 16-bit halfword and     |
+|        | 32-bit word elements.                                       |
++--------+-------------------------------------------------------------+
+
+CV32E20 coreplex memory bus
+---------------------------
+
++--------+-------------------------------------------------------------+
+| MEM-20 | The CV32E20 coreplex shall support a Harvard memory         |
+|        | interface with two 32-bit AMBA-AHB5 interfaces, one for     |
+|        | instruction fetch and a second for data loads & stores.     |
+|        | Each bus includes a 32-bit byte address and dual 32-bit     |
+|        | buses for read and write data. Data references support      |
+|        | 8-bit byte, 16-bit halfword and 32-bit word elements.       |
++--------+-------------------------------------------------------------+
+| MEM-21 | The CV32E20 coreplex also shall support a 32-bit AMBA-AHB5  |
+|        | interface from the debug module to allow real-time debug    |
+|        | access to system memory.                                    |
++--------+-------------------------------------------------------------+
+| MEM-30 | The CV32E20 coreplex shall support unaligned (also known as |
+|        | *misaligned*) data accesses for the E20 core by generating  |
+|        | 2 bus cycles to complete the memory reference. This         |
+|        | capability requires individual byte strobes be supported in |
+|        | the attached data memory.                                   |
+|        |                                                             |
+|        | If this capability cannot be supported, the coreplex shall  |
+|        | support an optional hardware configuration where all        |
+|        | unaligned data accesses are decomposed into combinations of |
+|        | 8- and 16-bit transfers. This means the ‘worst-case' data   |
+|        | unalignment may require 3 bus cycles (byte, halfword, byte) |
+|        | to complete.                                                |
++--------+-------------------------------------------------------------+
+| MEM-40 | The CV32E20 coreplex shall generate only SINGLE AHB         |
+|        | transactions, that is, no BURST transactions are generated  |
+|        | by the E20 core.                                            |
++--------+-------------------------------------------------------------+
+| MEM-50 | The CV32E20 coreplex AHB5 bus protocol shall support the    |
+|        | following design interface parameters:                      |
+|        |                                                             |
+|        | ADDR_WIDTH 32                                               |
+|        |                                                             |
+|        | DATA_WIDTH 32                                               |
+|        |                                                             |
+|        | HBURST_WIDTH 4                                              |
+|        |                                                             |
+|        | HPROT_WIDTH 4                                               |
+|        |                                                             |
+|        | HMASTER_WIDTH 0                                             |
++--------+-------------------------------------------------------------+
+| MEM-60 | The CV32E20 coreplex AHB5 bus protocol shall not support    |
+|        | signaling associated with exclusive accesses - this implies |
+|        | the HEXCL and HEXOKAY control signals are not used.         |
++--------+-------------------------------------------------------------+
+| MEM-70 | The CV32E20 coreplex AHB5 bus protocol shall encode the     |
+|        | operating mode of every access using the {HNONSECURE,       |
+|        | HPROT[1]} bus attribute signals defined as:                 |
+|        |                                                             |
+|        | if E20 core mode = user, then {HNONSECURE, HPROT[1]} =      |
+|        | 2'b10                                                       |
+|        |                                                             |
+|        | if E20 core mode = supervisor, then {HNONSECURE, HPROT[1]}  |
+|        | = 2'b11                                                     |
+|        |                                                             |
+|        | if E20 core mode = machine, then {HNONSECURE, HPROT[1]} =   |
+|        | 2'b01                                                       |
++--------+-------------------------------------------------------------+
+| MEM-80 | The CV32E20 coreplex AHB5 bus protocol shall implement a    |
+|        | 4-bit HPROT[*] bus attribute control where HPROT[3:2] is    |
+|        | hardwired to 2'b00.                                         |
++--------+-------------------------------------------------------------+
+
+Debug
+-----
+
++---------+------------------------------------------------------------+
+| DBG-10  | CV32E20 shall implement the features outlined in Chapter 4 |
+|         | of [RVdbg].                                                |
++---------+------------------------------------------------------------+
+
+In addition, there can be an external debug module, not in the scope of
+the IP.
+
+Interrupts
+----------
+
+CLINT is the default interrupt controller in [RVpriv]_. It is limited to 
+32 custom IRQs for RV32. A :term:`CLIC` [RVsmclic]_ supports up to 4.064
+IRQs, but is not yet ratified at the time of specification. 
+
++---------+------------------------------------------------------------+
+| IRQ-10  | CV32E20 shall implement interrupt handling registers as    |
+|         | per the RISC-V privilege specification and interface with  |
+|         | a :term:`CLINT` implementation.                            |
++---------+------------------------------------------------------------+
+| IRQ-20  | CV32E20 shall implement one Non-Maskable Interrupt (NMI),  |
+|         | which is triggered from an external signal. The            |
+|         | corresponding excpection code is 32.                       |
++---------+------------------------------------------------------------+
+| IRQ-30  | The NMI implemented by CV32E20 shall be resumable.         |
++---------+------------------------------------------------------------+
+
+.. note::
+   It should be noted that Ibex had implemented a custom mechanism for NMI 
+   recovery. A standard RISC-V way of NMI recovery is in draft stage. In
+   future, the custom mechanism could be reworked to follow the standard.
+
+Coprocessor interface
+---------------------
+
++--------+-------------------------------------------------------------+
+| XIF-10 | For *subsequent* core implementations, CV32E20 shall        |
+|        | support the coprocessor interface compliant with [CV-X-IF]  |
+|        | to extend the supported instructions. The goal is a set of  |
+|        | compatible interfaces between the CORE-V cores, for         |
+|        | example, CV32E40{P,S,X}, CV32E20, …                         |
+|        |                                                             |
+|        | The initial version of CV32E20 shall not support the        |
+|        | CV-X-IF coprocessor interface.                              |
++--------+-------------------------------------------------------------+
+
+PPA targets
+===========
+
+These PPA targets will be updated when physical design monitoring is
+integrated in the continuous integration flow.
+
++--------+-------------------------------------------------------------+
+| PPA-10 | CV32E20 should be resource optimized for both ASIC and FPGA |
+|        | targets.                                                    |
+|        |                                                             |
+|        | In general, the relative priority of the PPA metrics is     |
+|        | Power > Area > Performance. The project needs to determine  |
+|        | how much to measure and minimize power dissipation -        |
+|        | core/coreplex area provides a general proxy for power with  |
+|        | numerous caveats.                                           |
++--------+-------------------------------------------------------------+
+| PPA-20 | CV32E20 should deliver more than x.y CoreMark/MHz           |
+|        | performance when targeting RV32IMC for maximum performance, |
+|        | for example, GCC -O3 compiler options and attached to zero  |
+|        | wait-state instruction and data memories.                   |
+|        |                                                             |
+|        | This performance metric should be defined across multiple   |
+|        | configuration variables like RV32{I,E}MC, compilers         |
+|        | {GCC,LLVM} and compiler options {-O3, -Os/-Oz}. The core's  |
+|        | operating environment is defined with attached zero         |
+|        | wait-state instruction and data memories.                   |
++--------+-------------------------------------------------------------+
+| PPA-30 | CV32E20 should operate at more than ? MHz in the            |
+|        | CV32E20\_?\_fpga configuration on Kintex 7 FPGA technology. |
+|        |                                                             |
+|        | Metric details to be supplied later.                        |
++--------+-------------------------------------------------------------+
+| PPA-50 | CV32E20 should operate at more than ? MHz in the            |
+|        | CV32E20\_? configuration on 16-nm FFT technology in the     |
+|        | worst-case frequency corner with the fastest threshold      |
+|        | voltage.                                                    |
+|        |                                                             |
+|        | Metric details to be supplied later.                        |
++--------+-------------------------------------------------------------+
+
+Physical design rules
+---------------------
+
+As different teams have different design rules and flows, and to ease
+the integration in FPGA and ASIC design flows:
+
++---------+------------------------------------------------------------+
+| PDR-10  | CV32E20 should have a configurable global reset signal:    |
+|         | synchronous/asynchronous, active high/low.                 |
+|         |                                                            |
+|         | For asynchronous resets, the assertion edge is treated as  |
+|         | an asynchronous event; the negation edge is treated as a   |
+|         | *synchronous* event.                                       |
++---------+------------------------------------------------------------+
+| PDR-20  | CV32E20 shall be a “super-synchronous” design with a       |
+|         | single clock input and all sequential elements operating   |
+|         | on the pos-edge of the clock.                              |
++---------+------------------------------------------------------------+
+| PDR-40  | CV32E20 should not include multi-cycle paths.              |
++---------+------------------------------------------------------------+
+| PDR-50  | CV32E20 should not include technology-dependent blocks.    |
+|         |                                                            |
+|         | If technology-dependent blocks are used, e.g., to improve  |
+|         | PPA on certain targets, the equivalent                     |
+|         | technology-independent block should be available. A design |
+|         | parameter can be used to select between the                |
+|         | implementations.                                           |
++---------+------------------------------------------------------------+
+| PDR-60  | For certain FPGA targets, CV32E20 may remove the reset in  |
+|         | the RTL code.                                              |
+|         |                                                            |
+|         | See [FPGAreset]_ for background information on this        |
+|         | requirement.                                               |
++---------+------------------------------------------------------------+
+
+List of Abbreviations
+=====================
+
+.. glossary::
+
+   AHB
+      Advanced High-performance Bus
+
+   ALU
+      Arithmetic/Logic Unit
+
+   AMBA
+      Arm(R)'s Advanced Microcontroller Bus Architecture 
+
+   ASIC
+      Application-Specific Integrated Circuit 
+
+   AXI
+      Advanced eXtensible Interface
+
+   CLIC
+      Core-Local Interrupt Controller
+
+   CLINT
+      RISC-V Privileged Specification Interrupt Controller
+
+   coreplex
+      Core Complex
+
+   CSR
+      Control and Status Register
+
+   CV-X-IF
+      Core-V Coprocessor (X) Interface
+
+   DTM
+      Debug Transport Module
+      
+   DUT
+      Device Under Test
+      
+   FPGA
+      Field Programmable Gate Array
+   
+   GPR(s)
+      CPU General-Purpose Register(s)
+   
+   ID/EX
+      Pipeline stage: Instruction Decode & Execute
+      
+   IF
+      Pipeline stage: Instruction Fetch
+      
+   IP
+      Intellectual Property
+      
+   ISA
+      Instruction Set Architecture
+   
+   LSU
+      CPU Load/Store Unit
+      
+   MCU
+      Microcontroller
+      
+   MHz
+      Megahertz
+      
+   MULT
+      CPU Multiplier
+      
+   OBI
+      Open Bus Interface protocol
+   
+   OSes
+      Operating Systems
+   
+   PF
+      Open Hardware Group Project Freeze 
+      
+   PLIC
+      Platform-Level Interrupt Controller
+      
+   RISC-V
+      5th generation of UC Berkeley reduced instruction set computing, pronounced as "risk-five" 
+      
+   RTL
+      Register-Transfer Language
+      
+   SoC
+      System on a Chip 
+      
+   TWG
+      Technical Working Group

doc/03_reference/cs_registers.rst

@@ -545,7 +545,7 @@ Machine Vendor ID (mvendorid)
 
 CSR Address: ``0xF11``
 
-Reset Value: ``0x0000_0000``
+Reset Value: ``CSR_MVENDORID_VALUE``
 
 Use the ``CSR_MVENDORID_VALUE`` parameter in :file:`rtl/cve2_pkg.sv` to change the fixed value.
 Details of what the ID represents can be found in the RISC-V Privileged Specification.
@@ -555,10 +555,10 @@ Machine Architecture ID (marchid)
 
 CSR Address: ``0xF12``
 
-Reset Value: ``0x0000_0016``
+Reset Value: ``CSR_MARCHID_VALUE``
 
 Use the ``CSR_MARCHID_VALUE`` parameter in :file:`rtl/cve2_pkg.sv` to change the fixed value.
-The value used is allocated specifically to Ibex.
+The value used is allocated specifically to cve2. See https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md.
 If significant changes are made a different ID should be used.
 Details of what the ID represents can be found in the RISC-V Privileged Specification.
 

doc/04_developer/concierge.rst

@@ -1,73 +0,0 @@
-.. _concierge:
-
-The Ibex Concierge
-==================
-
-.. figure:: https://upload.wikimedia.org/wikipedia/commons/8/80/France_in_XXI_Century._Concierge.jpg
-
-The Ibex Concierge is the friendly caretaker of the Ibex project.
-It's a rotating duty shared by experienced contributors to help newcomers find their way around the project, and to stay on top of the various small tasks necessary to keep the project going.
-
-The Ibex CPU project is a reasonably large open source project.
-Like all projects we experience two challenges:
-we want to lend a helping hand to new developers, answering their questions or helping them with code contributions.
-And we need to stay on top of our "caretaker" tasks, like fixing problems with our continuous integration setup, triaging issues and pull requests, etc.
-The Ibex Concierge combines these two duties in one person.
-
-Please reach out to the Ibex Concierge if you have trouble finding your way around the Ibex project.
-You can find today's Ibex Concierge in the calendar below.
-
-
-Who is Ibex Concierge today?
-----------------------------
-
-The concierge duties rotate between several core developers on a weekly basis.
-You can find today's concierge on duty in a `public calendar <https://calendar.google.com/calendar/embed?src=lowrisc.org_s0pdodkddnggdp40jusjij27h4%40group.calendar.google.com>`_.
-
-* Greg Chadwick (`@GregAC <https://github.com/gregac>`_)
-* Tom Roberts (`@tomroberts-lowrisc <https://github.com/tomroberts-lowrisc>`_)
-* Rupert Swarbrick (`@rswarbrick <https://github.com/rswarbrick>`_)
-* Pirmin Vogel (`@vogelpi <https://github.com/vogelpi>`_)
-* Philipp Wagner (`@imphil <https://github.com/imphil>`_)
-
-You can be Ibex Concierge, too.
-Please talk to any of the current concierges to discuss!
-
-.. raw:: html
-
-    <iframe src="https://calendar.google.com/calendar/embed?src=lowrisc.org_s0pdodkddnggdp40jusjij27h4%40group.calendar.google.com" style="border: 0" width="100%" height="600" frameborder="0" scrolling="no"></iframe>
-
-
-Ibex Concierge duties
----------------------
-
-The Ibex Concierge is aware of what's happening in the Ibex project, and helps to ensure that everyone feels welcome and is able to work productively.
-The list of duties includes, but isn't strictly limited to the following tasks.
-
-* Triage incoming issues and pull requests.
-
-  * Assign labels to them.
-
-  * Give initial feedback with an indication of what the next steps are.
-
-  * Answer questions if possible.
-
-  * Ask for clarifications where necessary.
-
-  * Redirect to the right developers as needed.
-
-* Track progress of open issues and pull requests.
-  Ensure contributors always know what's going on, and are informed if things take longer.
-
-* Welcome new contributors, and provide (hands-on) help to get them up to speed.
-  For example, help them get their commits into good shape, etc.
-
-* Fix or coordinate fixes to necessary infrastructure, such as the continuous integration setup in a timely manner.
-
-* Go through the list of open pull requests: ping developers if information or action is needed, close abandoned pull requests, etc.
-
-* Assist with the review and update of open issues.
-
-* At the end of the week, hand over to the next Ibex Concierge on the rota.
-
-Note the obvious: it is not the job of the Ibex Concierge to fix all bugs, implement all incoming feature requests, or be available 24/7.

doc/04_developer/index.rst

@@ -1,18 +0,0 @@
-Ibex Developer Guide
-====================
-
-Ibex is an open source project and invites everyone to contribute.
-The Ibex Developer Guide documents how Ibex is developed, both in terms of process and tools.
-
-Read on if you would like to work with the Ibex code base to fix a bug, add a feature, or reproduce the verification.
-
-.. todo::
-
-   Describe how to set up development environment, how to make changes, etc.
-   Use content from various READMEs and the CONTRIBUTING guide in the repo.
-
-.. toctree::
-   :maxdepth: 2
-   :caption: In this section
-
-   concierge

doc/Readme.md

@@ -0,0 +1,45 @@
+# CVE2 Documentation
+
+The documentation of CVE2 is written in reStructuredText and compiled to HTML using Sphinx. For more information, check https://www.sphinx-doc.org/en/master/usage/restructuredtext/index.html.
+
+## Prerequisites
+
+To build the documentation, certain prequisites need to be fulfilled. This section outlines the necessary steps on Linux. Tested on Ubuntu 20.04.
+
+Sphinx is based on Python and requires at least version 3.8. Additionally, `make` is required and can be installed through build-essential.
+
+```bash
+sudo apt update
+sudo apt install python3
+sudo apt install build-essential
+```
+
+Please verify your Python version using
+
+```bash
+python3 --version
+```
+
+The recommended way of installing Sphinx is via `pip` using
+
+```bash
+pip install -U sphinx
+```
+
+Sphinx requires certain packages to build this documentation. These are summarized in `doc/requirements.txt`. They can automatically be installed using
+
+```bash
+cd doc
+pip install -r requirements.txt
+```
+
+## Building the documentation
+
+To build the documentation, switch to the `doc` folder if not already done. Build is invoked via the `make` command. Typically, an HTML should be build. 
+
+```bash
+cd doc
+make html
+```
+
+Simply type only `make` to view other available targets.

doc/_static/css/custom.css

@@ -0,0 +1,3 @@
+.no-scrollbar-table td {
+  white-space: normal !important;
+}

doc/_static/theme_overrides.css

@@ -1,18 +0,0 @@
-/* override table width restrictions */
-@media screen and (min-width: 767px) {
-
-   .wy-table-responsive table td {
-      /* !important prevents the common CSS stylesheets from overriding
-         this as on RTD they are loaded after this stylesheet */
-      white-space: normal !important;
-   }
-
-   .wy-table-responsive {
-      overflow: visible !important;
-   }
-}
-
-.wy-nav-content {
-  max-width: 1000px !important;
-}
-

doc/conf.py

@@ -1,34 +1,53 @@
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
+# -*- coding: utf-8 -*-
 #
-# Sphinx configuration file for the Ibex documentation
+#  Copyright (c) 2020, 2023 OpenHW Group
 #
-# All configuration values have a default; values that are commented out
-# serve to show the default.
+#  Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+# 
+#  https://solderpad.org/licenses/
+# 
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+# 
+#  SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+#
+###############################################################################
+#
+# Configuration file for the Sphinx documentation builder.
+#
+# This file does only contain a selection of the most common options. For a
+# full list see the documentation:
+# http://www.sphinx-doc.org/en/master/config
+
+# -- Path setup --------------------------------------------------------------
 
 # If extensions (or modules to document with autodoc) are in another directory,
 # add these directories to sys.path here. If the directory is relative to the
 # documentation root, use os.path.abspath to make it absolute, like shown here.
 #
-import os
-import sys
-
-# Source top directory
-topsrcdir = os.path.join(os.path.dirname(__file__), '..')
-
-old_sys_path = sys.path
-try:
-    sys.path.append(os.path.join(topsrcdir, 'util'))
-    import check_tool_requirements as ctr
-finally:
-    sys.path = old_sys_path
+# import os
+# import sys
+# sys.path.insert(0, os.path.abspath('.'))
 
 
-numfig=True
-numfig_format = {'figure': 'Figure %s', 'table': 'Table %s', 'code-block': 'Listing %s'}
+# -- Project information -----------------------------------------------------
 
-# -- General configuration ------------------------------------------------
+project = 'CV32E20 Documentation'
+copyright = '2017-2018, ETH Zurich and University of Bologna, 2018-2022 lowRISC, 2022-2023 OpenHW Group'
+author = 'OpenHW Group'
+
+# The short X.Y version
+version = u'0.1'
+# The full version, including alpha/beta/rc tags
+release = u'0.1'
+
+
+# -- General configuration ---------------------------------------------------
 
 # If your documentation needs a minimal Sphinx version, state it here.
 #
@@ -38,6 +57,7 @@ numfig_format = {'figure': 'Figure %s', 'table': 'Table %s', 'code-block': 'List
 # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
 # ones.
 extensions = [
+    'sphinx.ext.autodoc',
     'sphinxcontrib.wavedrom',
     'sphinx.ext.todo',
 ]
@@ -47,7 +67,7 @@ wavedrom_html_jsinline = False
 render_using_wavedrompy = True
 
 # Add any paths that contain templates here, relative to this directory.
-templates_path = ['_templates']
+templates_path = ['ytemplates']
 
 # The suffix(es) of source filenames.
 # You can specify multiple suffix as a list of string:
@@ -58,21 +78,6 @@ source_suffix = '.rst'
 # The master toctree document.
 master_doc = 'index'
 
-# General information about the project.
-project = 'Ibex Documentation'
-copyright = '2017-2018, ETH Zurich and University of Bologna, 2018-present lowRISC'
-author = 'lowRISC contributors'
-
-# The version info for the project you're documenting, acts as replacement for
-# |version| and |release|, also used in various other places throughout the
-# built documents.
-#
-# The short X.Y version.
-version = ''
-# The full version, including alpha/beta/rc tags.
-from setuptools_scm import get_version
-release = get_version(root=topsrcdir)
-
 # The language for content autogenerated by Sphinx. Refer to documentation
 # for a list of supported languages.
 #
@@ -82,43 +87,60 @@ language = 'en'
 
 # List of patterns, relative to source directory, that match files and
 # directories to ignore when looking for source files.
-# This patterns also effect to html_static_path and html_extra_path
-exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store', 'venv']
+# This pattern also affects html_static_path and html_extra_path.
+exclude_patterns = []
+
+# Numbering
+numfig=True
+numfig_format = {'figure': 'Figure %s', 'table': 'Table %s', 'code-block': 'Listing %s'}
 
 # The name of the Pygments (syntax highlighting) style to use.
-pygments_style = 'sphinx'
-
-# If true, `todo` and `todoList` produce output, else they produce nothing.
-todo_include_todos = True
+pygments_style = None
 
 
-# -- Options for HTML output ----------------------------------------------
+# -- Options for HTML output -------------------------------------------------
 
 # The theme to use for HTML and HTML Help pages.  See the documentation for
 # a list of builtin themes.
 #
+#html_theme = 'alabaster'
 html_theme = 'sphinx_rtd_theme'
 
 # Theme options are theme-specific and customize the look and feel of a theme
 # further.  For a list of options available for each theme, see the
 # documentation.
 #
-html_theme_options = {
-    'style_nav_header_background': '#E53651'
-}
-
-html_logo = 'images/logo.svg'
+html_theme_options = {'style_nav_header_background': '#DDDDDD'}
+html_logo = 'images/openhw-landscape.svg'
 
 # Add any paths that contain custom static files (such as style sheets) here,
 # relative to this directory. They are copied after the builtin static files,
 # so a file named "default.css" will overwrite the builtin "default.css".
+#html_static_path = ['ystatic']
+# Set html_static_path to null on the advice of RTDs:
 html_static_path = ['_static']
 
+# Custom sidebar templates, must be a dictionary that maps document names
+# to template names.
+#
+# The default sidebars (for documents that don't match any pattern) are
+# defined by theme itself.  Builtin themes are using these templates by
+# default: ``['localtoc.html', 'relations.html', 'sourcelink.html',
+# 'searchbox.html']``.
+#
+# html_sidebars = {}
+
 html_css_files = [
-    'theme_overrides.css', # Fix wide tables in RTD theme
+  'css/custom.css',
 ]
 
-# -- Options for LaTeX output ---------------------------------------------
+# -- Options for HTMLHelp output ---------------------------------------------
+
+# Output file base name for HTML help builder.
+htmlhelp_basename = 'CORE-V_CV32E20_Documentation'
+
+
+# -- Options for LaTeX output ------------------------------------------------
 
 latex_elements = {
     # The paper size ('letterpaper' or 'a4paper').
@@ -142,39 +164,76 @@ latex_elements = {
 # (source start file, target name, title,
 #  author, documentclass [howto, manual, or own class]).
 latex_documents = [
-    (master_doc, 'ibex.tex', u'Ibex Documentation',
-     u'lowRISC', 'manual'),
+    (master_doc, 'CV32E20_Documentation.tex', u'CV32E20 Documentation',
+     u'OpenHW Group', 'manual'),
 ]
 
-latex_logo = ''
 
-# -- Options for manual page output ---------------------------------------
+# -- Options for manual page output ------------------------------------------
 
 # One entry per manual page. List of tuples
 # (source start file, name, description, authors, manual section).
 man_pages = [
-    (master_doc, 'ibex', u'Ibex Documentation',
+    (master_doc, 'CV32E20_Documentation.tex', u'CORE-V-Docs Documentation',
      [author], 1)
 ]
 
 
-# -- Options for Texinfo output -------------------------------------------
+# -- Options for Texinfo output ----------------------------------------------
 
 # Grouping the document tree into Texinfo files. List of tuples
 # (source start file, target name, title, author,
 #  dir menu entry, description, category)
 texinfo_documents = [
-    (master_doc, 'ibex', u'Ibex Documentation',
-     author, 'ibex', 'Ibex RV32 CPU core',
+    (master_doc, 'CV32E20_Documentation.tex', u'CORE-V-Docs Documentation',
+     author, 'Documentation', 'Documentation for CV32E20 CORE-V processor core.',
      'Miscellaneous'),
 ]
 
+
+# -- Options for Epub output -------------------------------------------------
+
+# Bibliographic Dublin Core info.
+epub_title = project
+
+# The unique identifier of the text. This can be a ISBN number
+# or the project homepage.
+#
+# epub_identifier = ''
+
+# A unique identification for the text.
+#
+# epub_uid = ''
+
+# A list of files that should not be packed into the epub file.
+epub_exclude_files = ['search.html']
+
+
+# -- Extension configuration -------------------------------------------------
+
+# -- Options for todo extension ----------------------------------------------
+
+# If true, `todo` and `todoList` produce output, else they produce nothing.
+todo_include_todos = True
+
 # -- Tool version numbers -------------------------------------------------
 
 # Add minimum versions of required tools as variables for use inside the
 # documentation.
+import os
+import sys
+
+# Source top directory
+topsrcdir = os.path.join(os.path.dirname(__file__), '..')
+
+old_sys_path = sys.path
+try:
+    sys.path.append(os.path.join(topsrcdir, 'util'))
+    import check_tool_requirements as ctr
+finally:
+    sys.path = old_sys_path
 tool_reqs = ctr.read_tool_requirements()
 rst_epilog = ""
 for tool, req in tool_reqs.items():
     rst_epilog += (".. |tool_requirements.{}| replace:: {}\n"
-                   .format(tool, req.min_version))
+                   .format(tool, req.min_version))

doc/images/openhw-landscape.svg

@@ -0,0 +1,311 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!-- Generator: Adobe Illustrator 16.0.4, SVG Export Plug-In . SVG Version: 6.00 Build 0)  -->
+<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
+<svg version="1.1" id="Layer_1" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" x="0px" y="0px"
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+	 xml:space="preserve">
+<g>
+	<g>
+		<path fill="#20AA4D" d="M38.589,37.644c0.665,0.646,1.379,1.235,2.136,1.775v-1.775H38.589z"/>
+		<path fill="#20AA4D" d="M40.726,9.98c-0.136,0.096-0.268,0.197-0.398,0.298h0.398V9.98z"/>
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doc/index.rst

@@ -1,15 +1,16 @@
-Ibex: An embedded 32 bit RISC-V CPU core
-========================================
+CV32E20: An embedded 32-bit RISC-V CPU core
+===========================================
 
-Ibex is a production-quality open source 32 bit RISC-V CPU core written in SystemVerilog.
-The CPU core is heavily parametrizable and well suited for embedded control applications.
-Ibex is being extensively verified and has seen multiple tape-outs.
+CV32E20 is a production-quality open source 32-bit RISC-V CPU core written in SystemVerilog.
+The CPU core is based on the Ibex core, but simplified and verified under the OpenHW Group.
 
-You are now reading the Ibex documentation.
-The documentation is split into four parts.
+You are now reading the CV32E20 documentation.
+The documentation is split into multiple parts.
 
-The :doc:`Overview documentation <01_overview/index>` looks at Ibex from high up.
-It answers questions like what are the high-level properties of Ibex, which standards is Ibex following, and where is it typically used.
+The :doc:`Technical Specification <01_specification/index>` contains the technical specification of CV32E20.
+It defines the supported features in the form of requirements.
+
+The remaining parts of documentation are inherited from the Ibex project. They are kept for reference and will be reworked in the future.
 
 The :doc:`User Guide <02_user/index>` provides all necessary information to use Ibex.
 It is aimed at hardware developers integrating Ibex into a design, and software developers writing software running on Ibex.
@@ -17,14 +18,10 @@ It is aimed at hardware developers integrating Ibex into a design, and software
 The :doc:`Reference Guide <03_reference/index>` provides background information.
 It describes the design in detail, discusses the verification approach and the resulting testbench structures, and generally helps to understand Ibex in depth.
 
-The :doc:`Developer Guide <04_developer/index>` is aimed at people making changes to Ibex itself.
-Since Ibex is open source, every user of Ibex is encouraged to learn how to adapt Ibex to their use case, and be part of the open development process.
-
 .. toctree::
-   :maxdepth: 2
+   :maxdepth: 3
    :hidden:
 
-   01_overview/index.rst
+   01_specification/index.rst
    02_user/index.rst
    03_reference/index.rst
-   04_developer/index.rst

doc/requirements.txt

@@ -5,3 +5,4 @@ sphinx~=3.0
 sphinx_rtd_theme
 sphinxcontrib-wavedrom
 wavedrom>=1.9.0rc1
+Jinja2<3.1

rtl/cve2_controller.sv

@@ -140,7 +140,7 @@ module cve2_controller #(
   logic enter_debug_mode;
   logic ebreak_into_debug;
   logic handle_irq;
-
+  logic irq_enabled;
   logic [3:0] mfip_id;
   logic       unused_irq_timer;
 
@@ -159,7 +159,7 @@ module cve2_controller #(
   always_ff @(negedge clk_i) begin
     // print warning in case of decoding errors
     if ((ctrl_fsm_cs == DECODE) && instr_valid_i && !instr_fetch_err_i && illegal_insn_d) begin
-      $display("%t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, cve2_core.hart_id_i,
+     $display("%m @ %t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, cve2_core.hart_id_i,
                cve2_id_stage.pc_id_i, cve2_id_stage.instr_rdata_i);
     end
   end
@@ -291,19 +291,22 @@ module cve2_controller #(
                              priv_mode_i == PRIV_LVL_U ? debug_ebreaku_i :
                                                          1'b0;
 
+  // MIE bit only applies when in M mode
+  assign irq_enabled = csr_mstatus_mie_i | (priv_mode_i == PRIV_LVL_U);
+
   // Interrupts including NMI are ignored,
   // - while in debug mode [Debug Spec v0.13.2, p.39],
   // - while in NMI mode (nested NMIs are not supported, NMI has highest priority and
   //   cannot be interrupted by regular interrupts).
   // - while single stepping.
-  assign handle_irq = ~debug_mode_q & ~debug_single_step_i & ~nmi_mode_q &
+  assign handle_irq = ~debug_mode_q & ~nmi_mode_q &
       (irq_nm_i | (irq_pending_i & csr_mstatus_mie_i));
 
   // generate ID of fast interrupts, highest priority to lowest ID
   always_comb begin : gen_mfip_id
     mfip_id = 4'd0;
 
-    for (int i = 14; i >= 0; i--) begin
+    for (int i = 15; i >= 0; i--) begin
       if (irqs_i.irq_fast[i]) begin
         mfip_id = i[3:0];
       end
@@ -499,12 +502,13 @@ module cve2_controller #(
           if (irq_nm_i && !nmi_mode_q) begin
             exc_cause_o = EXC_CAUSE_IRQ_NM;
             nmi_mode_d  = 1'b1; // enter NMI mode
-          end else if (irqs_i.irq_fast != 15'b0) begin
+          end else if (irqs_i.irq_fast != 16'b0) begin
             // generate exception cause ID from fast interrupt ID:
             // - first bit distinguishes interrupts from exceptions,
-            // - second bit adds 16 to fast interrupt ID
-            // for example EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16}
-            exc_cause_o = exc_cause_e'({2'b11, mfip_id});
+            // - third bit adds 16 to fast interrupt ID so that the interrup 0 becomes 16 and the interrupt 15 becomes 31 (hence 5bits)
+            // - second bit is always 0 as the FAST interrupts are represented in the first 5bits, the 6th is always 0 cause is used by the NMI (in that case is 1 as represented by the number 32)
+            // for example EXC_CAUSE_IRQ_FAST_0 = {1'b1, 6'd16}
+            exc_cause_o = exc_cause_e'({3'b101, mfip_id});
           end else if (irqs_i.irq_external) begin
             exc_cause_o = EXC_CAUSE_IRQ_EXTERNAL_M;
           end else if (irqs_i.irq_software) begin
@@ -531,11 +535,11 @@ module cve2_controller #(
 
         csr_save_cause_o = 1'b1;
         if (trigger_match_i) begin
-          debug_cause_o = DBG_CAUSE_TRIGGER;
-        end else if (debug_single_step_i) begin
-          debug_cause_o = DBG_CAUSE_STEP;
+          debug_cause_o = DBG_CAUSE_TRIGGER;     // (priority 4)
+        end else if (debug_req_i) begin
+          debug_cause_o = DBG_CAUSE_HALTREQ;     // (priority 1)
         end else begin
-          debug_cause_o = DBG_CAUSE_HALTREQ;
+          debug_cause_o = DBG_CAUSE_STEP;        // (priority 0, lowest)
         end
 
         // enter debug mode
@@ -679,9 +683,14 @@ module cve2_controller #(
         // Leave all other signals as is to ensure CSRs and PC get set as if
         // core was entering exception handler, entry to debug mode will then
         // see the appropriate state and setup dpc correctly.
+
         // If an EBREAK instruction is causing us to enter debug mode on the
         // same cycle as a debug_req or single step, honor the EBREAK and
-        // proceed to DBG_TAKEN_ID.
+        // proceed to DBG_TAKEN_ID, as it has the highest priority.
+        // [Debug Spec v1.0.0-STABLE, p.53]
+        // cause==EBREAK    -> prio 3 (highest)
+        // cause==debug_req -> prio 2
+        // cause==step      -> prio 1 (lowest)
         if (enter_debug_mode_prio_q && !(ebrk_insn_prio && ebreak_into_debug)) begin
           ctrl_fsm_ns = DBG_TAKEN_IF;
         end

rtl/cve2_core.sv

@@ -58,7 +58,7 @@ module cve2_core import cve2_pkg::*; #(
   input  logic                         irq_software_i,
   input  logic                         irq_timer_i,
   input  logic                         irq_external_i,
-  input  logic [14:0]                  irq_fast_i,
+  input  logic [15:0]                  irq_fast_i,
   input  logic                         irq_nm_i,       // non-maskeable interrupt
   output logic                         irq_pending_o,
 
@@ -950,8 +950,10 @@ module cve2_core import cve2_pkg::*; #(
 
   // Factor in exceptions taken in ID so RVFI tracking picks up flushed instructions that took
   // a trap
-  assign rvfi_id_done = instr_id_done | (id_stage_i.controller_i.rvfi_flush_next &
-                                         id_stage_i.controller_i.exc_req_d);
+  // MRET causes MSTATUS to get written one clock later. Fix rvfi_valid when executing MRET
+  assign rvfi_id_done = (instr_id_done & !id_stage_i.controller_i.mret_insn)|
+                         id_stage_i.csr_restore_mret_id_o |
+                        (id_stage_i.controller_i.rvfi_flush_next & id_stage_i.controller_i.exc_req_d);
 
   // Without writeback stage first RVFI stage is output stage so simply valid the cycle after
   // instruction leaves ID/EX (and so has retired)

rtl/cve2_cs_registers.sv

@@ -53,7 +53,7 @@ module cve2_cs_registers #(
   input  logic                 irq_software_i,
   input  logic                 irq_timer_i,
   input  logic                 irq_external_i,
-  input  logic [14:0]          irq_fast_i,
+  input  logic [15:0]          irq_fast_i,
   input  logic                 nmi_mode_i,
   output logic                 irq_pending_o,          // interrupt request pending
   output cve2_pkg::irqs_t      irqs_o,                 // interrupt requests qualified with mie
@@ -169,7 +169,7 @@ module cve2_cs_registers #(
   logic        mscratch_en;
   logic [31:0] mepc_q, mepc_d;
   logic        mepc_en;
-  logic  [5:0] mcause_q, mcause_d;
+  logic  [6:0] mcause_q, mcause_d;
   logic        mcause_en;
   logic [31:0] mtval_q, mtval_d;
   logic        mtval_en;
@@ -189,7 +189,7 @@ module cve2_cs_registers #(
   status_stk_t mstack_q, mstack_d;
   logic        mstack_en;
   logic [31:0] mstack_epc_q, mstack_epc_d;
-  logic  [5:0] mstack_cause_q, mstack_cause_d;
+  logic  [6:0] mstack_cause_q, mstack_cause_d;
 
   // PMP Signals
   logic [31:0]                 pmp_addr_rdata  [PMP_MAX_REGIONS];
@@ -318,7 +318,7 @@ module cve2_cs_registers #(
       CSR_MEPC: csr_rdata_int = mepc_q;
 
       // mcause: exception cause
-      CSR_MCAUSE: csr_rdata_int = {mcause_q[5], 26'b0, mcause_q[4:0]};
+      CSR_MCAUSE: csr_rdata_int = {mcause_q[6], 25'b0, mcause_q[5:0]};
 
       // mtval: trap value
       CSR_MTVAL: csr_rdata_int = mtval_q;
@@ -468,6 +468,16 @@ module cve2_cs_registers #(
         illegal_csr = 1'b1;
       end
     endcase
+
+    if (!PMPEnable) begin
+      if (csr_addr inside {CSR_PMPCFG0,   CSR_PMPCFG1,   CSR_PMPCFG2,   CSR_PMPCFG3,
+                           CSR_PMPADDR0,  CSR_PMPADDR1,  CSR_PMPADDR2,  CSR_PMPADDR3,
+                           CSR_PMPADDR4,  CSR_PMPADDR5,  CSR_PMPADDR6,  CSR_PMPADDR7,
+                           CSR_PMPADDR8,  CSR_PMPADDR9,  CSR_PMPADDR10, CSR_PMPADDR11,
+                           CSR_PMPADDR12, CSR_PMPADDR13, CSR_PMPADDR14, CSR_PMPADDR15}) begin
+        illegal_csr = 1'b1;
+      end
+    end
   end
 
   // write logic
@@ -482,7 +492,7 @@ module cve2_cs_registers #(
     mepc_en      = 1'b0;
     mepc_d       = {csr_wdata_int[31:1], 1'b0};
     mcause_en    = 1'b0;
-    mcause_d     = {csr_wdata_int[31], csr_wdata_int[4:0]};
+    mcause_d     = {csr_wdata_int[31], csr_wdata_int[5:0]};
     mtval_en     = 1'b0;
     mtval_d      = csr_wdata_int;
     mtvec_en     = csr_mtvec_init_i;
@@ -807,7 +817,7 @@ module cve2_cs_registers #(
 
   // MCAUSE
   cve2_csr #(
-    .Width     (6),
+    .Width     (7),
     .ShadowCopy(1'b0),
     .ResetValue('0)
   ) u_mcause_csr (
@@ -939,7 +949,7 @@ module cve2_cs_registers #(
 
   // MSTACK_CAUSE
   cve2_csr #(
-    .Width     (6),
+    .Width     (7),
     .ShadowCopy(1'b0),
     .ResetValue('0)
   ) u_mstack_cause_csr (

rtl/cve2_if_stage.sv

@@ -101,7 +101,7 @@ module cve2_if_stage import cve2_pkg::*; #(
 
   logic       [31:0] exc_pc;
 
-  logic        [5:0] irq_id;
+  logic        [6:0] irq_id;
   logic              unused_irq_bit;
 
   logic              if_id_pipe_reg_we; // IF-ID pipeline reg write enable
@@ -116,16 +116,16 @@ module cve2_if_stage import cve2_pkg::*; #(
 
   // extract interrupt ID from exception cause
   assign irq_id         = {exc_cause};
-  assign unused_irq_bit = irq_id[5];   // MSB distinguishes interrupts from exceptions
+  assign unused_irq_bit = irq_id[6];   // MSB distinguishes interrupts from exceptions
 
   // exception PC selection mux
   always_comb begin : exc_pc_mux
     unique case (exc_pc_mux_i)
-      EXC_PC_EXC:     exc_pc = { csr_mtvec_i[31:8], 8'h00                    };
-      EXC_PC_IRQ:     exc_pc = { csr_mtvec_i[31:8], 1'b0, irq_id[4:0], 2'b00 };
+      EXC_PC_EXC:     exc_pc = { csr_mtvec_i[31:8], 8'h00              };
+      EXC_PC_IRQ:     exc_pc = { csr_mtvec_i[31:8], irq_id[5:0], 2'b00 };
       EXC_PC_DBD:     exc_pc = DmHaltAddr;
       EXC_PC_DBG_EXC: exc_pc = DmExceptionAddr;
-      default:        exc_pc = { csr_mtvec_i[31:8], 8'h00                    };
+      default:        exc_pc = { csr_mtvec_i[31:8], 8'h00              };
     endcase
   end
 

rtl/cve2_pkg.sv

@@ -292,26 +292,25 @@ package cve2_pkg;
     logic        irq_software;
     logic        irq_timer;
     logic        irq_external;
-    logic [14:0] irq_fast; // 15 fast interrupts,
-                          // one interrupt is reserved for NMI (not visible through mip/mie)
+    logic [15:0] irq_fast; // 16 fast interrupts
   } irqs_t;
 
   // Exception cause
-  typedef enum logic [5:0] {
-    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 5'd03},
-    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 5'd07},
-    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 5'd11},
-    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 5'd16},
-    // EXC_CAUSE_IRQ_FAST_14     = {1'b1, 5'd30},
-    EXC_CAUSE_IRQ_NM             = {1'b1, 5'd31}, // == EXC_CAUSE_IRQ_FAST_15
-    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 5'd00},
-    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd01},
-    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 5'd02},
-    EXC_CAUSE_BREAKPOINT         = {1'b0, 5'd03},
-    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 5'd05},
-    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07},
-    EXC_CAUSE_ECALL_UMODE        = {1'b0, 5'd08},
-    EXC_CAUSE_ECALL_MMODE        = {1'b0, 5'd11}
+  typedef enum logic [6:0] {
+    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 6'd03},
+    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 6'd07},
+    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 6'd11},
+    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 6'd16},
+    // EXC_CAUSE_IRQ_FAST_15     = {1'b1, 6'd31},
+    EXC_CAUSE_IRQ_NM             = {1'b1, 6'd32},
+    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 6'd00},
+    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},
+    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 6'd02},
+    EXC_CAUSE_BREAKPOINT         = {1'b0, 6'd03},
+    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 6'd05},
+    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},
+    EXC_CAUSE_ECALL_UMODE        = {1'b0, 6'd08},
+    EXC_CAUSE_ECALL_MMODE        = {1'b0, 6'd11}
   } exc_cause_e;
 
   // Debug cause
@@ -547,32 +546,31 @@ package cve2_pkg;
   parameter int unsigned CSR_MTIX_BIT      = 7;
   parameter int unsigned CSR_MEIX_BIT      = 11;
   parameter int unsigned CSR_MFIX_BIT_LOW  = 16;
-  parameter int unsigned CSR_MFIX_BIT_HIGH = 30;
+  parameter int unsigned CSR_MFIX_BIT_HIGH = 31;
 
   // CSR Machine Security Configuration bits
   parameter int unsigned CSR_MSECCFG_MML_BIT  = 0;
   parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;
   parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;
 
-  // Vendor ID
-  // No JEDEC ID has been allocated to lowRISC so the value is 0 to indicate the field is not
-  // implemented
-  localparam logic [31:0] CSR_MVENDORID_VALUE  = 32'b0;
+  // Machine Vendor ID - OpenHW JEDEC ID is '2 decimal (bank 13)'
+  parameter MVENDORID_OFFSET = 7'h2;  // Final byte without parity bit
+  parameter MVENDORID_BANK = 25'hC;  // Number of continuation codes
 
-  // Architecture ID
-  // Top bit is unset to indicate an open source project. The lower bits are an ID allocated by the
-  // RISC-V Foundation. Note this is allocated specifically to Ibex, should significant changes be
-  // made a different architecture ID should be supplied.
-  localparam logic [31:0] CSR_MARCHID_VALUE = {1'b0, 31'd22};
+  // Machine Architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)
+  parameter MARCHID = 32'd35;
+
+  localparam logic [31:0] CSR_MVENDORID_VALUE  = {MVENDORID_BANK, MVENDORID_OFFSET};
+  localparam logic [31:0] CSR_MARCHID_VALUE = MARCHID;
 
   // Implementation ID
-  // 0 indicates this field is not implemeted. Ibex implementors may wish to indicate an RTL/netlist
+  // 0 indicates this field is not implemeted. cve2 implementors may wish to indicate an RTL/netlist
   // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented
   // commit).
   localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;
 
   // Machine Configuration Pointer
-  // 0 indicates the configuration data structure does not eixst. Ibex implementors may wish to
+  // 0 indicates the configuration data structure does not eixst. cve2 implementors may wish to
   // alter this to point to their system specific configuration data structure.
   localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;
 

rtl/cve2_top.sv

@@ -53,7 +53,7 @@ module cve2_top import cve2_pkg::*; #(
   input  logic                         irq_software_i,
   input  logic                         irq_timer_i,
   input  logic                         irq_external_i,
-  input  logic [14:0]                  irq_fast_i,
+  input  logic [15:0]                  irq_fast_i,
   input  logic                         irq_nm_i,       // non-maskeable interrupt
 
   // Debug Interface

rtl/cve2_top_tracing.sv

@@ -49,7 +49,7 @@ module cve2_top_tracing import cve2_pkg::*; #(
   input  logic                         irq_software_i,
   input  logic                         irq_timer_i,
   input  logic                         irq_external_i,
-  input  logic [14:0]                  irq_fast_i,
+  input  logic [15:0]                  irq_fast_i,
   input  logic                         irq_nm_i,       // non-maskeable interrupt
 
   // Debug Interface