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Improve display for illegal instructions

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This commit is contained in:
Andreas Traber 2015-08-31 09:16:03 +02:00
parent 5f3b73ab8a
commit dd57252f60
1 changed files with 17 additions and 10 deletions
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27
controller.sv
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@ -945,16 +945,6 @@ module controller
end
endcase
// synopsys translate_off
// print warning in case of decoding errors
// note: this is done intentionally before checking RVC decoding, to
// suppress wrong (and annoying) messages during simulation
if (illegal_insn_int) begin
$warning("Illegal instruction (core %0d) at PC 0x%h:", $time, riscv_core.core_id_i);
//prettyPrintInstruction(instr_rdata_i, id_stage.current_pc_id_i);
end
// synopsys translate_on
// make sure invalid compressed instruction causes an exception
if (illegal_c_insn_i) begin
illegal_insn_int = 1'b1;
@ -981,6 +971,23 @@ module controller
end
end
`ifndef SYNTHESIS
// synopsys translate_off
// make sure we are called later so that we do not generate messages for
// glitches
always_ff @(negedge clk)
begin
// print warning in case of decoding errors
// note: this is done intentionally before checking RVC decoding, to
// suppress wrong (and annoying) messages during simulation
if (illegal_insn_o) begin
$warning("Illegal instruction (core %0d) at PC 0x%h:", $time, riscv_core.core_id_i);
//prettyPrintInstruction(instr_rdata_i, id_stage.current_pc_id_i);
end
end
// synopsys translate_on
`endif
////////////////////////////////////////////////////////////////////////////////////////////
// ____ ___ ____ _____ ____ ___ _ _ _____ ____ ___ _ _ _____ ____ //