Add a "caching" sequence for ICache testing

dv/uvm/icache/data/ibex_icache_testplan.hjson

@@ -51,7 +51,7 @@
             cached by counting transactions on the instruction bus versus
             instructions fetched.'''
       milestone: V2
-      tests: []
+      tests: ["ibex_icache_caching"]
     }
 
     {

dv/uvm/icache/dv/env/ibex_icache_env.core

@@ -21,6 +21,7 @@ filesets:
       - seq_lib/ibex_icache_base_vseq.sv: {is_include_file: true}
       - seq_lib/ibex_icache_sanity_vseq.sv: {is_include_file: true}
       - seq_lib/ibex_icache_passthru_vseq.sv: {is_include_file: true}
+      - seq_lib/ibex_icache_caching_vseq.sv: {is_include_file: true}
     file_type: systemVerilogSource
 
 targets:

dv/uvm/icache/dv/env/seq_lib/ibex_icache_caching_vseq.sv

@@ -0,0 +1,23 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_caching_vseq extends ibex_icache_base_vseq;
+
+  `uvm_object_utils(ibex_icache_caching_vseq)
+  `uvm_object_new
+
+  virtual task pre_start();
+    super.pre_start();
+
+    // Constrain branch targets and force the cache to be enabled
+    core_seq.constrain_branches = 1'b1;
+    core_seq.initial_enable     = 1'b1;
+    core_seq.const_enable       = 1'b1;
+
+    // Don't invalidate the cache (since that will lower the hit rate)
+    core_seq.no_invalidate = 1'b1;
+
+  endtask : pre_start
+
+endclass : ibex_icache_caching_vseq

dv/uvm/icache/dv/env/seq_lib/ibex_icache_vseq_list.sv

@@ -5,3 +5,4 @@
 `include "ibex_icache_base_vseq.sv"
 `include "ibex_icache_sanity_vseq.sv"
 `include "ibex_icache_passthru_vseq.sv"
+`include "ibex_icache_caching_vseq.sv"

dv/uvm/icache/dv/ibex_icache_core_agent/seq_lib/ibex_icache_core_base_seq.sv

@@ -24,6 +24,9 @@ class ibex_icache_core_base_seq extends dv_base_seq #(
   // setting.
   bit const_enable = 1'b0;
 
+  // If this bit is set, we will never invalidate the cache (useful for hit ratio tracking)
+  bit no_invalidate = 1'b0;
+
   // Number of test items (note that a single test item may contain many instruction fetches)
   protected rand int count;
   constraint c_count { count inside {[800:1000]}; }
@@ -85,6 +88,9 @@ class ibex_icache_core_base_seq extends dv_base_seq #(
        // time in each mode (note that each transaction here results in multiple instruction
        // fetches)
        enable dist { cache_enabled :/ 49, ~cache_enabled :/ 1 };
+
+       // If no_invalidate is set, we shouldn't ever touch the invalidate line.
+       no_invalidate -> invalidate == 1'b0;
     )
 
     finish_item(req);

dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson

@@ -49,6 +49,12 @@
       uvm_test_seq: ibex_icache_passthru_vseq
       run_opts: ["+test_timeout_ns=1000000000"]
     }
+
+    {
+      name: ibex_icache_caching
+      uvm_test_seq: ibex_icache_caching_vseq
+      run_opts: ["+test_timeout_ns=1000000000"]
+    }
   ]
 
   // List of regressions.
@@ -56,7 +62,8 @@
     {
       name: sanity
       tests: ["ibex_icache_sanity",
-              "ibex_icache_passthru"]
+              "ibex_icache_passthru",
+              "ibex_icache_caching"]
     }
   ]
 }