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correcting copywrite string
Signed-off-by: Lee Hoff <lhoff@intrinsix.com>
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Lee Hoff
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2 changed files with 275 additions and 0 deletions
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examples/obi2ahb/OBI2AHBM_Adapter Design Spec.pdf
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examples/obi2ahb/OBI2AHBM_Adapter Design Spec.pdf
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examples/obi2ahb/obi2ahbm_adapter.sv
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examples/obi2ahb/obi2ahbm_adapter.sv
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// Copyright 2023 Intrinsix Corp.
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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// ============================================================================
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//
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// Description : OBI to AHB-Lite Master Adaptor
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//
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module obi2ahbm_adapter (
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// Clock and reset
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input hclk, // (I) AHB clock
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input hreset_n, // (I) AHB reset, active LOW
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// AHB master interface
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output logic [31:0] haddr_m, // (O) 32-bit AHB system address bus
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output logic [2:0] hburst_m, // (O) Burst type
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output logic hmastlock_m, // (O) Sequence lock
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output logic [3:0] hprot_m, // (O) Protection control
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output logic [2:0] hsize_m, // (O) Transfer size
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output logic [1:0] htrans_m, // (O) Transfer type
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output logic [31:0] hwdata_m, // (O) 32-bit AHB write data bus
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output logic hwrite_m, // (O) Transfer direction
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input logic [31:0] hrdata_m, // (I) 32-bit AHB read data bus
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input logic hready_m, // (I) Status of transfer
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input logic hresp_m, // (I) Transfer response
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// Data interface from core
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input logic data_req_o, // (I) Request ready
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output logic data_gnt_i, // (O) The other side accepted the request
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output logic data_rvalid_i, // (O) Read data valid when high
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input logic data_we_o, // (I) Write enable (active HIGH)
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input logic [3:0] data_be_o, // (I) Byte enable
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input logic [31:0] data_addr_o, // (I) Address
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input logic [31:0] data_wdata_o, // (I) Write data
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output logic [31:0] data_rdata_i, // (O) Read data
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output logic data_err_i, // (O) Error
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input logic pending_dbus_xfer, // (I) Asserted if data bus is busy from other transactions
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// Miscellaneous
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input logic priv_mode // (I) Privilege mode (from core. 1=machine mode, 0=user mode)
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);
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// ********** //
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// Parameters //
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// ********** //
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parameter HPROT_NONCACHEABLE = 1'b0;
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parameter HPROT_NONBUFFERABLE = 1'b0;
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parameter HPROT_DATAACCESS = 1'b1;
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parameter MACHINE_MODE = 1'b1;
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parameter HBURST_SINGLE = 3'b000;
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parameter TIE_LO = 1'b0;
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parameter AHB_FSM_WAIT = 2'b00;
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parameter AHB_FSM_DATA = 2'b10;
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// ********** //
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// Wires/Regs //
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// ********** //
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logic [1:0] ahb_fsm_reg;
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logic [1:0] ahb_fsm_reg_nxt;
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logic [31:0] haddr_m_reg;
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logic [3:0] hprot_m_reg;
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logic [2:0] hsize_m_reg;
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logic hwrite_m_reg;
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logic data_err_i_nxt;
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logic [31:0] data_rdata_i_reg;
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logic [31:0] hwdata_m_nxt;
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logic prev_data_gnt_i;
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// ********************** //
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// Continuous assignments //
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// ********************** //
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// These signals are unused, so OK that they are tied to a constant
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// lint_checking TIELOG off
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// Only single bursts are supported
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assign hburst_m = HBURST_SINGLE;
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// hmastlock_m is not used, so it is tied low
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assign hmastlock_m = TIE_LO;
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// lint_checking TIELOG on
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// A grant should only happen on a request, and if the AHB side is ready
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// to respond. Don't initiate an AHB xfer if the data bus is busy from
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// other pending xfers
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assign data_gnt_i = hready_m && data_req_o && !pending_dbus_xfer;
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// The valid signal should only assert when transitioning to the DATA state
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assign data_rvalid_i = ahb_fsm_reg == AHB_FSM_DATA ? hready_m : 1'b0;
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// ************* //
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// Clocked Logic //
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// ************* //
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always @ (posedge hclk or negedge hreset_n) begin
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if (!hreset_n) begin
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data_err_i <= 1'b0;
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data_rdata_i_reg <= 32'h00000000;
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haddr_m_reg <= 32'h00000000;
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hprot_m_reg <= {HPROT_NONCACHEABLE, HPROT_NONBUFFERABLE, MACHINE_MODE, HPROT_DATAACCESS};
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hsize_m_reg <= 3'b000;
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// Write data needs to come one cycle after per AHB protocol
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hwdata_m <= 32'h00000000;
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hwrite_m_reg <= 1'b0;
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ahb_fsm_reg <= AHB_FSM_WAIT;
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prev_data_gnt_i <= 1'b0;
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end
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else begin
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data_err_i <= data_err_i_nxt;
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data_rdata_i_reg <= data_rdata_i;
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haddr_m_reg <= haddr_m;
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hprot_m_reg <= hprot_m;
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hsize_m_reg <= hsize_m;
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hwdata_m <= hwdata_m_nxt;
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hwrite_m_reg <= hwrite_m;
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ahb_fsm_reg <= ahb_fsm_reg_nxt;
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if (!data_rvalid_i) begin
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prev_data_gnt_i <= data_gnt_i | prev_data_gnt_i;
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end else begin
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prev_data_gnt_i <= data_gnt_i;
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end
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end
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end
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// ******************* //
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// Combinational Logic //
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// ******************* //
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always @ (*) begin
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// Signal that the current request errored out and the read is invalid if
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// an AHB error response is received
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data_err_i_nxt = hresp_m;
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end
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//AHB Logic
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always @ (*) begin
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hprot_m = hprot_m_reg;
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haddr_m = haddr_m_reg;
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hwrite_m = hwrite_m_reg;
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// lint_checking TIELOG off
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// If htrans_m is not driven to non-seq while data_gnt_i is set
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// then it should be idle and set to (2'b00)
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htrans_m = 2'b00;
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// lint_checking TIELOG on
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hwdata_m_nxt = hwdata_m;
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hsize_m = hsize_m_reg;
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unique case (ahb_fsm_reg)
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AHB_FSM_WAIT: begin
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// Idles until data_gnt_i is received
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// Once data_gnt_i is received, this is the address phase of AHB
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// and all ahb signals are fed through from the core
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if (data_gnt_i) begin
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// lint_checking TIELOG off
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// Non-bufferable, non-cacheable data accesses are supported. The
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// privilege bit, hprot_m[1], is driven by the privilege mode
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// that the core is currently in (1 for machine, 0 for user)
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hprot_m = {HPROT_NONCACHEABLE, HPROT_NONBUFFERABLE, priv_mode, HPROT_DATAACCESS};
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// lint_checking TIELOG on
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// The address, transfer request, and write enable can be fed
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// through from the core to the corresponding AHB signals. For
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// htrans_m, if data_gnt_i is given, the ahb is in address phase,
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// and the transaction is non-sequential (1'b10).
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haddr_m = data_addr_o;
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hwrite_m = data_we_o;
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// lint_checking TIELOG off
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htrans_m = 2'b10;
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// lint_checking TIELOG on
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// Write data needs to be in data phase (After data_gnt_i is de-asserted)
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// So the data fromthe core is registered to save it for completing the transaction
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hwdata_m_nxt = data_wdata_o;
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// lint_checking TIELOG off
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// Only word (32-bit), half-word (16-bit), or byte (8-bit)
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// aligned transfers are supported. Invalid responses default to
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hsize_m[2] = TIE_LO;
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// lint_checking TIELOG on
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hsize_m[1] = &data_be_o;
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hsize_m[0] = (data_be_o[3] & data_be_o[2]) ^ (data_be_o[1] & data_be_o[0]);
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end
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end
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AHB_FSM_DATA: begin
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// DATA phase
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// read data is fed through from the core
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data_rdata_i = hrdata_m;
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// If data_gnt_i is also given during the data phase, then it is also
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// the subsequent address phase, so the necessary signals get
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// passed through from the core
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if (data_gnt_i) begin
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// lint_checking TIELOG off
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// Non-bufferable, non-cacheable data accesses are supported. The
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// privilege bit, hprot_m[1], is driven by the privilege mode
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// that the core is currently in (1 for machine, 0 for user)
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hprot_m = {HPROT_NONCACHEABLE, HPROT_NONBUFFERABLE, priv_mode, HPROT_DATAACCESS};
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// lint_checking TIELOG on
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// The address, transfer request, and write enable can be fed
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// through from the core to the corresponding AHB signals. For
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// htrans_m, if data_gnt_i is given, the ahb is in address phase,
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// and the transaction is non-sequential (1'b10).
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haddr_m = data_addr_o;
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hwrite_m = data_we_o;
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// lint_checking TIELOG off
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htrans_m = 2'b10;
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// lint_checking TIELOG on
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// Write data needs to be in data phase (After data_gnt_i is de-asserted)
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// So the data fromthe core is registered to save it for completing the transaction
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hwdata_m_nxt = data_wdata_o;
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// lint_checking TIELOG off
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// Only word (32-bit), half-word (16-bit), or byte (8-bit)
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// aligned transfers are supported. Invalid responses default to
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hsize_m[2] = TIE_LO;
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// lint_checking TIELOG on
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hsize_m[1] = &data_be_o;
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hsize_m[0] = (data_be_o[3] & data_be_o[2]) ^ (data_be_o[1] & data_be_o[0]);
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end
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end
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endcase
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end
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//FSM
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always @ (*) begin
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ahb_fsm_reg_nxt = ahb_fsm_reg;
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unique case (ahb_fsm_reg)
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// IDLE/ADDRESS phase
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// Waits until "ADDRESS Phase" occurs during data_gnt_i
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AHB_FSM_WAIT: begin
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if (data_gnt_i) begin
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ahb_fsm_reg_nxt = AHB_FSM_DATA;
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end
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end
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// DATA/ADDRESS phase
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// DATA phase for alread started transaction.
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// If data_gnt_i it is also the ADDRESS phase for the next set of data so it stays
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// in the data phase on the next cycle
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AHB_FSM_DATA: begin
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if (data_rvalid_i) begin
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if (data_gnt_i) begin
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ahb_fsm_reg_nxt = AHB_FSM_DATA;
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end else begin
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ahb_fsm_reg_nxt = AHB_FSM_WAIT;
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end
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end
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end
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endcase
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end
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// lint_checking TRNMBT on
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// lint_checking HASUPC on
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endmodule : obi2ahbm_adapter
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