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Update google_riscv-dv to e81acc9 (#257)
Update code from upstream repository https://github.com/google/riscv- dv to revision e81acc9ab4f692ff205a207c2dc3d9f2b0284d39 * Merge pull request #89 from google/dev (taoliug) * Fix mtvec alignement (Tao Liu)
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2 changed files with 4 additions and 4 deletions
2
vendor/google_riscv-dv.lock.hjson
vendored
2
vendor/google_riscv-dv.lock.hjson
vendored
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@ -9,6 +9,6 @@
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upstream:
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{
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url: https://github.com/google/riscv-dv
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rev: 73274f227000f1316cb201a8503aad437e427948
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rev: e81acc9ab4f692ff205a207c2dc3d9f2b0284d39
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}
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}
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@ -645,9 +645,6 @@ class riscv_asm_program_gen extends uvm_object;
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bit is_interrupt = 'b1;
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string tvec_name;
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string instr[$];
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// The trap handler will occupy one 4KB page, it will be allocated one entry in the page table
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// with a specific privileged mode.
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instr_stream.push_back(".align 12");
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if (cfg.mtvec_mode == VECTORED) begin
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gen_interrupt_vector_table(mode, status, cause, scratch, instr);
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end else begin
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@ -667,6 +664,9 @@ class riscv_asm_program_gen extends uvm_object;
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$sformatf("srli a1, a1, %0d", XLEN-1),
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$sformatf("bne a1, x0, %0smode_intr_handler", mode)};
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end
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// The trap handler will occupy one 4KB page, it will be allocated one entry in the page table
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// with a specific privileged mode.
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instr_stream.push_back(".align 12");
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tvec_name = tvec.name();
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gen_section($sformatf("%0s_handler", tvec_name.tolower()), instr);
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// Exception handler
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