Update google_riscv-dv to e81acc9 (#257)

Update code from upstream repository https://github.com/google/riscv-
dv to revision e81acc9ab4f692ff205a207c2dc3d9f2b0284d39

* Merge pull request #89 from google/dev (taoliug)
* Fix mtvec alignement (Tao Liu)
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taoliug 2019-08-21 18:22:58 -07:00 committed by GitHub
parent 03df591266
commit e2b9c17c0b
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2 changed files with 4 additions and 4 deletions

View file

@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/google/riscv-dv
rev: 73274f227000f1316cb201a8503aad437e427948
rev: e81acc9ab4f692ff205a207c2dc3d9f2b0284d39
}
}

View file

@ -645,9 +645,6 @@ class riscv_asm_program_gen extends uvm_object;
bit is_interrupt = 'b1;
string tvec_name;
string instr[$];
// The trap handler will occupy one 4KB page, it will be allocated one entry in the page table
// with a specific privileged mode.
instr_stream.push_back(".align 12");
if (cfg.mtvec_mode == VECTORED) begin
gen_interrupt_vector_table(mode, status, cause, scratch, instr);
end else begin
@ -667,6 +664,9 @@ class riscv_asm_program_gen extends uvm_object;
$sformatf("srli a1, a1, %0d", XLEN-1),
$sformatf("bne a1, x0, %0smode_intr_handler", mode)};
end
// The trap handler will occupy one 4KB page, it will be allocated one entry in the page table
// with a specific privileged mode.
instr_stream.push_back(".align 12");
tvec_name = tvec.name();
gen_section($sformatf("%0s_handler", tvec_name.tolower()), instr);
// Exception handler