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Harmonize indentation in controller
This commit is contained in:
Sven Stucki
parent
b81c7c6c57
commit
e305a8e648
1 changed files with 64 additions and 64 deletions
128
controller.sv
128
controller.sv
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@ -33,18 +33,18 @@
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module controller
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(
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input logic clk,
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input logic rst_n,
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input logic clk,
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input logic rst_n,
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input logic fetch_enable_i, // Start the decoding
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output logic core_busy_o, // Core is busy processing instructions
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input logic fetch_enable_i, // Start the decoding
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output logic core_busy_o, // Core is busy processing instructions
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input logic [31:0] instr_rdata_i, // Instruction read from instr memory/cache: (sampled in the if stage)
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output logic instr_req_o, // Fetch instruction Request:
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input logic instr_gnt_i, // grant from icache
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input logic instr_ack_i, // Acknow from instr memory or cache (means that data is available)
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input logic [31:0] instr_rdata_i, // Instruction read from instr memory/cache: (sampled in the if stage)
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output logic instr_req_o, // Fetch instruction Request:
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input logic instr_gnt_i, // grant from icache
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input logic instr_ack_i, // Acknow from instr memory or cache (means that data is available)
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output logic [2:0] pc_mux_sel_o, // Selector in the Fetch stage to select the rigth PC (normal, jump ...)
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output logic [2:0] pc_mux_sel_o, // Selector in the Fetch stage to select the rigth PC (normal, jump ...)
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// ALU signals
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output logic [`ALU_OP_WIDTH-1:0] alu_operator_o, // Operator in the Ex stage for the ALU block
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@ -58,82 +58,82 @@ module controller
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output logic [1:0] alu_cmp_mode_o, // selects comparison mode for ALU (i.e. full, any, all)
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// Mupliplicator related control signals
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output logic mult_en_o, // Multiplication operation is running
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output logic [1:0] mult_sel_subword_o, // Select subwords for 16x16 bit of multiplier
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output logic [1:0] mult_signed_mode_o, // Multiplication in signed mode
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output logic mult_mac_en_o, // Use the accumulator after multiplication
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output logic mult_en_o, // Multiplication operation is running
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output logic [1:0] mult_sel_subword_o, // Select subwords for 16x16 bit of multiplier
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output logic [1:0] mult_signed_mode_o, // Multiplication in signed mode
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output logic mult_mac_en_o, // Use the accumulator after multiplication
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output logic regfile_we_o, // Write Enable to regfile
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output logic [1:0] regfile_alu_waddr_mux_sel_o, // Select register write address for ALU/MUL operations
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output logic regfile_we_o, // Write Enable to regfile
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output logic [1:0] regfile_alu_waddr_mux_sel_o, // Select register write address for ALU/MUL operations
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output logic regfile_alu_we_o, // Write Enable to regfile 2nd port
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output logic regfile_alu_we_o, // Write Enable to regfile 2nd port
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output logic prepost_useincr_o, // When not active bypass the alu result=op_a
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input logic data_misaligned_i,
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output logic prepost_useincr_o, // When not active bypass the alu result=op_a
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input logic data_misaligned_i,
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// CSR manipulation
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output logic csr_access_o,
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output logic [1:0] csr_op_o,
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output logic csr_access_o,
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output logic [1:0] csr_op_o,
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// LD/ST unit signals
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output logic data_we_o, // Write enable to data memory
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output logic [1:0] data_type_o, // Data type on data memory: byte, half word or word
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output logic data_sign_extension_o, // Sign extension on read data from data memory
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output logic [1:0] data_reg_offset_o, // Offset in bytes inside register for stores
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output logic data_req_o, // Request for a transaction to data memory
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input logic data_ack_i, // Data memory request-acknowledge
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input logic data_req_ex_i, // Delayed copy of the data_req_o
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input logic data_rvalid_i, // rvalid from data memory
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output logic data_we_o, // Write enable to data memory
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output logic [1:0] data_type_o, // Data type on data memory: byte, half word or word
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output logic data_sign_extension_o, // Sign extension on read data from data memory
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output logic [1:0] data_reg_offset_o, // Offset in bytes inside register for stores
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output logic data_req_o, // Request for a transaction to data memory
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input logic data_ack_i, // Data memory request-acknowledge
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input logic data_req_ex_i, // Delayed copy of the data_req_o
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input logic data_rvalid_i, // rvalid from data memory
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// hwloop signals
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output logic [2:0] hwloop_we_o, // write enables for hwloop regs
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output logic hwloop_wb_mux_sel_o, // select data to write to hwloop regs
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output logic [1:0] hwloop_cnt_mux_sel_o, // selects hwloop counter input
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input logic hwloop_jump_i, // modify pc_mux_sel to select the hwloop addr
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output logic [2:0] hwloop_we_o, // write enables for hwloop regs
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output logic hwloop_wb_mux_sel_o, // select data to write to hwloop regs
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output logic [1:0] hwloop_cnt_mux_sel_o, // selects hwloop counter input
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input logic hwloop_jump_i, // modify pc_mux_sel to select the hwloop addr
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// Interrupt signals
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input logic irq_present_i, // there is an IRQ, so if we are sleeping we should wake up now
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input logic irq_present_i, // there is an IRQ, so if we are sleeping we should wake up now
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// Exception Controller Signals
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input logic illegal_c_insn_i, // compressed instruction decode failed
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output logic illegal_insn_o, // illegal instruction encountered
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output logic trap_insn_o, // trap instruction encountered
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input logic pc_valid_i, // is the next_pc currently valid?
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output logic clear_isr_running_o, // an l.rfe instruction was encountered, exit ISR
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input logic exc_pipe_flush_i, // flush pipeline after exception handling
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input logic trap_hit_i, // a trap was hit, so we have to flush EX and WB
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input logic illegal_c_insn_i, // compressed instruction decode failed
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output logic illegal_insn_o, // illegal instruction encountered
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output logic trap_insn_o, // trap instruction encountered
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input logic pc_valid_i, // is the next_pc currently valid?
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output logic clear_isr_running_o, // an l.rfe instruction was encountered, exit ISR
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input logic exc_pipe_flush_i, // flush pipeline after exception handling
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input logic trap_hit_i, // a trap was hit, so we have to flush EX and WB
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// Debug Unit Signals
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input logic dbg_stall_i, // Pipeline stall is requested
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input logic dbg_set_npc_i, // Change PC to value from debug unit
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output logic dbg_trap_o, // trap hit, inform debug unit
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input logic dbg_stall_i, // Pipeline stall is requested
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input logic dbg_set_npc_i, // Change PC to value from debug unit
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output logic dbg_trap_o, // trap hit, inform debug unit
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// Forwarding signals from regfile
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input logic [4:0] regfile_waddr_ex_i, // FW: write address from EX stage
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input logic regfile_we_ex_i, // FW: write enable from EX stage
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input logic [4:0] regfile_waddr_wb_i, // FW: write address from WB stage
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input logic regfile_we_wb_i, // FW: write enable from WB stage
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input logic [4:0] regfile_alu_waddr_fw_i, // FW: ALU/MUL write address from EX stage
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input logic regfile_alu_we_fw_i, // FW: ALU/MUL write enable from EX stage
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output logic [1:0] operand_a_fw_mux_sel_o, // regfile ra data selector form ID stage
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output logic [1:0] operand_b_fw_mux_sel_o, // regfile rb data selector form ID stage
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output logic [1:0] operand_c_fw_mux_sel_o, // regfile rc data selector form ID stage
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input logic [4:0] regfile_waddr_ex_i, // FW: write address from EX stage
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input logic regfile_we_ex_i, // FW: write enable from EX stage
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input logic [4:0] regfile_waddr_wb_i, // FW: write address from WB stage
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input logic regfile_we_wb_i, // FW: write enable from WB stage
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input logic [4:0] regfile_alu_waddr_fw_i, // FW: ALU/MUL write address from EX stage
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input logic regfile_alu_we_fw_i, // FW: ALU/MUL write enable from EX stage
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output logic [1:0] operand_a_fw_mux_sel_o, // regfile ra data selector form ID stage
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output logic [1:0] operand_b_fw_mux_sel_o, // regfile rb data selector form ID stage
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output logic [1:0] operand_c_fw_mux_sel_o, // regfile rc data selector form ID stage
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// Jump target calcuation done decision
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input logic [1:0] jump_in_ex_i, // jump is being calculated in ALU
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output logic [1:0] jump_in_id_o, // jump is being calculated in ALU
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input logic branch_decision_i,
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input logic [1:0] jump_in_ex_i, // jump is being calculated in ALU
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output logic [1:0] jump_in_id_o, // jump is being calculated in ALU
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input logic branch_decision_i,
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output logic stall_if_o, // Stall IF stage (deassert requests)
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output logic stall_id_o, // Stall ID stage (and instr and data memory interface) ( ID_STAGE )
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output logic stall_ex_o, // Stall ex stage ( EX_STAGE )
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output logic stall_wb_o, // Stall write to register file due contentions ( WB_STAGE )
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output logic stall_if_o, // Stall IF stage (deassert requests)
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output logic stall_id_o, // Stall ID stage (and instr and data memory interface) ( ID_STAGE )
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output logic stall_ex_o, // Stall ex stage ( EX_STAGE )
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output logic stall_wb_o, // Stall write to register file due contentions ( WB_STAGE )
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// Performance Counters
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output logic perf_jump_o, // we are executing a jump instruction (j, jr, jal, jalr)
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output logic perf_branch_o, // we are executing a branch instruction (bf, bnf)
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output logic perf_jr_stall_o, // stall due to jump-register-hazard
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output logic perf_ld_stall_o // stall due to load-use-hazard
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// Performance Counters
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output logic perf_jump_o, // we are executing a jump instruction (j, jr, jal, jalr)
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output logic perf_branch_o, // we are executing a branch instruction (bf, bnf)
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output logic perf_jr_stall_o, // stall due to jump-register-hazard
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output logic perf_ld_stall_o // stall due to load-use-hazard
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);
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// FSM state encoding
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