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Feature/remove branch target alu (#51)

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* remove BranchTargetALU param.

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from the documentation

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from the example configurations

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from examples

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from compliance verification

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* remove references to the removed parameters from core lists

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

* Remove references to the removed parameter(s) from Yosys framework configuration parser

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>

---------

Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
This commit is contained in:
christian-herber-nxp 2023-02-13 18:59:56 +01:00 • committed by GitHub
parent 7a678a54c4
commit e7559f327d
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
18 changed files with 23 additions and 214 deletions
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8
cve2_configs.yaml
View file

@ -12,7 +12,6 @@ small:
RV32M : "cve2_pkg::RV32MFast"
RV32B : "cve2_pkg::RV32BNone"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 0
WritebackStage : 0
ICache : 0
ICacheECC : 0
@ -29,7 +28,6 @@ opentitan:
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BOTEarlGrey"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 1
ICacheECC : 1
@ -52,7 +50,6 @@ experimental-maxperf:
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BNone"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
ICacheECC : 0
@ -69,7 +66,6 @@ experimental-maxperf-pmp:
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BNone"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
ICacheECC : 0
@ -86,7 +82,6 @@ experimental-maxperf-pmp-bmbalanced:
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BBalanced"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
ICacheECC : 0
@ -103,7 +98,6 @@ experimental-maxperf-pmp-bmfull:
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BFull"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
ICacheECC : 0
@ -120,7 +114,6 @@ experimental-maxperf-pmp-bmfull-icache:
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BFull"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 1
ICacheECC : 1
@ -140,7 +133,6 @@ experimental-branch-predictor:
RV32M : "cve2_pkg::RV32MSingleCycle"
RV32B : "cve2_pkg::RV32BNone"
RegFile : "cve2_pkg::RegFileFF"
BranchTargetALU : 1
WritebackStage : 1
ICache : 0
ICacheECC : 0

6
cve2_core.core
View file

@ -100,12 +100,6 @@ parameters:
paramtype: vlogparam
description: "Enable ECC protection in instruction cache"
BranchTargetALU:
datatype: int
default: 0
paramtype: vlogparam
description: "Enables separate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
WritebackStage:
datatype: int
default: 0

6
cve2_top.core
View file

@ -84,12 +84,6 @@ parameters:
paramtype: vlogparam
description: "Enable ECC protection in instruction cache"
BranchTargetALU:
datatype: int
default: 0
paramtype: vlogparam
description: "Enables separate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
WritebackStage:
datatype: int
default: 0

7
cve2_top_tracing.core
View file

@ -59,12 +59,6 @@ parameters:
paramtype: vlogparam
description: "Enable ECC protection in instruction cache"
BranchTargetALU:
datatype: int
default: 0
paramtype: vlogparam
description: "Enables separate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"
WritebackStage:
datatype: int
default: 0
@ -126,7 +120,6 @@ targets:
- RegFile
- ICache
- ICacheECC
- BranchTargetALU
- WritebackStage
- BranchPredictor
- SecureCVE2

3
doc/02_user/integration.rst
View file

@ -112,9 +112,6 @@ Parameters
| | | | "cve2_pkg::RegFileFPGA": Register file for FPGA targets |
| | | | "cve2_pkg::RegFileLatch": Latch-based register file for ASIC targets |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``BranchTargetALU`` | bit | 0 | *EXPERIMENTAL* - Enables branch target ALU removing a stall |
| | | | cycle from taken branches |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``WritebackStage`` | bit | 0 | *EXPERIMENTAL* - Enables third pipeline stage (writeback) |
| | | | improving performance of loads and stores |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+

10
doc/03_reference/pipeline_details.rst
View file

@ -76,17 +76,13 @@ Read the description for more information.
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Branch (Taken) | 2 - N | Any branch where the condition is met will stall for 2 |
| | | cycles as in the first cycle the branch is in ID/EX the ALU |
| | 1 - N (Branch Target | is used to calculate the branch condition. The following |
| | ALU enabled) | cycle the ALU is used again to calculate the branch target |
| | | is used to calculate the branch condition. The following |
| | | cycle the ALU is used again to calculate the branch target |
| | | where it proceeds as Jump does above (Flush IF stage and |
| | | prefetch buffer, new PC on instruction-side memory |
| | | interface the same cycle it is calculated). The longer the |
| | | instruction-side memory interface takes to receive data the |
| | | longer the branch will stall. With the parameter |
| | | ``BranchTargetALU`` set to ``1`` a separate ALU calculates |
| | | the branch target simultaneously to calculating the branch |
| | | condition with the main ALU so 1 less stall cycle is |
| | | required. |
| | | longer the branch will stall. |
+-----------------------+--------------------------------------+-------------------------------------------------------------+
| Instruction Fence | 1 - N | The FENCE.I instruction as defined in 'Zifencei' of the |
| | | RISC-V specification. Internally it is implemented as a |

7
dv/riscv_compliance/cve2_riscv_compliance.core
View file

@ -59,12 +59,6 @@ parameters:
paramtype: vlogparam
description: "Enable ECC protection in instruction cache"
BranchTargetALU:
datatype: int
paramtype: vlogparam
default: 0
description: "Enables separate branch target ALU (increasing branch performance EXPERIMENTAL)"
WritebackStage:
datatype: int
paramtype: vlogparam
@ -120,7 +114,6 @@ targets:
- RegFile
- ICache
- ICacheECC
- BranchTargetALU
- WritebackStage
- BranchPredictor
- PMPEnable

2
dv/riscv_compliance/rtl/cve2_riscv_compliance.sv
View file

@ -22,7 +22,6 @@ module cve2_riscv_compliance (
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast;
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone;
parameter cve2_pkg::regfile_e RegFile = cve2_pkg::RegFileFF;
parameter bit BranchTargetALU = 1'b0;
parameter bit WritebackStage = 1'b0;
parameter bit ICache = 1'b0;
parameter bit ICacheECC = 1'b0;
@ -121,7 +120,6 @@ module cve2_riscv_compliance (
.RV32M (RV32M ),
.RV32B (RV32B ),
.RegFile (RegFile ),
.BranchTargetALU (BranchTargetALU ),
.WritebackStage (WritebackStage ),
.ICache (ICache ),
.ICacheECC (ICacheECC ),

7
examples/simple_system/cve2_simple_system.core
View file

@ -54,12 +54,6 @@ parameters:
paramtype: vlogparam
description: "Path to a vmem file to initialize the RAM with"
BranchTargetALU:
datatype: int
paramtype: vlogparam
default: 0
description: "Enables separate branch target ALU (increasing branch performance EXPERIMENTAL)"
WritebackStage:
datatype: int
paramtype: vlogparam
@ -115,7 +109,6 @@ targets:
- ICache
- ICacheScramble
- ICacheECC
- BranchTargetALU
- WritebackStage
- SecureIbex
- BranchPredictor

2
examples/simple_system/rtl/cve2_simple_system.sv
View file

@ -44,7 +44,6 @@ module cve2_simple_system (
parameter cve2_pkg::rv32m_e RV32M = `RV32M;
parameter cve2_pkg::rv32b_e RV32B = `RV32B;
parameter cve2_pkg::regfile_e RegFile = `RegFile;
parameter bit BranchTargetALU = 1'b0;
parameter bit WritebackStage = 1'b0;
parameter bit ICache = 1'b0;
parameter bit ICacheECC = 1'b0;
@ -173,7 +172,6 @@ module cve2_simple_system (
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.RegFile ( RegFile ),
.BranchTargetALU ( BranchTargetALU ),
.ICache ( ICache ),
.ICacheECC ( ICacheECC ),
.WritebackStage ( WritebackStage ),

15
rtl/cve2_core.sv
View file

@ -21,7 +21,6 @@ module cve2_core import cve2_pkg::*; #(
parameter bit RV32E = 1'b0,
parameter rv32m_e RV32M = RV32MFast,
parameter rv32b_e RV32B = RV32BNone,
parameter bit BranchTargetALU = 1'b0,
parameter bit WritebackStage = 1'b0,
parameter bit ICache = 1'b0,
parameter bit ICacheECC = 1'b0,
@ -237,9 +236,6 @@ module cve2_core import cve2_pkg::*; #(
logic [31:0] alu_operand_a_ex;
logic [31:0] alu_operand_b_ex;
logic [31:0] bt_a_operand;
logic [31:0] bt_b_operand;
logic [31:0] alu_adder_result_ex; // Used to forward computed address to LSU
logic [31:0] result_ex;
@ -484,7 +480,6 @@ module cve2_core import cve2_pkg::*; #(
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU(BranchTargetALU),
.DataIndTiming (DataIndTiming),
.WritebackStage (WritebackStage),
.BranchPredictor(BranchPredictor)
@ -538,9 +533,6 @@ module cve2_core import cve2_pkg::*; #(
.imd_val_d_ex_i (imd_val_d_ex),
.imd_val_we_ex_i(imd_val_we_ex),
.bt_a_operand_o(bt_a_operand),
.bt_b_operand_o(bt_b_operand),
.mult_en_ex_o (mult_en_ex),
.div_en_ex_o (div_en_ex),
.mult_sel_ex_o (mult_sel_ex),
@ -641,8 +633,7 @@ module cve2_core import cve2_pkg::*; #(
cve2_ex_block #(
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU(BranchTargetALU)
.RV32B (RV32B)
) ex_block_i (
.clk_i (clk_i),
.rst_ni(rst_ni),
@ -653,10 +644,6 @@ module cve2_core import cve2_pkg::*; #(
.alu_operand_b_i (alu_operand_b_ex),
.alu_instr_first_cycle_i(instr_first_cycle_id),
// Branch target ALU signal from ID stage
.bt_a_operand_i(bt_a_operand),
.bt_b_operand_i(bt_b_operand),
// Multipler/Divider signal from ID stage
.multdiv_operator_i (multdiv_operator_ex),
.mult_en_i (mult_en_ex),

44
rtl/cve2_decoder.sv
View file

@ -16,8 +16,7 @@
module cve2_decoder #(
parameter bit RV32E = 0,
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone,
parameter bit BranchTargetALU = 0
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone
) (
input logic clk_i,
input logic rst_ni,
@ -45,8 +44,6 @@ module cve2_decoder #(
// immediates
output cve2_pkg::imm_a_sel_e imm_a_mux_sel_o, // immediate selection for operand a
output cve2_pkg::imm_b_sel_e imm_b_mux_sel_o, // immediate selection for operand b
output cve2_pkg::op_a_sel_e bt_a_mux_sel_o, // branch target selection operand a
output cve2_pkg::imm_b_sel_e bt_b_mux_sel_o, // branch target selection operand b
output logic [31:0] imm_i_type_o,
output logic [31:0] imm_s_type_o,
output logic [31:0] imm_b_type_o,
@ -244,8 +241,8 @@ module cve2_decoder #(
jump_in_dec_o = 1'b1;
if (instr_first_cycle_i) begin
// Calculate jump target (and store PC + 4 if BranchTargetALU is configured)
rf_we = BranchTargetALU;
// Calculate jump target (and store PC)
rf_we = 1'b0;
jump_set_o = 1'b1;
end else begin
// Calculate and store PC+4
@ -257,8 +254,8 @@ module cve2_decoder #(
jump_in_dec_o = 1'b1;
if (instr_first_cycle_i) begin
// Calculate jump target (and store PC + 4 if BranchTargetALU is configured)
rf_we = BranchTargetALU;
// Calculate jump target (and store PC)
rf_we = 1'b0;
jump_set_o = 1'b1;
end else begin
// Calculate and store PC+4
@ -676,10 +673,6 @@ module cve2_decoder #(
imm_a_mux_sel_o = IMM_A_ZERO;
imm_b_mux_sel_o = IMM_B_I;
bt_a_mux_sel_o = OP_A_CURRPC;
bt_b_mux_sel_o = IMM_B_I;
opcode_alu = opcode_e'(instr_alu[6:0]);
use_rs3_d = 1'b0;
@ -694,13 +687,8 @@ module cve2_decoder #(
///////////
OPCODE_JAL: begin // Jump and Link
if (BranchTargetALU) begin
bt_a_mux_sel_o = OP_A_CURRPC;
bt_b_mux_sel_o = IMM_B_J;
end
// Jumps take two cycles without the BTALU
if (instr_first_cycle_i && !BranchTargetALU) begin
if (instr_first_cycle_i) begin
// Calculate jump target
alu_op_a_mux_sel_o = OP_A_CURRPC;
alu_op_b_mux_sel_o = OP_B_IMM;
@ -716,13 +704,8 @@ module cve2_decoder #(
end
OPCODE_JALR: begin // Jump and Link Register
if (BranchTargetALU) begin
bt_a_mux_sel_o = OP_A_REG_A;
bt_b_mux_sel_o = IMM_B_I;
end
// Jumps take two cycles without the BTALU
if (instr_first_cycle_i && !BranchTargetALU) begin
if (instr_first_cycle_i) begin
// Calculate jump target
alu_op_a_mux_sel_o = OP_A_REG_A;
alu_op_b_mux_sel_o = OP_B_IMM;
@ -749,19 +732,13 @@ module cve2_decoder #(
default: ;
endcase
if (BranchTargetALU) begin
bt_a_mux_sel_o = OP_A_CURRPC;
// Not-taken branch will jump to next instruction (used in secure mode)
bt_b_mux_sel_o = branch_taken_i ? IMM_B_B : IMM_B_INCR_PC;
end
// Without branch target ALU, a branch is a two-stage operation using the Main ALU in both
// stages
if (instr_first_cycle_i) begin
// First evaluate the branch condition
alu_op_a_mux_sel_o = OP_A_REG_A;
alu_op_b_mux_sel_o = OP_B_REG_B;
end else if (!BranchTargetALU) begin
end else begin
// Then calculate jump target
alu_op_a_mux_sel_o = OP_A_CURRPC;
alu_op_b_mux_sel_o = OP_B_IMM;
@ -1147,15 +1124,10 @@ module cve2_decoder #(
end
3'b001: begin
// FENCE.I will flush the IF stage, prefetch buffer and ICache if present.
if (BranchTargetALU) begin
bt_a_mux_sel_o = OP_A_CURRPC;
bt_b_mux_sel_o = IMM_B_INCR_PC;
end else begin
alu_op_a_mux_sel_o = OP_A_CURRPC;
alu_op_b_mux_sel_o = OP_B_IMM;
imm_b_mux_sel_o = IMM_B_INCR_PC;
alu_operator_o = ALU_ADD;
end
end
default: ;
endcase

23
rtl/cve2_ex_block.sv
View file

@ -10,8 +10,7 @@
*/
module cve2_ex_block #(
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone,
parameter bit BranchTargetALU = 0
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone
) (
input logic clk_i,
input logic rst_ni,
@ -22,11 +21,6 @@ module cve2_ex_block #(
input logic [31:0] alu_operand_b_i,
input logic alu_instr_first_cycle_i,
// Branch Target ALU
// All of these signals are unusued when BranchTargetALU == 0
input logic [31:0] bt_a_operand_i,
input logic [31:0] bt_b_operand_i,
// Multiplier/Divider
input cve2_pkg::md_op_e multdiv_operator_i,
input logic mult_en_i, // dynamic enable signal, for FSM control
@ -91,20 +85,9 @@ module cve2_ex_block #(
// branch handling
assign branch_decision_o = alu_cmp_result;
if (BranchTargetALU) begin : g_branch_target_alu
logic [32:0] bt_alu_result;
logic unused_bt_carry;
assign bt_alu_result = bt_a_operand_i + bt_b_operand_i;
assign unused_bt_carry = bt_alu_result[32];
assign branch_target_o = bt_alu_result[31:0];
end else begin : g_no_branch_target_alu
begin : g_no_branch_target_alu
// Unused bt_operand signals cause lint errors, this avoids them
logic [31:0] unused_bt_a_operand, unused_bt_b_operand;
assign unused_bt_a_operand = bt_a_operand_i;
assign unused_bt_b_operand = bt_b_operand_i;
//logic [31:0] unused_bt_a_operand, unused_bt_b_operand;
assign branch_target_o = alu_adder_result_ex_o;
end

86
rtl/cve2_id_stage.sv
View file

@ -22,7 +22,6 @@ module cve2_id_stage #(
parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,
parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone,
parameter bit DataIndTiming = 1'b0,
parameter bit BranchTargetALU = 0,
parameter bit WritebackStage = 0,
parameter bit BranchPredictor = 0
) (
@ -75,10 +74,6 @@ module cve2_id_stage #(
input logic [33:0] imd_val_d_ex_i[2],
output logic [33:0] imd_val_q_ex_o[2],
// Branch target ALU
output logic [31:0] bt_a_operand_o,
output logic [31:0] bt_b_operand_o,
// MUL, DIV
output logic mult_en_ex_o,
output logic div_en_ex_o,
@ -257,9 +252,6 @@ module cve2_id_stage #(
logic [33:0] imd_val_q[2];
op_a_sel_e bt_a_mux_sel;
imm_b_sel_e bt_b_mux_sel;
imm_a_sel_e imm_a_mux_sel;
imm_b_sel_e imm_b_mux_sel, imm_b_mux_sel_dec;
@ -310,53 +302,10 @@ module cve2_id_stage #(
endcase
end
if (BranchTargetALU) begin : g_btalu_muxes
// Branch target ALU operand A mux
always_comb begin : bt_operand_a_mux
unique case (bt_a_mux_sel)
OP_A_REG_A: bt_a_operand_o = rf_rdata_a_fwd;
OP_A_CURRPC: bt_a_operand_o = pc_id_i;
default: bt_a_operand_o = pc_id_i;
endcase
end
// Branch target ALU operand B mux
always_comb begin : bt_immediate_b_mux
unique case (bt_b_mux_sel)
IMM_B_I: bt_b_operand_o = imm_i_type;
IMM_B_B: bt_b_operand_o = imm_b_type;
IMM_B_J: bt_b_operand_o = imm_j_type;
IMM_B_INCR_PC: bt_b_operand_o = instr_is_compressed_i ? 32'h2 : 32'h4;
default: bt_b_operand_o = instr_is_compressed_i ? 32'h2 : 32'h4;
endcase
end
// Reduced main ALU immediate MUX for Operand B
always_comb begin : immediate_b_mux
unique case (imm_b_mux_sel)
IMM_B_I: imm_b = imm_i_type;
IMM_B_S: imm_b = imm_s_type;
IMM_B_U: imm_b = imm_u_type;
IMM_B_INCR_PC: imm_b = instr_is_compressed_i ? 32'h2 : 32'h4;
IMM_B_INCR_ADDR: imm_b = 32'h4;
default: imm_b = 32'h4;
endcase
end
`ASSERT(IbexImmBMuxSelValid, instr_valid_i |-> imm_b_mux_sel inside {
IMM_B_I,
IMM_B_S,
IMM_B_U,
IMM_B_INCR_PC,
IMM_B_INCR_ADDR})
end else begin : g_nobtalu
begin : g_nobtalu
op_a_sel_e unused_a_mux_sel;
imm_b_sel_e unused_b_mux_sel;
assign unused_a_mux_sel = bt_a_mux_sel;
assign unused_b_mux_sel = bt_b_mux_sel;
assign bt_a_operand_o = '0;
assign bt_b_operand_o = '0;
// Full main ALU immediate MUX for Operand B
always_comb begin : immediate_b_mux
unique case (imm_b_mux_sel)
@ -422,8 +371,7 @@ module cve2_id_stage #(
cve2_decoder #(
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU(BranchTargetALU)
.RV32B (RV32B)
) decoder_i (
.clk_i (clk_i),
.rst_ni(rst_ni),
@ -448,8 +396,6 @@ module cve2_id_stage #(
// immediates
.imm_a_mux_sel_o(imm_a_mux_sel),
.imm_b_mux_sel_o(imm_b_mux_sel_dec),
.bt_a_mux_sel_o (bt_a_mux_sel),
.bt_b_mux_sel_o (bt_b_mux_sel),
.imm_i_type_o (imm_i_type),
.imm_s_type_o (imm_s_type),
@ -653,11 +599,7 @@ module cve2_id_stage #(
// Branch set control //
////////////////////////
if (BranchTargetALU && !DataIndTiming) begin : g_branch_set_direct
// Branch set fed straight to controller with branch target ALU
// (condition pass/fail used same cycle as generated instruction request)
assign branch_set_raw = branch_set_raw_d;
end else begin : g_branch_set_flop
begin : g_branch_set_flop
// SEC_CM: CORE.DATA_REG_SW.SCA
// Branch set flopped without branch target ALU, or in fixed time execution mode
// (condition pass/fail used next cycle where branch target is calculated)
@ -674,8 +616,7 @@ module cve2_id_stage #(
// Branches always take two cycles in fixed time execution mode, with or without the branch
// target ALU (to avoid a path from the branch decision into the branch target ALU operand
// muxing).
assign branch_set_raw = (BranchTargetALU && !data_ind_timing_i) ? branch_set_raw_d :
branch_set_raw_q;
assign branch_set_raw = branch_set_raw_q;
end
@ -802,9 +743,9 @@ module cve2_id_stage #(
// All branches take two cycles in fixed time execution mode, regardless of branch
// condition.
// SEC_CM: CORE.DATA_REG_SW.SCA
id_fsm_d = (data_ind_timing_i || (!BranchTargetALU && branch_decision_i)) ?
id_fsm_d = (data_ind_timing_i || branch_decision_i) ?
MULTI_CYCLE : FIRST_CYCLE;
stall_branch = (~BranchTargetALU & branch_decision_i) | data_ind_timing_i;
stall_branch = (branch_decision_i | data_ind_timing_i);
branch_set_raw_d = (branch_decision_i | data_ind_timing_i);
if (BranchPredictor) begin
@ -815,9 +756,8 @@ module cve2_id_stage #(
end
jump_in_dec: begin
// uncond branch operation
// BTALU means jumps only need one cycle
id_fsm_d = BranchTargetALU ? FIRST_CYCLE : MULTI_CYCLE;
stall_jump = ~BranchTargetALU;
id_fsm_d = MULTI_CYCLE;
stall_jump = 1'b1;
jump_set_raw = jump_set_dec;
end
alu_multicycle_dec: begin
@ -1080,16 +1020,6 @@ module cve2_id_stage #(
OP_A_FWD,
OP_A_CURRPC,
OP_A_IMM})
`ASSERT_KNOWN_IF(IbexBTAluAOpMuxSelKnown, bt_a_mux_sel, instr_valid_i)
`ASSERT(IbexBTAluAOpMuxSelValid, instr_valid_i |-> bt_a_mux_sel inside {
OP_A_REG_A,
OP_A_CURRPC})
`ASSERT_KNOWN_IF(IbexBTAluBOpMuxSelKnown, bt_b_mux_sel, instr_valid_i)
`ASSERT(IbexBTAluBOpMuxSelValid, instr_valid_i |-> bt_b_mux_sel inside {
IMM_B_I,
IMM_B_B,
IMM_B_J,
IMM_B_INCR_PC})
`ASSERT(IbexRegfileWdataSelValid, instr_valid_i |-> rf_wdata_sel inside {
RF_WD_EX,
RF_WD_CSR})

2
rtl/cve2_lockstep.sv
View file

@ -18,7 +18,6 @@ module cve2_lockstep import cve2_pkg::*; #(
parameter bit RV32E = 1'b0,
parameter rv32m_e RV32M = RV32MFast,
parameter rv32b_e RV32B = RV32BNone,
parameter bit BranchTargetALU = 1'b0,
parameter bit WritebackStage = 1'b0,
parameter bit ICache = 1'b0,
parameter bit ICacheECC = 1'b0,
@ -359,7 +358,6 @@ module cve2_lockstep import cve2_pkg::*; #(
.RV32E ( RV32E ),
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.BranchTargetALU ( BranchTargetALU ),
.ICache ( ICache ),
.ICacheECC ( ICacheECC ),
.BusSizeECC ( BusSizeECC ),

3
rtl/cve2_top.sv
View file

@ -19,7 +19,6 @@ module cve2_top import cve2_pkg::*; #(
parameter rv32m_e RV32M = RV32MFast,
parameter rv32b_e RV32B = RV32BNone,
parameter regfile_e RegFile = RegFileFF,
parameter bit BranchTargetALU = 1'b0,
parameter bit WritebackStage = 1'b0,
parameter bit ICache = 1'b0,
parameter bit ICacheECC = 1'b0,
@ -238,7 +237,6 @@ module cve2_top import cve2_pkg::*; #(
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU (BranchTargetALU),
.ICache (ICache),
.ICacheECC (ICacheECC),
.BusSizeECC (BusSizeECC),
@ -817,7 +815,6 @@ module cve2_top import cve2_pkg::*; #(
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU (BranchTargetALU),
.ICache (ICache),
.ICacheECC (ICacheECC),
.BusSizeECC (BusSizeECC),

2
rtl/cve2_top_tracing.sv
View file

@ -13,7 +13,6 @@ module cve2_top_tracing import cve2_pkg::*; #(
parameter rv32m_e RV32M = RV32MFast,
parameter rv32b_e RV32B = RV32BNone,
parameter regfile_e RegFile = RegFileFF,
parameter bit BranchTargetALU = 1'b0,
parameter bit WritebackStage = 1'b0,
parameter bit ICache = 1'b0,
parameter bit ICacheECC = 1'b0,
@ -140,7 +139,6 @@ module cve2_top_tracing import cve2_pkg::*; #(
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.RegFile ( RegFile ),
.BranchTargetALU ( BranchTargetALU ),
.ICache ( ICache ),
.ICacheECC ( ICacheECC ),
.BranchPredictor ( BranchPredictor ),

4
syn/tcl/yosys_run_synth.tcl
View file

@ -16,10 +16,6 @@ if { $lr_synth_timing_run } {
yosys "read_verilog -defer -sv ./rtl/prim_clock_gating.v $lr_synth_out_dir/generated/*.v"
if { $lr_synth_cve2_branch_target_alu } {
yosys "chparam -set BranchTargetALU 1 $lr_synth_top_module"
}
if { $lr_synth_cve2_writeback_stage } {
yosys "chparam -set WritebackStage 1 $lr_synth_top_module"
}