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Add RV32E to simchecker and tracer
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parent
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commit
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2 changed files with 15 additions and 7 deletions
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@ -36,6 +36,14 @@ import "DPI-C" function void riscv_checker_reg_access(input chandle cpu, inpu
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`endif
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module riscv_simchecker
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#(
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// CONFIG_REGION: RV32E
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`ifdef RV32E
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parameter REG_ADDR_WIDTH = 4
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`else
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parameter REG_ADDR_WIDTH = 5
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`endif // RV32E
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)
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(
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// Clock and Reset
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input logic clk,
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@ -61,7 +69,7 @@ module riscv_simchecker
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input logic pipe_flush,
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input logic ex_valid,
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input logic [ 4:0] ex_reg_addr,
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input logic [(REG_ADDR_WIDTH-1):0] ex_reg_addr,
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input logic ex_reg_we,
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input logic [31:0] ex_reg_wdata,
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@ -75,7 +83,7 @@ module riscv_simchecker
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input logic wb_bypass,
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input logic wb_valid,
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input logic [ 4:0] wb_reg_addr,
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input logic [(REG_ADDR_WIDTH-1):0] wb_reg_addr,
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input logic wb_reg_we,
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input logic [31:0] wb_reg_wdata,
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@ -89,7 +97,7 @@ module riscv_simchecker
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// SV-only stuff
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typedef struct {
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logic [ 4:0] addr;
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logic [(REG_ADDR_WIDTH-1):0] addr;
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logic [31:0] value;
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} reg_t;
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@ -74,7 +74,7 @@ module riscv_tracer
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input logic [31:0] rs2_value_vec,
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input logic ex_valid,
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input logic [ 4:0] ex_reg_addr,
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input logic [(REG_ADDR_WIDTH-1):0] ex_reg_addr,
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input logic ex_reg_we,
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input logic [31:0] ex_reg_wdata,
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@ -87,7 +87,7 @@ module riscv_tracer
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input logic wb_bypass,
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input logic wb_valid,
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input logic [ 4:0] wb_reg_addr,
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input logic [(REG_ADDR_WIDTH-1):0] wb_reg_addr,
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input logic wb_reg_we,
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input logic [31:0] wb_reg_wdata,
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@ -111,7 +111,7 @@ module riscv_tracer
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logic [ 4:0] rd, rs1, rs2, rs3;
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typedef struct {
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logic [ 4:0] addr;
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logic [(REG_ADDR_WIDTH-1):0] addr;
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logic [31:0] value;
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} reg_t;
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@ -140,7 +140,7 @@ module riscv_tracer
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mem_access = {};
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endfunction
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function string regAddrToStr(input logic [4:0] addr);
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function string regAddrToStr(input logic [(REG_ADDR_WIDTH-1):0] addr);
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begin
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if (addr < 10)
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return $sformatf(" x%0d", addr);
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