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Fixing reference for FPGA reset

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Christian Herber 2023-08-15 14:53:14 +02:00
parent 2b47c3007b
commit f2fb7c4ad7
1 changed files with 2 additions and 2 deletions
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doc/00_specification/index.rst
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@ -794,7 +794,7 @@ the integration in FPGA and ASIC design flows:
| PDR-20 | For certain FPGA targets, CV32E20 may remove the reset in |
| | the RTL code. |
| | |
| | See [FPGAreset] for background information on this |
| | See [FPGAreset]_ for background information on this |
| | requirement. |
+---------+------------------------------------------------------------+