github-mirrors/cve2
1
0
Fork 0
mirror of https://github.com/openhwgroup/cve2.git synced 2025-06-28 09:39:26 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fixing reference for FPGA reset

Browse source
This commit is contained in:
Christian Herber 2023-08-15 14:53:14 +02:00
parent 2b47c3007b
commit f2fb7c4ad7
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
doc/00_specification/index.rst
View file

@ -199,7 +199,7 @@ Other documents
===============
.. [FPGAreset] Ken Chapman, “Get Smart About Reset: Think Local, Not
Global”, Xilinx WP272 white paper, https://docs.xilinx.com/v/u/en-US/wp272
Global”, Xilinx WP272 white paper, https://docs.xilinx.com/v/u/en-US/wp272
CV32E20 core functional requirements
====================================
@ -794,7 +794,7 @@ the integration in FPGA and ASIC design flows:
| PDR-20 | For certain FPGA targets, CV32E20 may remove the reset in |
| | the RTL code. |
| | |
| | See [FPGAreset] for background information on this |
| | See [FPGAreset]_ for background information on this |
| | requirement. |
+---------+------------------------------------------------------------+