Add performance counter for compressed instructions

controller.sv

@@ -38,6 +38,7 @@ module controller
 
   input  logic        fetch_enable_i,             // Start the decoding
   output logic        core_busy_o,                // Core is busy processing instructions
+  output logic        is_decoding_o,
 
   input  logic [31:0] instr_rdata_i,              // Instruction read from instr memory/cache: (sampled in the if stage)
   output logic        instr_req_o,                // Fetch instruction Request:
@@ -803,7 +804,7 @@ module controller
             begin
               illegal_insn_int = 1'b1;
             end
-          endcase // unique case (instr_rdata_i)
+          endcase
         end
         else
         begin
@@ -956,13 +957,14 @@ module controller
   always_comb
   begin
     // Default values
-    instr_req_o   = 1'b1;
+    instr_req_o    = 1'b1;
 
-    pc_mux_sel_o  = `PC_INCR;
+    pc_mux_sel_o   = `PC_INCR;
 
-    ctrl_fsm_ns   = ctrl_fsm_cs;
+    ctrl_fsm_ns    = ctrl_fsm_cs;
 
-    core_busy_o   = 1'b1;
+    core_busy_o    = 1'b1;
+    is_decoding_o  = 1'b0;
 
     halt_if        = 1'b0;
     halt_id        = 1'b0;
@@ -1019,6 +1021,8 @@ module controller
 
       DECODE:
       begin
+        is_decoding_o = 1'b1;
+
         // handle conditional branches
         if (jump_in_id == `BRANCH_COND) begin
           // handle branch if decision is availble in next cycle

cs_registers.sv

@@ -55,6 +55,8 @@ module cs_registers
 
   // Performance Counters
   input  logic        stall_id_i,        // stall ID stage
+  input  logic        is_compressed_i,   // compressed instruction in ID
+  input  logic        is_decoding_i,     // controller is in DECODE state
 
   input  logic        instr_fetch_i,     // instruction fetch
 
@@ -69,7 +71,7 @@ module cs_registers
   input  logic [N_EXT_PERF_COUNTERS-1:0]   ext_counters_i
 );
 
-  localparam N_PERF_COUNTERS = 9 + N_EXT_PERF_COUNTERS;
+  localparam N_PERF_COUNTERS = 10 + N_EXT_PERF_COUNTERS;
 
 `ifdef PULP_FPGA_EMUL
   localparam N_PERF_REGS     = N_PERF_COUNTERS;
@@ -139,7 +141,7 @@ module cs_registers
     irq_enable_n = irq_enable;
 
     case (csr_addr_i)
-      // mstatus: always M-mode, contains IE bit
+      // mstatus: IE bit
       12'h300: if (csr_we_int) irq_enable_n = csr_wdata_int[0];
 
       // mscratch
@@ -218,7 +220,7 @@ module cs_registers
   /////////////////////////////////////////////////////////////////
 
   assign PCCR_in[0]  = 1'b1;                           // cycle counter
-  assign PCCR_in[1]  = ~stall_id_i;                    // instruction counter
+  assign PCCR_in[1]  = ~stall_id_i & is_decoding_i;    // instruction counter
   assign PCCR_in[2]  = ld_stall_i & (~stall_id_q);     // nr of load use hazards
   assign PCCR_in[3]  = jr_stall_i & (~stall_id_q);     // nr of jump register hazards
   assign PCCR_in[4]  = instr_fetch_i;                  // cycles waiting for instruction fetches
@@ -226,6 +228,8 @@ module cs_registers
   assign PCCR_in[6]  = mem_store_i;                    // nr of stores
   assign PCCR_in[7]  = jump_i   & (~stall_id_q);       // nr of jumps (unconditional)
   assign PCCR_in[8]  = branch_i & (~stall_id_q);       // nr of branches (conditional)
+  assign PCCR_in[9]  = ~stall_id_i & is_decoding_i
+                       & is_compressed_i;              // compressed instruction counter
 
   // assign external performance counters
   generate

id_stage.sv

@@ -40,6 +40,7 @@ module id_stage
 
     input logic         fetch_enable_i,
     output logic        core_busy_o,
+    output logic        is_decoding_o,
 
     // Interface to instruction memory
     input  logic [31:0] instr_rdata_i,      // comes from pipeline of IF stage
@@ -530,6 +531,7 @@ module id_stage
     .rst_n                        ( rst_n                 ),
     .fetch_enable_i               ( fetch_enable_i        ),
     .core_busy_o                  ( core_busy_o           ),
+    .is_decoding_o                ( is_decoding_o         ),
 
     // Signal from-to PC pipe (instr rdata) and instr mem system (req and ack)
     .instr_rdata_i                ( instr                 ),

include/defines.sv

@@ -389,8 +389,7 @@ endfunction // prettyPrintInstruction
 
 // Hardware loop registers
 // Caution: Changing this parameter is not sufficient to increase the number of
-// hwloop registers! There are adjustments needed in hwloop_controller and
-// controller (decoder).
+// hwloop registers! There are adjustments needed in the controller (decoder).
 `define HWLOOP_REGS 2
 
 

riscv_core.sv

@@ -89,14 +89,14 @@ module riscv_core
   logic [2:0]    pc_mux_sel_id;     // Mux selector for next PC
   logic [1:0]    exc_pc_mux_id;     // Mux selector for exception PC
 
+  // ID performance counter signals
   logic          compressed_instr;
+  logic          is_decoding;
+
 
   logic          useincr_addr_ex;   // Active when post increment
   logic          data_misaligned;   // Active when post increment
 
-
-  // Forwarding
-
   // Jump and branch target and decision (EX->IF)
   logic [31:0] jump_target_id, jump_target_ex;
   logic  [1:0] jump_in_id;
@@ -296,6 +296,7 @@ module riscv_core
     .jump_target_o                ( jump_target_id       ),
 
     .core_busy_o                  ( core_busy            ),
+    .is_decoding_o                ( is_decoding          ),
 
     // Interface to instruction memory
     .instr_rdata_i                ( instr_rdata_id       ),
@@ -540,6 +541,8 @@ module riscv_core
 
     // performance counter related signals
     .stall_id_i              ( stall_id       ),
+    .is_compressed_i         ( compressed_instr ),
+    .is_decoding_i           ( is_decoding    ),
 
     .instr_fetch_i           ( ~instr_ack_int ),