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Update lec_sv2v.sh

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NilsGraf 2020-06-19 17:07:00 -07:00
parent 31d797162c
commit f9badaf073
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syn/lec_sv2v.sh
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@ -57,7 +57,7 @@ cp ../rtl/prim_clock_gating.v .
cp ../rtl/prim_clock_gating.v prim_clock_gating.sv
#-------------------------------------------------------------------------
# run LEC (generarted Verilog vs. original SystemVerilog)
# run LEC (generated Verilog vs. original SystemVerilog)
#-------------------------------------------------------------------------
printf "\n\nLEC RESULTS:\n"