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15da12dfd6
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7c4f8b3fde4bb625ac3330ff52d3f66507190fe5 * Revert "[dv] Allow using memutil_dpi_scrambled even without prim_ram_1p_scr" (Rupert Swarbrick) * [dv] Fix some signed/unsigned comparison warnings (Rupert Swarbrick) * [dv] Make an implicit up-conversion explicit (Rupert Swarbrick) * [dv] Remove an unused array variable in prince_ref.h (Rupert Swarbrick) * [prim/security] Improve the code for prim_sparse_fsm security check (Cindy Chen) * [dv] Apply VCS option `-xprop=mmsopt` only when wave dump is off (Weicai Yang) * [all] variety of minor lint fixes (Timothy Chen) * [dv] Add options to improve VCS runtime (Weicai Yang) * [rv_dm] CSR test fixes (Srikrishna Iyer) * [dvsim] Fix pass/fail status for synthesis regression (Michael Schaffner) * [prim] Minor lint fixes for unused clocks / resets (Timothy Chen) * [dv] Flag illegal ENUMASSIGN warnings as errors (Michael Schaffner) * [flash_ctrl] Correct erase suspend interface behavior (Timothy Chen) * [rstmgr] Address several d2s review items (Timothy Chen) * [fpv/sec] Add some workaround logic for $cast keyword (Cindy Chen) * [dv] CSR seq lib - support for adapter-less RAL (Srikrishna Iyer) * [dv] Prepare codebase for UVM REG changes (Srikrishna Iyer) * [dv] Print computed CSR stuff in RAL (Srikrishna Iyer) * [dv] Allow CSR tests to run on custom RALs (Srikrishna Iyer) * [fpv/rom_ctrl] Check connectivity for alerts in rom_ctrl (Cindy Chen) * [prim] Add prim_and2 primitive (Pirmin Vogel) * [prim_dom_and_2share] Remove EnNegedge parameter (Pirmin Vogel) * [prim_dom_and_2share] Use prim_xor2 and prim_flop_en primitives (Pirmin Vogel) * [prim_dom_and_2share] Switch to single randomness input (Pirmin Vogel) * [util/dvsim] Fix confusing error message (Guillermo Maturana) * [dvsim] Minor changes to SynCfg results reporting (Michael Schaffner) * [fpv] V2S formal support (Cindy Chen) * [tools/xcelium] updated common coverage exclusions to exclude single bit correctly (Rasmus Madsen) * [dv] Clean up enable_reg_testplan (Weicai Yang) * [top] Hook-up flash/otp control and observation bus to ast (Timothy Chen) * [lint] Increase the unroll count (Eunchan Kim) * [entropy_src] Document & Implement THRESHOLD_SCOPE (Martin Lueker- Boden) * [AST] USB Observe, Clocks & POR_NI logic update (Jacob Levy) * [prim] Add new assertion macro for generating static lint errors (Pirmin Vogel) * [dv] csr_seq_lib fixes (Srikrishna Iyer) * [dv] dv_base_reg_block - Add special knobs (Srikrishna Iyer) * [dv] dv_base_mem - add special knobs (Srikrishna Iyer) * [prim] Move sec_cm assertion to an include file in prim_assert (Weicai Yang) * [flash_ctrl] Fixes for erase suspend (Timothy Chen) * [dv] exclude d_user.rsp_intg[6] for xcelium (Weicai Yang) * [prim_flop_en] Dependency fix (Michael Schaffner) * [dv] add mubi coverage for CSR and update reggen (Weicai Yang) * [prim] Add option for secure buffers in prim_mubi (Timothy Chen) * [prim] Add option for hand instantiated buffers for prim_flop_en (Timothy Chen) * [dv/shadow_reg] Move shadow_reg to V2S (Cindy Chen) * [prim_count] Updated comments to reflect all changes in lowRISC/opentitan#10378 (Michael Tempelmeier) * [dv] Teach ECC32 flavours of mem_area to write with integrity bits (Rupert Swarbrick) * [dv/shadow_reg] update milestone for shadow reg tests (Cindy Chen) * [checklists] Update V2S checklists (Srikrishna Iyer) * [tools/xcelium] updated xcelium flow to vcs for coverage test grading (Rasmus Madsen) * [prim] Add stub flops to remove lint warnings (Timothy Chen) * [dv] Add automatic covergroup for all regwen CSRs (Weicai Yang) * [dvsim] Add support for tags in testplan (Srikrishna Iyer) * [dv] Enable xcelium to include X for toggle coverage (Weicai Yang) * [dv] Clean up mem_bkdr_util__sram (Weicai Yang) * [util, testplan] Allow relative testplan imports (Srikrishna Iyer) * [prim] Add phase output to shadow register primitive (Pirmin Vogel) * [dv] Add assertion to check double_lfsr err triggers an alert (Weicai Yang) * [dv] Fix foundary failure (Weicai Yang) * [prim] update prim_count comment (Timothy Chen) * [prim_flop_2sync] Make the prim a standard non-generated prim (Michael Schaffner) * [dv/prim_max_tree] Fix xcelium compile error (Cindy Chen) * [dv] Fixes to enable foundry database pwrmgr_smoketest (Timothy Chen) * [dv] Add countermeasure verification for double_lfsr (Weicai Yang) * [dv] Update countermeasure verification (Weicai Yang) * [doc] Update V2S items (Weicai Yang) * [prim_max_tree] Remove dedicated FPV TB since all SVAs are embedded (Michael Schaffner) * [prim_max_tree/fpv] Add a simple formal testbench (Michael Schaffner) * [prim_max_tree] Create a primitive that calculates maxima (Michael Schaffner) * [dv] CSR / RAL model fixes (Srikrishna Iyer) * [uvmdvgen] bug fix (Srikrishna Iyer) * [dv] Fix some Xcelium warnings (Srikrishna Iyer) * [dv] Disable some benign warnings (Srikrishna Iyer) * [prim_mubi*_sender] Add option to omit sender flops (Michael Schaffner) * [dv, mem_bkdr_util] Fix ECC-computed backdoor WRs (Srikrishna Iyer) * [keymgr] sparsify the data control fsm (Timothy Chen) * [prim_lc_sender] Add AsyncOn parameter (Michael Schaffner) * [prim] Update behavior of prim_count (Timothy Chen) * [flash_ctrl] Minor fixes to flash foundry failure (Timothy Chen) * [sw,tests,pwrmgr] Improve synchronization (Guillermo Maturana) * [sw,tests] SRAM execution test DV integration (Dave Williams) * [dv] Update common_cov_excl to exclude d_user.rsp_intg[6] (Weicai Yang) * [otbn, dv] Added otbn_passthru_mem_tl_intg_err testcase (Prajwala Puttappa) * [rom_ctrl, dv] Fixes regression failures in rom_ctrl_passthru_mem_tl_intg_err (Prajwala Puttappa) * [dv/chip] Add jtag_csr_rw seq (Cindy Chen) * [chip dv] Remove xcelium build opt (Srikrishna Iyer) * [doc] Reorder D2S checklist items (Michael Schaffner) * [reggen] Add support for validation of RTL CM annotation (Michael Schaffner) * [all] various simple lint fixes (Timothy Chen) * [mem_bkdr,dv] Add missing type to otp_write_lc_partition_cnt (Rupert Swarbrick) * [dv/csr_utils_pkg] Clone ral map with top-level submaps (Cindy Chen) * [clkmgr] various spec and parameter updates (Timothy Chen) * [dv] Add ASSERT_NET to check net value (Weicai Yang) * [dv] revert lowRISC/opentitan#9050 and lowRISC/opentitan#9934 (Weicai Yang) * [primgen] Update AscentLint waiver in generated abstract prim wrappers (Pirmin Vogel) * [prim_generic] Fix lint errors (Pirmin Vogel) * [prim_count] Fix lint warnings (Pirmin Vogel) * [prim_alert_receiver] Fix ping during init sequence bug (Michael Schaffner) * [rom_ctrl, dv] Added passthru mem test (Prajwala Puttappa) * [prim_assert,dv] Use if condition in assert_init (Srikrishna Iyer) * [prim_filter_cnt] Make threshold runtime programmable (Michael Schaffner) * [prim_filter*] Optionally instantiate a 2-stage sync in prim_filter* (Michael Schaffner) * [dv] intg_err test cleanup and change passthru_mem_tl_intg_err to V2S (Weicai Yang) * [prim_xilinx] Replace KEEP with DONT_TOUCH attributes (Pirmin Vogel) * [sram/dv] Enable the integrity test for passthru (Weicai Yang) * [dv] Add integrity test for passthru mem (Weicai Yang) * [dv/tools] Fix alert ping exclusion (Cindy Chen) * [dv/mem_bkdr_util] added backdoor write of LC counter into LC partition in OTP (Dror Kabely) * [prim_pad_wrapper] Add dual pad wrapper for USB (Michael Schaffner) * [prim_clock_mux] Model generic mux with boolean ops (Michael Schaffner) * [prim_buf] Ensure generic primitives contain a logic cell (Michael Schaffner) * [prim_count] improved documentation and style (Michael Tempelmeier) * Revert "[dv] Replace fileset_partner flag with fileset_ast flag" (Michael Schaffner) * [dv] Replace fileset_partner flag with fileset_ast flag (Sharon Topaz) * [dv] Pass data_intg_passthru to dv_base_mem (Weicai Yang) * [dv/prim_alert] Add V3 item to testplan (Cindy Chen) * [dv/prim_count] Add an assertion to check max count stable (Cindy Chen) * [dv] Fix typo in uvmdvgen comment (Rupert Swarbrick) * [mem_bkdr_util] Use inverted integrity in rom_encrypt_write32_integ (Rupert Swarbrick) * [doc/checklist] Template fix (Cindy Chen) * [mem_bkdr_util,rom_ctrl] Fix how we call encrypt_sram_data (Rupert Swarbrick) * [rom/ram/xbar/otbn] Switch end-end bus integrity to inverted ECC codes (Michael Schaffner) * [dv/prim_alert_tb] Modify the seq to ensure alert always sends (Cindy Chen) * [dv,xcelium] Fix lowRISC/opentitan#4230: Xcelium compile error. (Timothy Trippel) * [dv/prim_alert] Add randomization in ping request sequence (Cindy Chen) * [prim_alert_receiver] Only check for ping requests after initialization (Michael Schaffner) * [doc] Update D2S checklist template and description (Michael Schaffner) * [prim_esc_receiver] Switch to standardized prim_count (Michael Schaffner) * [prim_count] Add option to disable the connection SVA (Michael Schaffner) * [otbn, rtl] Lint fixes (Greg Chadwick) * [sram/dv] Better support partial write in scb (Weicai Yang) * [dv/mem_bkdr_util] Fix ECC width error in OTP foundary test (Cindy Chen) * [secded/lint] Fix lint errors (Michael Schaffner) * [dv/prim_esc] Add more stimulus to reach coverage goal (Cindy Chen) * [alert_handler] Switch to sparse fsm primitive (Michael Schaffner) * [prim_sparse_fsm_flop] Add a parameter to disable SVA (Michael Schaffner) Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org> |
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| .. | ||
| lint | ||
| rtl | ||
| BUILD | ||
| prim_xilinx_and2.core | ||
| prim_xilinx_buf.core | ||
| prim_xilinx_clock_buf.core | ||
| prim_xilinx_clock_gating.core | ||
| prim_xilinx_clock_mux2.core | ||
| prim_xilinx_flop.core | ||
| prim_xilinx_flop_en.core | ||
| prim_xilinx_pad_attr.core | ||
| prim_xilinx_pad_wrapper.core | ||
| prim_xilinx_xor2.core | ||