mirror of
https://github.com/openhwgroup/cve2.git
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44393eb863
* [rtl] Changed the default number of performance counters from 0 to 10 (#214) * Implementation of sequential equivalence checking option using Yosys EQY. * [sec] Automatic removal of new IO when performing SEC against (current) golden design with Yosys EQY
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990 B
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43 lines
No EOL
990 B
Text
# Build output
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build
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buildsim.log
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# Common editor/IDE config and temporary files
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.project
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.vscode/
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.sw[a-p]
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tags
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*~
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# ibex_tracer log file
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trace_core_*.log
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# Simple system output files
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ibex_simple_system.log
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ibex_simple_system_pcount.csv
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# Python cache files
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__pycache__
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# This is generated by VCS when running DV simulations with WAVE=1.
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/dv/uvm/core_cve2/ucli.key
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# This is generated by UVM when running simulations and doesn't seem
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# to be something you can disable.
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/dv/uvm/core_cve2/tr_db.log
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# This is the default output directory in dv/uvm/core_cve2 and
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# contains auto-generated files from building and running tests.
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/dv/uvm/core_cve2/out
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# This is generated by Questa tool when running DV simulations
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modelsim.ini
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# This is generated by Xcelium when running DV simulations, even with WAVE=0
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/dv/uvm/core_cve2/waves.shm
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# This is generated by the sequential equivalent checking
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/scripts/sec/golden.src
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/scripts/sec/revised.src
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/scripts/sec/reports
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/scripts/sec/ref_design |