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3fcf5a634d
Update code from upstream repository https://github.com/google/riscv- dv to revision c98d89cdff7b56d9911904e05e6b46e005233280 * Interrupt test integration (Udi) * Update README for illegal/hint instruction (google/riscv-dv#155) (taoliug) * Refactor illegal/hint instruction generation (google/riscv-dv#154) (taoliug) * Skip x0 in GPR save/restore (google/riscv-dv#153) (taoliug) * Move user_define.h to the beginning of the program (google/riscv- dv#151) (taoliug) * Add user_define.h (google/riscv-dv#149) (taoliug) * Move instr_bin to a separate section (google/riscv-dv#148) (taoliug) * Remove temp files (google/riscv-dv#145) (taoliug) * Move dv_defines.svh outside the package (google/riscv-dv#144) (taoliug) * Fix typo (google/riscv-dv#141) (taoliug) * Refactored loop instruction stream, reduce global reserved registers (google/riscv-dv#139) (taoliug) * Remove obsolete sample program (google/riscv-dv#138) (taoliug) * Update readme (google/riscv-dv#137) (taoliug) * Skip kernel instruction/data pages when not needed (google/riscv- dv#136) (taoliug) * Re-organize data page generation (google/riscv-dv#135) (taoliug) * Re-organize text and data section (google/riscv-dv#134) (taoliug) * Refine the bare program mode (google/riscv-dv#133) (taoliug) * Add a bare program mode (google/riscv-dv#130) (taoliug) * Allow running riscv-dv from other directories (google/riscv-dv#128) (taoliug) * Fix trace compare issue (google/riscv-dv#123) (taoliug) * Optimize for constraint solving performance (google/riscv-dv#122) (taoliug) * Avoid ISS simulation timeout (google/riscv-dv#121) (taoliug) * Optimize irun randomization performance (google/riscv-dv#120) (taoliug) * fix ius compile/simulation warnings (Tao Liu) * Fix ius compilation failure (Tao Liu) * Fix google/riscv-dv#109 ius constraint solver failure (Tao Liu) * Add ebreak sequence generation and cmdline options (Udi) * Added dret instruction to random generation (Udi) * Tighten up regex in spike log tracer. (Dave Estes) * Fix generation of debug handshake (Udi) * Fix wfi generation, add indent to core_initialization handshake (Udi)
23 lines
849 B
FortranFixed
23 lines
849 B
FortranFixed
// Copyright 2018 Google LLC
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// HEADERS
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+incdir+${RISCV_DV_ROOT}/src
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+incdir+${RISCV_DV_ROOT}/test
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// SOURCES
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${RISCV_DV_ROOT}/src/riscv_signature_pkg.sv
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${RISCV_DV_ROOT}/src/riscv_instr_pkg.sv
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${RISCV_DV_ROOT}/test/riscv_instr_test_pkg.sv
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${RISCV_DV_ROOT}/test/riscv_instr_gen_tb_top.sv
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