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* update vendor.hjson to exclude generated pdf file * Update google_riscv-dv to google/riscv-dv@d23da38 Update code from upstream repository https://github.com/google/riscv- dv to revision d23da3862f95954e6374aaec787e0fb0c1878a16 * fix matched_list and directed_list size comparisons (Udi Jonnalagadda) * Add run_cmd_output for reporting all debug command lines (google/riscv-dv#436) (Hai Hoang Dang) * Resolve: missing pass gcc_opts from YAML for GCC compile command (google/riscv-dv#435) (Hai Hoang Dang) * Sphinx: Add generating pdf file (google/riscv-dv#431) (Hai Hoang Dang) * integrate directed asm_tests with yaml flow (Udi Jonnalagadda) * Fix running cov without arguments (google/riscv-dv#433) (Hai Hoang Dang) * Add setup Travis CI for tracking build docs, and install (google/riscv-dv#430) (Hai Hoang Dang) * Add handling KeyboardInterrupt for run_cmd and run_parallel_cmd (google/riscv-dv#424) (Hai Hoang Dang) * Sphinx: add basic page for structure of the document (google/riscv- dv#428) (Hai Hoang Dang) * README.md: Update the information relating to usage (google/riscv- dv#426) (Hai Hoang Dang) * Add initial Sphinx docs (google/riscv-dv#427) (Hai Hoang Dang) * Fix typo in the testlist (google/riscv-dv#423) (taoliug) * Add try-except for handling KeyboardInterrupt (google/riscv-dv#421) (Hai Hoang Dang) * Update information about instruction for running scripts (google/riscv-dv#420) (Hai Hoang Dang) * Add vector permutation, reduction, mask instructions (google/riscv- dv#422) (taoliug) * Python package (google/riscv-dv#419) (Hai Hoang Dang) * Refactor the code for cov.py (google/riscv-dv#416) (Hai Hoang Dang) * Update ovpsim config for vector extesion (google/riscv-dv#415) (taoliug) * Fix coverage flow issue (google/riscv-dv#414) (taoliug) * Add missing license header (google/riscv-dv#412) (taoliug) * Fix typo in cov_test (google/riscv-dv#410) (taoliug) * Add vector floating point instructions (google/riscv-dv#409) (taoliug) * Add fixed point arithmetic vector instruction (google/riscv-dv#408) (taoliug) * cov.py: Generate error when it cannot find spike_sim directory (google/riscv-dv#407) (Hai Hoang Dang) * Add vector CSR initialization routine (google/riscv-dv#405) (taoliug) * Create vector extension target, add basic enums (google/riscv- dv#404) (taoliug) * Fix qrun sim warning (google/riscv-dv#402) (taoliug) * Try fix qrun constraint solver issue (google/riscv-dv#401) (taoliug) * Fix simulation warning (google/riscv-dv#400) (taoliug) * run.py: Generate error for gcc compile when it cannot find assembly files (google/riscv-dv#398) (Hai Hoang Dang) * Add numeric corner case test, misc coverage fixes (google/riscv- dv#396) (taoliug) * Switch to new CSV format (google/riscv-dv#395) (taoliug) * misc fixes for the coverage model (google/riscv-dv#394) (taoliug) * Fix new CSV coverage flow issue (google/riscv-dv#392) (taoliug) * Integrate new trace CSV format with coverage flow (google/riscv- dv#390) (taoliug) * Add experimental script for the new CSV format (google/riscv-dv#389) (taoliug) * Support flexible running directed assembly tests (google/riscv- dv#386) (Hai Hoang Dang) * run.py: Enhance passing argument for gen function (google/riscv- dv#382) (Hai Hoang Dang) * Fix qrun issue, take 2 (google/riscv-dv#384) (taoliug) * Attempt to fix qrun issue (google/riscv-dv#383) (taoliug) * Fix (google/riscv-dv#381) (taoliug) * Fix typo (google/riscv-dv#380) (taoliug) * Fix qrun simulation issue (google/riscv-dv#379) (taoliug) * Cleaning the output directory by default. Using exist output directory (google/riscv-dv#377) (Hai Hoang Dang) * Fix ius compilation error temporarily (google/riscv-dv#378) (taoliug) * Functional coverage improvement (google/riscv-dv#376) (taoliug) * Add unaligned jump instruction support (google/riscv-dv#375) (taoliug) * move handcoded asm_test generation into separate output directory (Udi Jonnalagadda) * Ignore return code for ovpsim sim (google/riscv-dv#371) (taoliug) * Fix mie compare mismatch (google/riscv-dv#370) (taoliug) * Fix directory/file name for assembly test flow (google/riscv-dv#369) (taoliug) * Fix error in README (google/riscv-dv#368) (taoliug) * Add sample rv32imc test (google/riscv-dv#367) (taoliug) * Fix typo (google/riscv-dv#366) (taoliug) * Support running regression with hand-coded assembly tests (google/riscv-dv#365) (taoliug) Signed-off-by: Udi <udij@google.com>
25 lines
769 B
INI
25 lines
769 B
INI
[metadata]
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name = riscv-dv
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description = "RISCV-DV is a SV/UVM instruction generator for RISC-V processor verification."
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long_description = file: README.md
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version = 1.0
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author = Google, Inc.
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author_email = riscv_dv_dev@google.com.
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license = LICENSE.txt
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url = https://github.com/google/riscv-dv.git
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[options]
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# Automatically find all files beneath the riscv-dv directory and include them.
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packages = find:
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# Parse the MANIFEST.in file and include those files.
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include_package_data = True
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# Let pip install dependencies automatically.
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install_requires = PyYAML
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bitstring
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python_requires = >=3
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[options.entry_points]
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# Set up an executable script that calls the main() function in riscv-dv
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console_scripts =
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run = run:main
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cov = cov:main
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