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https://github.com/openhwgroup/cve2.git
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066ff47261
* remove parameter BranchPredictor Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * Remove references to the removed parameter(s) from examples Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remove references to the removed parameters from compliance verification Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remove references to the removed parameters from core lists Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remove references to the removed parameters from the example configurations Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * Remove references to the removed parameter from documentation Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * Remove related and dead code Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> --------- Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
63 lines
2.5 KiB
Text
63 lines
2.5 KiB
Text
///////////////////////////////////////////////////////////////////////////////
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//
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// Copyright 2022 OpenHW Group
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//
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// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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///////////////////////////////////////////////////////////////////////////////
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//
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// Manifest for the CV32E20 RTL model.
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// - Format based on manifest used by other CORE-V cores.
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// - Intended to be used by both synthesis and simulation.
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// - Relevent synthesis and simulation scripts/Makefiles must set the shell
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// ENV variable DESIGN_RTL_DIR as required.
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//
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// TODO: Replace once-and-for-all with unified manifest (FuseSoc?)
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//
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///////////////////////////////////////////////////////////////////////////////
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+incdir+${DESIGN_RTL_DIR}/../shared/rtl/
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+incdir+${DESIGN_RTL_DIR}/../rtl
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+incdir+${DESIGN_RTL_DIR}/../shared/rtl/sim
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+incdir+${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl
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+incdir+${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/dv/sv/dv_utils
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${DESIGN_RTL_DIR}/cve2_pkg.sv
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${DESIGN_RTL_DIR}/cve2_tracer_pkg.sv
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${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
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${DESIGN_RTL_DIR}/../vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
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${DESIGN_RTL_DIR}/cve2_alu.sv
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${DESIGN_RTL_DIR}/cve2_compressed_decoder.sv
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${DESIGN_RTL_DIR}/cve2_controller.sv
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${DESIGN_RTL_DIR}/cve2_cs_registers.sv
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${DESIGN_RTL_DIR}/cve2_csr.sv
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${DESIGN_RTL_DIR}/cve2_counter.sv
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${DESIGN_RTL_DIR}/cve2_decoder.sv
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${DESIGN_RTL_DIR}/cve2_ex_block.sv
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${DESIGN_RTL_DIR}/cve2_fetch_fifo.sv
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${DESIGN_RTL_DIR}/cve2_id_stage.sv
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${DESIGN_RTL_DIR}/cve2_if_stage.sv
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${DESIGN_RTL_DIR}/cve2_load_store_unit.sv
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${DESIGN_RTL_DIR}/cve2_multdiv_fast.sv
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${DESIGN_RTL_DIR}/cve2_multdiv_slow.sv
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${DESIGN_RTL_DIR}/cve2_prefetch_buffer.sv
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${DESIGN_RTL_DIR}/cve2_pmp.sv
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${DESIGN_RTL_DIR}/cve2_register_file_ff.sv
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${DESIGN_RTL_DIR}/cve2_wb.sv
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${DESIGN_RTL_DIR}/cve2_core.sv
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${DESIGN_RTL_DIR}/cve2_top.sv
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${DESIGN_RTL_DIR}/cve2_top_tracing.sv
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${DESIGN_RTL_DIR}/cve2_tracer.sv
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${DESIGN_RTL_DIR}/../bhv/cve2_sim_clock_gate.sv
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