mirror of
https://github.com/openhwgroup/cve2.git
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3a9f2d058f
* remove parameter option WritebackStage Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remove references to the removed parameters from examples Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remove references to the removed parameters from compliance verification Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * remove references to the removed parameters from formal verification code generated for SymbioticEDA Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * Remove reference to the deleted parameterd from the documentation Do not refer to WriteBack as to a stage Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * Remove related code to Writeback stage Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * Removal of related and dead code after Writeback-stage removal Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * substitute ASSERT macro with one ignoring rst_ni and clk signals Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * keep clk_i and rst_ni for the sake of assert alone Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> * BUGFIX: reintroduce en_wb signal between id and wb Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> --------- Signed-off-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com> Co-authored-by: Szymon Bieganski <szymon.bieganski@oss.nxp.com>
59 lines
1,002 B
YAML
59 lines
1,002 B
YAML
cve2:
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incdirs: [
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rtl,
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shared/rtl,
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]
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files: [
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rtl/cve2_pkg.sv,
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rtl/cve2_alu.sv,
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rtl/cve2_compressed_decoder.sv,
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rtl/cve2_controller.sv,
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rtl/cve2_cs_registers.sv,
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rtl/cve2_counters.sv,
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rtl/cve2_decoder.sv,
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rtl/cve2_ex_block.sv,
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rtl/cve2_id_stage.sv,
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rtl/cve2_if_stage.sv,
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rtl/cve2_wb.sv,
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rtl/cve2_load_store_unit.sv,
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rtl/cve2_multdiv_slow.sv,
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rtl/cve2_multdiv_fast.sv,
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rtl/cve2_prefetch_buffer.sv,
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rtl/cve2_fetch_fifo.sv,
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rtl/cve2_pmp.sv,
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rtl/cve2_core.sv,
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shared/rtl/prim_assert.sv,
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]
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cve2_vip_rtl:
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targets: [
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rtl,
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]
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incdirs: [
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]
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files: [
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rtl/cve2_pkg.sv,
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rtl/cve2_tracer_pkg.sv,
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rtl/cve2_tracer.sv,
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rtl/cve2_core_tracing.sv,
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]
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cve2_regfile_rtl:
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targets: [
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rtl,
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tsmc55,
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gf22
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]
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incdirs: [
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]
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files: [
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rtl/cve2_register_file_latch.sv,
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]
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cve2_regfile_fpga:
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targets: [
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xilinx,
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]
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incdirs: [
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]
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files: [
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rtl/cve2_register_file_fpga.sv,
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]
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